John Wawrzynek
#54,110
Most Influential Person Now
American computer scientist
John Wawrzynek's AcademicInfluence.com Rankings
John Wawrzynekcomputer-science Degrees
Computer Science
#2127
World Rank
#2210
Historical Rank
#971
USA Rank
Computer Architecture
#25
World Rank
#25
Historical Rank
#20
USA Rank
Database
#7972
World Rank
#8306
Historical Rank
#1026
USA Rank
John Wawrzynekengineering Degrees
Engineering
#4469
World Rank
#5665
Historical Rank
#1111
USA Rank
Electrical Engineering
#2545
World Rank
#2667
Historical Rank
#327
USA Rank
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Computer Science Engineering
John Wawrzynek's Degrees
- PhD Electrical Engineering and Computer Science University of California, Berkeley
- Masters Electrical Engineering and Computer Science University of California, Berkeley
- Bachelors Electrical Engineering and Computer Science University of California, Berkeley
Why Is John Wawrzynek Influential?
(Suggest an Edit or Addition)According to Wikipedia, John Wawrzynek is Professor of Electrical Engineering and Computer Sciences at the University of California at Berkeley. He holds a joint appointment with Lawrence Berkeley National Laboratory and is the Chief Faculty Director of the Berkeley Wireless Research Center. He is currently a principal researcher in multiple large research centers at UC Berkeley including Algorithms and Specializers for Provably Optimal Implementations with Resilience and Efficiency , the Parallel Computing Laboratory , and the TerraSwarm Research Center.
John Wawrzynek's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Garp: a MIPS processor with a reconfigurable coprocessor (1997) (963)
- Chisel: Constructing hardware in a Scala embedded language (2012) (688)
- A view of the parallel computing landscape (2009) (653)
- The Garp Architecture and C Compiler (2000) (449)
- Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine (1991) (340)
- BEE2: a high-end reconfigurable computing system (2005) (322)
- Silicon Auditory Processors as Computer Peripherals (1992) (251)
- RAMP: Research Accelerator for Multiple Processors (2007) (215)
- The Cloud is Not Enough: Saving IoT from the Cloud (2015) (212)
- Reconfigurable computing: what, why, and implications for design automation (1999) (193)
- Vector microprocessors (1998) (170)
- HSRA: high-speed, hierarchical synchronous reconfigurable array (1999) (132)
- Stream Computations Organized for Reconfigurable Execution (SCORE) (2000) (131)
- Fast module mapping and placement for datapaths in FPGAs (1998) (120)
- AWStream: adaptive wide-area streaming analytics (2018) (117)
- Instruction-Level Parallelism for Reconfigurable Computing (1998) (116)
- Spert-II: A Vector Microprocessor System (1996) (112)
- The Swarm at the Edge of the Cloud (2015) (99)
- RAMP Blue: A Message-Passing Manycore System in FPGAs (2007) (98)
- Localization as a feature of mmWave communication (2016) (96)
- Adapting software pipelining for reconfigurable computing (2000) (88)
- Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018) (84)
- Stream computations organized for reconfigurable execution (2006) (81)
- Post-placement C-slow retiming for the xilinx virtex FPGA (2003) (71)
- A case for network musical performance (2001) (70)
- The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View (2008) (65)
- A multi-sender asynchronous extension to the AER protocol (1995) (64)
- PetaOp/Second FPGA Signal Processing for SETI and Radio Astronomy (2006) (63)
- The swarm at the edge of the cloud - A new perspective on wireless (2011) (61)
- High-throughput bayesian computing machine with reconfigurable hardware (2010) (60)
- MARC: A Many-Core Approach to Reconfigurable Computing (2010) (60)
- Hardware-assisted fast routing (2002) (58)
- Object oriented circuit-generators in Java (1998) (57)
- The design of a neuro-microprocessor (1993) (56)
- Research accelerator for multiple processors (2006) (53)
- Active messages: an efficient communication architecture for multiprocessors (1993) (49)
- Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial (2000) (46)
- Augmenting a microprocessor with reconfigurable hardware (2000) (44)
- Systems technologies for silicon auditory models (1994) (44)
- OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices (2010) (43)
- Stream Computations Organized for Reconfigurable Execution (SCORE) Extended Abstract (2000) (40)
- A Comparison of the AES Candidates Amenability to FPGA Implementation (2000) (38)
- CoSA: Scheduling by Constrained Optimization for Spatial Accelerators (2021) (35)
- A Streaming Multi-Threaded Model (2001) (30)
- The TerraSwarm Research Center (TSRC) (A White Paper) (2012) (29)
- AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning (2020) (28)
- GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs (2019) (28)
- CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs (2021) (27)
- AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning (2019) (27)
- ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism (2015) (26)
- Automatic compilation of c for hybrid reconfigurable architectures (2002) (26)
- Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine (2002) (25)
- Toward a Global Data Infrastructure (2016) (25)
- The SFRA: a corner-turn FPGA architecture (2004) (24)
- RAMP Blue : Implementation of a Manycore 1008 Processor FPGA System (2008) (23)
- Workloads of the Future (2008) (23)
- Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling (2010) (23)
- A micropower analog circuit implementation of hidden Markov model state decoding (1997) (22)
- VLSI models for sound synthesis (1989) (22)
- Low-Power Silicon Neurons, Axons, and Synapses (1993) (21)
- Stochastic, spatial routing for hypergraphs, trees, and meshes (2003) (21)
- Bridging the GPGPU-FPGA efficiency gap (2011) (20)
- T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines (1996) (20)
- The design and applications of BEE2: A high end reconfigurable computing system (2005) (19)
- A design methodology for domain-optimized power-efficient supercomputing (2009) (19)
- Reconfigurable Computing: What, Why, Design Automation Requirements (1999) (17)
- CNS-1 Architecture Specification (1993) (17)
- A supercomputer for neural computation (1994) (16)
- Using simulations of reduced precision arithmetic to design a neuro-microprocessor (1993) (16)
- ProTuner: Tuning Programs with Monte Carlo Tree Search (2020) (16)
- SPERT: a VLIW/SIMD microprocessor for artificial neural network computations (1992) (16)
- ZUMA: A platform for smart-home environmnents (2006) (16)
- ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs (2010) (15)
- Design automation for streaming systems (2005) (15)
- JPEG Quality Transcoding Using Neural Networks Trained with a Perceptual Error Measure (1999) (15)
- HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference (2021) (15)
- A New Discipline for CMOS Design: an Architecture for Sound Synthesis (1985) (14)
- SPERT-II: a vector microprocessor system and its application to large problems in backpropagation training (1995) (14)
- On the opportunity to improve system yield with multi-core architectures (2007) (14)
- Speech Recognition Experiments with Silicon Auditory Models (1997) (14)
- Exploiting Memory-Level Parallelism in Reconfigurable Accelerators (2012) (13)
- Defect tolerance in multiple-FPGA systems (2005) (13)
- Exploring Many-Core Design Templates for FPGAs and ASICs (2012) (13)
- ZUMA: A platform for smart-home environments the case for infrastructure (2006) (13)
- A Micropower Analog VLSI HMM State Decoder for Wordspotting (1996) (12)
- Designing A Connectionist Network Supercomputer (1993) (11)
- A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle (2017) (10)
- Stochastic spatial routing for reconfigurable networks (2006) (10)
- Subtractive Synthesis without Filters (2007) (10)
- Using adaptive routing to compensate for performance heterogeneity (2009) (10)
- RTP Payload Format for MIDI (2004) (10)
- Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations (2010) (9)
- Electronic system for synthesizing and combining voices of musical instruments (1988) (9)
- High Level Synthesis with a Dataflow Architectural Template (2016) (9)
- AWStream (2018) (9)
- Exploring FPGA Routing Architecture Stochastically (2010) (9)
- A two-dimensional topological compactor with octagonal geometry (1991) (8)
- An Implementation Guide for RTP MIDI (2006) (8)
- Architectural synthesis of computational pipelines with decoupled memory access (2014) (8)
- A fixed-point recursive digital oscillator for additive synthesis of audio (1999) (8)
- CNS-1 Architecture Specification A Connectionist Network Supercomputer (1993) (7)
- Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration (2019) (7)
- Synthesis of statically analyzable accelerator networks from sequential programs (2016) (7)
- Toward standardized localization service (2016) (7)
- Algorithm-hardware Co-design for Deformable Convolution (2019) (7)
- A VLSI Architecture for Sound Synthesis (1984) (6)
- The effects of datapath placement and C-slow retiming on three computational benchmarks (2002) (6)
- Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience (2012) (6)
- SPERT: a VLIW/SIMD neuro-microprocessor (1992) (6)
- Compressive sensing and sparse antenna arrays for indoor 3-D microwave imaging (2017) (6)
- Spert-II : A Vector Micro Processore System, Special Issue of Neural Computing in (1996) (6)
- Reconfigurable computing in the era of post-silicon scaling [panel discussion] (2013) (5)
- Hierarchical Synchronous Recon gurable Array (1999) (5)
- Silicon Models for Auditory Scene Analysis (1995) (5)
- Selection and Aggregation of Location Information Provisioning Services (2017) (5)
- Hardware-assisted fast routing for runtime reconfigurable computing (2004) (5)
- Energy Efficient Antenna Arrays for Indoor 3-D Microwave Imaging (2016) (5)
- AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning (2019) (5)
- A VLSI Approach to Sound Synthesis (1984) (5)
- Discriminatively Fortified Computing with Reconfigurable Digital Fabric (2011) (4)
- SPERT: a neuro-microprocessor (1995) (4)
- Rethinking FPGA Computing with a Many-Core Approach (2010) (4)
- Simple Profiling System for SUIF (1996) (4)
- OLAF'16: Second International Workshop on Overlay Architectures for FPGAs (2016) (4)
- The sfra: a fixed frequency fpga architecture (2003) (4)
- Compiling MPEG 4 structured audio into C (2001) (4)
- The T0 Vector Microprocessor (2011) (4)
- Programming Streaming FPGA Applications Using Block Diagrams in Simulink (2008) (4)
- VLSI concurrent computation for music synthesis (1987) (4)
- The Center for New Music and Audio Technologies (1989) (4)
- HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing (2019) (4)
- A Universal Processor for RAMP (2006) (4)
- The Parallel Computing Laboratory at U . C . (2008) (3)
- Real products, real technology Guest Editor's Introduction] (1999) (3)
- SLSR: A flexible middleware localization service architecture (2017) (3)
- Characterization of three-dimensional near-field microwave imaging algorithms for stationary and moving objects (2016) (3)
- SURVEY OF ONLINE HARDWARE TASK SCHEDULING AND PLACEMENT ALGORITHMS FOR PARTIALLY RECONFIGURABLE COMPUTING SYSTEMS (2012) (3)
- A topological framework for compaction and routing (1991) (2)
- Adventures with a Reconfigurable Research Platform (2007) (2)
- The Design And Application Of A High-End Reconfigurable Computing System (2005) (2)
- Synetgy (2019) (2)
- BEE 2 : a multi-purpose computing platform for radio telescope signal processing applications (2004) (2)
- Spert-II: A Vector Microprocessor (1996) (2)
- Development of a Connectionist Network Supercomputer (1993) (2)
- Datapath-oriented FPGA mapping and placement for configurable computing (1997) (2)
- Balancing computation and memory in high capacity reconfigurable arrays (2000) (2)
- Should the academic community launch an open-source FPGA device and tools effort?: evening panel (2011) (2)
- VLSI Parallel Processing for Musical Sound Synthesis (1990) (2)
- SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays (2020) (1)
- MIMIC, A Custom VLSI Parallel Processor for Musical Sound Synthesis (1990) (1)
- Anawake : Signal-Based Power Management For Digital Signal Processing Systems (2006) (1)
- Extracting memory-level parallelism through reconfigurable hardware traces (2013) (1)
- Quality based compute-resource allocation in real-time signal processing (2003) (1)
- Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture (2009) (1)
- A Reconfigurable HEC Platform (2003) (1)
- Complexity-quality tradeoffs for real-time signal compression (2005) (1)
- Design in the Late-and Post-Silicon Eras (2009) (1)
- Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design (2022) (1)
- CoDeNet: Algorithm-hardware Co-design for Deformable Convolution (2020) (1)
- High speed 64-b CMOS datapath (1993) (1)
- Synthesis of program binaries into FPGA accelerators with runtime dependence validation (2017) (1)
- A Multimedia Digital Signal Processing Tutoring System (1990) (1)
- BEE2: Reconfigurable Computing System (2005) (0)
- System on a Chip Real-Time Emulation (SOCRE) (2006) (0)
- Using many-core architectural templates for FPGA-based computing (abstract only) (2011) (0)
- Development of a Connectionist Network Supercomputer1 (1993) (0)
- Memory management in the programming language ICL (1983) (0)
- Today ’ s lecture : More on power and energy Histogram filters Face detection Diffusion processing (2012) (0)
- Theme Feature Spert-II : A Vector Microprocessor System (1996) (0)
- Energy Efficient Antenna Arrays for Indoor Three-dimensional Microwave Imaging (2016) (0)
- Session details: Simulation acceleration (2008) (0)
- Receiver Adaptive Beamforming and Interference of Indoor Environments in mmWave (2018) (0)
- Cl ou d St or ag e Toward a Global Data Infrastructure (2016) (0)
- MWPP: A resilient MIDI RTP packetization for network musical performance (2001) (0)
- Compute-resource allocation for motion estimation in real-time video compression (2003) (0)
- Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010 (2010) (0)
- Spectrum Access System : Comparison of Different Equalizers (2017) (0)
- Third Time ’ s The Charm : Designing & Building RDLC (0)
- Intel Sandy Bridge : IDF 2010 All on chip : 4 x 86 cores GPU North Bridge DRAM controller On chip ring network 2 (2010) (0)
- Automatically updating technology dependent information in design automation (1993) (0)
- Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016) (2016) (0)
- Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017) (2017) (0)
- Session details: Tools and architectures for power minimization (2004) (0)
- A Tilt Filter in a Servo Loop (2012) (0)
- Accelerator Systems for Neural Networks, Speech, and Related Applications. (1995) (0)
- 1997 EECS/ERL research summary (1997) (0)
- Accelerating Science Driven System Design With RAMP (2015) (0)
- Antenna Array Geometries for Directional Wireless Networks (2019) (0)
- Improving FPGA Placement with Dynamically (2010) (0)
- OLAF'17: Third International Workshop on Overlay Architectures for FPGAs (2017) (0)
- Advances and challenges of computing with FPGAs (2011) (0)
- Provisions Relating to IETF Documents (2009) (0)
- Session details: Computation techniques for FPGAs (2005) (0)
- Connectionist Network Supercomputer Project (1994) (0)
- A Supercomputer for Neural (1994) (0)
- Session details: Application 1 (2006) (0)
- Network Working Group an Implementation Guide for Rtp Midi an Implementation Guide for Rtp Midi (2006) (0)
- A Comparison of FPGA Implementations of Two ’ s Complement Bit-Level and Word-Level Matrix Multipliers (2001) (0)
- Complementary-Logic Fault Detector (1985) (0)
- NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads (2018) (0)
- Session details: Panel (2011) (0)
- Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics (2003) (0)
- A Collaborative Research Proposal to the NSF: Research Accelerator for Multiple Processors (RAMP) - A Shared Experimental Parallel HW/SW Platform (2008) (0)
- A Streaming Multi-Threaded Model Extended (2001) (0)
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John Wawrzynek is affiliated with the following schools:
