A. Richard Newton
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A. Richard Newtonengineering Degrees
Engineering
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Electrical Engineering
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Engineering
A. Richard Newton's Degrees
- PhD Electrical Engineering University of California, Berkeley
- Masters Electrical Engineering University of California, Berkeley
- Bachelors Electrical Engineering University of California, Berkeley
Why Is A. Richard Newton Influential?
(Suggest an Edit or Addition)A. Richard Newton's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas (1990) (1163)
- System-Level Design: Orthogonalization of Concerns and Platform-Based Design (2001) (794)
- System-level design: orthogonalization of concerns andplatform-based design (2000) (415)
- MUSTANG: state assignment of finite state machines targeting multilevel logic implementations (1988) (277)
- A simple MOSFET model for circuit analysis (1991) (269)
- Algorithms for hardware allocation in data path synthesis (1989) (257)
- Delay analysis of series-connected MOSFET circuits (1991) (245)
- Relaxation-based electrical simulation (1983) (232)
- Test generation for sequential circuits (1988) (186)
- Sketched symbol recognition using Zernike moments (2004) (157)
- From ASIC to ASIP: the next design discontinuity (2002) (141)
- An empirical evaluation of two memory-efficient directory methods (1990) (138)
- Exact algorithms for output encoding, state assignment, and four-level Boolean minimization (1991) (137)
- An Algorithm for Optimal PLA Folding (1982) (128)
- Electronic CAD Frameworks (1992) (127)
- Logic synthesis for large pass transistor circuits (1997) (124)
- Test generation and verification for highly sequential circuits (1991) (116)
- Decomposition and factorization of sequential finite state machines (1988) (109)
- Sequential Logic Synthesis (1991) (109)
- Techniques for the simulation of large-scale integrated circuits (1979) (91)
- A cell-replicating approach to minicut-based circuit partitioning (1991) (90)
- A synthesis and optimization procedure for fully and easily testable sequential machines (1989) (87)
- On The Verification of Sequential Machines at Differing Levels of Abstraction (1987) (87)
- MUSE: a multilevel symbolic encoding algorithm for state assignment (1990) (86)
- Analysis of performance and convergence issues for circuit simulation (1989) (85)
- Irredundant sequential machines via optimal logic synthesis (1990) (84)
- Test generation for highly sequential circuits (1989) (84)
- Don't care minimization of multi-level sequential logic networks (1990) (82)
- Limitations and challenges of computer-aided design technology for CMOS VLSI (2001) (75)
- An incomplete scan design approach to test generation for sequential machines (1988) (66)
- Design and specification of embedded systems in Java using successive, formal refinement (1998) (65)
- Design management based on design traces (1991) (62)
- Robust sketched symbol fragmentation using templates (2004) (61)
- Recognition and beautification of multi-stroke symbols in digital ink (2005) (58)
- Optimum and heuristic algorithms for an approach to finite state machine decomposition (1991) (56)
- The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation (1989) (56)
- Fast simulated diffusion: an optimization algorithm for multi-minimum problems and its application to MOSFET model parameter extraction (1991) (54)
- Topological Optimization of Multiple-Level Array Logic (1987) (52)
- Sequential Logic Testing and Verification (1991) (50)
- Mixed-mode simulation and analog multilevel simulation (1994) (50)
- Algorithms for the transient simulation of lossy interconnect (1994) (49)
- WELD—an environment for Web-based electronic design (1998) (47)
- Redundancies and don't cares in sequential logic synthesis (1989) (46)
- Computer-Aided Design for VLSI Circuits (1986) (46)
- Relaxation-Based Electrical Simulation (1983) (46)
- The simulation of large scale integrated circuits (1978) (44)
- Techniques for Programmable Logic Array Folding (1982) (40)
- Synthesis and optimization procedures for fully and easily testable sequential machines (1988) (39)
- Boolean decomposition in multilevel logic optimization (1989) (39)
- Papers on Twenty-five years of electronic design automation (1988) (38)
- Sequential test generation and synthesis for testability at the register-transfer and logic levels (1993) (38)
- Implicit manipulation of equivalence classes using binary decision diagrams (1991) (36)
- A unified approach to the decomposition and re-decomposition of sequential machines (1990) (34)
- Boolean decomposition in multi-level logic optimization (1988) (33)
- The future of logic synthesis and physical design in deep-submicron process geometries (1997) (33)
- SPICE3 Version 3f3 User s Manual (1993) (31)
- Design aids for VLSI: The Berkeley perspective (1981) (30)
- Electrical-logic simulation and its applications (1989) (28)
- An accuration delay modeling technique for switch-level timing verification (1986) (28)
- Sequential test generation at the register-transfer and logic levels (1990) (27)
- A simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFETs (1990) (27)
- Boolean decomposition of programmable logic arrays (1988) (26)
- A modified approach to two-level logic minimization (1988) (26)
- A Symbolic Design System for Integrated Circuits (1982) (26)
- Heuristic minimization of Boolean relations using testing techniques (1990) (26)
- Reduced offsets for minimization of binary-valued functions (1991) (25)
- Timing, Logic and Mixed-Mode Simulation for Large MOS Integrated Circuits (1984) (24)
- Retargetable estimation scheme for DSP architecture selection (2000) (23)
- Computer-aided design of VLSI circuits (1981) (22)
- Analysis Time, Accuracy And Memory Requirement Tradeoffs In Spice2 (1977) (22)
- GENIE: A Generalized Array Optimizer for VLSI Synthesis (1986) (22)
- EDA and the network (1997) (21)
- KIC2: A Low-Cost, Interactive Editor for Integrated Circuit Design (1982) (21)
- A disciplined approach to the development of platform architectures (2002) (20)
- An impulse-response based linear time-complexity algorithm for lossy interconnect simulation (1991) (20)
- Optimum and heuristic algorithms for finite state machine decomposition and partitioning (1989) (20)
- Critic: a knowledge-based program for critiquing circuit designs (1988) (18)
- Symbolic Layout and Procedural Design (1987) (16)
- Exact Redundant State Registers Removal Based on Binary Decision Diagrams (1991) (16)
- An estimation technique to guide low power resynthesis algorithms (1995) (16)
- Verification of interacting sequential circuits (1990) (15)
- CAD tools for ASIC design (1987) (15)
- A generalized approach to the constrained cubical embedding problem (1989) (15)
- Exact algorithms for output encoding, state assignment and four-level Boolean minimization (1990) (14)
- Basic Definitions and Concepts (1992) (14)
- A multiprocessor implementation of relaxation-based electrical circuit simulation (1984) (14)
- Learning as applied to stochastic optimization for standard cell placement (1998) (13)
- Iterated Timing Analysis (1990) (13)
- TOBAC: a test case browser for testing object-oriented software (1994) (13)
- An efficient verifier for finite state machines (1991) (13)
- Digital image restoration by exposure-splitting and registration (2004) (12)
- Proceedings of the 25th ACM/IEEE Design Automation Conference (1988) (12)
- Irredundant interacting sequential machines via optimal logic synthesis (1991) (11)
- An Accurate Delay Modeling Technique for Switch-Level Timing Verification (1986) (11)
- Abstract data types and high-level synthesis (1990) (10)
- Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits (1983) (10)
- Retiming for DSM with area-delay trade-offs and delay constraints (1999) (10)
- Implicit state transition graphs: applications to sequential logic synthesis and test (1990) (10)
- An Empirical Analysis of the Performance of a Multiprocessor-Based Circuit Simulator (1986) (10)
- Integration of retiming with architectural floorplanning (2000) (9)
- Selected Papers on Logic Synthesis for Integrated Circuit Design (1987) (9)
- Two-Level Minimization of Multivalued Functions with Large Offsets (1993) (9)
- WELD-an environment for Web-based electronic design (1998) (9)
- Predicting performance potential of modern DSPs (2000) (9)
- SLIP: a software environment for system level interactive partitioning (1989) (9)
- Adaptive methods for netlist partitioning (1997) (8)
- Simulating lossy interconnect with high frequency nonidealities in linear time (1992) (8)
- A Multiprocessor Implementation of Relaxation-Based Electrical Circuit Simulation (1984) (8)
- Finite State Machine Decomposition (1992) (8)
- Design Work-Stations (1983) (8)
- The CAD Framework Initiative (1992) (8)
- KAHLUA: A Hierarchical Circuit Disassembler (1987) (8)
- Reduced offsets for two-level multi-valued logic minimization (1990) (8)
- Has CAD for VLSI Reached a Dead End? (1991) (7)
- Fast Boolean matching with don't cares (2006) (7)
- Gate-Level Simulation (1985) (7)
- The MARCO/DARPA Gigascale Silicon Research Center (1999) (6)
- Sequential logic synthesis for testability using register-transfer level descriptions (1990) (6)
- A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions (1990) (6)
- The JavaTime approach to mixed hardware-software system design (1999) (6)
- Estimation techniques to guide low-power resynthesis algorithms for combinational random cmos logic (1995) (6)
- Accelerating Relaxation Algorithms for Circuit Simulation Using Waveform Newton, Iterative Step Size (1985) (6)
- A SIMPLE MOSFET MODEL FOR CIRCUIT ANALYSIS AND ITS APPLICATION TO CMOS GATE DELAY ANALYSIS AND SERIES-CONNECTED MOSFET STRUCTURE (1990) (5)
- An application of a synchronous~reactive semantics to the vhdl language (1992) (5)
- Design Aids for VLSI: A Perspective Revisited (1985) (5)
- Design Flow Management (1992) (4)
- Data-flow based behavioral-level simulation and synthesis (1983) (4)
- Switch-Level Timing Simulation (1990) (4)
- Interfacing system description languages to formal verification (1996) (4)
- The analysis of floating capacitors for timing simulation (1980) (4)
- On estimation accuracy for guiding low-power resynthesis (1996) (4)
- Engineering change for power optimization using global sensitivity and synthesis flexibility (1997) (4)
- Twenty-five years of electronic design automation (1988) (3)
- A Survey of Computer Aids for VLSI Layout (1982) (3)
- Logic Synthesis for Integrated Circuit Design, Selected Papers On (1987) (3)
- Rapid prototyping from VDM specifications using Ada (1992) (3)
- Multiple-Output Shared Transistor Logic (MOSTL) (1990) (2)
- Data-Flow/Event Graphs (1992) (2)
- Experiments on the synthesis and testability of non-scan finite state machines (1992) (2)
- VLSI-Based System Design Challenges in the Early 1990s (1990) (2)
- Evaluation and guidance in processor architecture selection for dsp (2000) (2)
- Discerning structure from freeform sketches (2003) (2)
- Implementation of Mixed-Mode Simulation (1990) (2)
- Sequential Test Generation (1992) (2)
- Introduction to Mixed-Mode Simulation (1990) (2)
- Multiple fault testable sequential circuits (1990) (2)
- Logic synthesis using power-sensitive Don't Care sets (1996) (2)
- The Berkeley synthesis project (1987) (2)
- Highlights of VLSI Research at Berkeley (1986) (2)
- Mixed-Mode Simulation and Implementation (1994) (1)
- Custom and Semi-Custom Design Techniques (1984) (1)
- Testability driven synthesis of interacting finite state machines (1990) (1)
- The Hartnell Astronomy Short Course: Bolstering the Scientific Research Preparation of Community College Students (2010) (1)
- Difhsion: An Optimization Algorithm for Multiminimum Problems and Its Application to MOSFET Model Parameter Extraction (1992) (1)
- The VLSI design challenge of the 80's (Position Statement) (1980) (1)
- . " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout (1)
- 4 Preliminary Experimental Results (1)
- 5 Conclusion and Future Work 4 Experimental Results (1995) (1)
- Computer-Aided Synthesis of Data-Path by using a Simulated-Annealing-based approach (1991) (1)
- Design and Prototyping of Hard Real Time Systems (1990) (1)
- The maximal VHDL subset with a cycle-level abstraction (1996) (1)
- A MUL~R IMPLEMENTATION OF REIAXATION-BA~ ~I;~CTRICAL CIRCUIT SIMUIATION (1984) (1)
- An executive view of the EDA industry (panel) (1997) (0)
- Symbolic FSM Traversal Methods (1992) (0)
- Embedded systems design in the new millennium (panel session) (2000) (0)
- Implementing a CAD Framework (1992) (0)
- Estimation and synthesis for low-power, high-performance integrated circuits (1997) (0)
- Technical challenges of IP and system-on-chip (panel): the ASIC vendor perspective (1998) (0)
- A common model approach to the integration of heterogeneous models of communications, concurrency, and coordination for embedded systems (2004) (0)
- Introduction to design automation for electronic systems (1991) (0)
- Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). (1998) (0)
- Position Statement the VLSI Design Challenge of the 80'S (1980) (0)
- Major Components of an Engineering Framework (1992) (0)
- The Mixed-Mode Interface (1994) (0)
- Encoding of Symbolic Inputs (1992) (0)
- Statistical Machine Learning for Large-Scale Optimization Contributors (0)
- An exact analytic technique for simulating uniform RC lines (1992) (0)
- Research in computer simulation of integrated circuits (1983) (0)
- Great works for the 21st century: a critical role for the modern research university (2004) (0)
- Irreduiidaiit Sequential Macliiiies Via Optiiiial Logic S;\-iitliesis (1990) (0)
- Electrical Simulation Techniques (1990) (0)
- Framework Standards: How Important are They? (Panel Abstract) (1991) (0)
- Analog Multilevel Simulation (1994) (0)
- Encoding of Symbolic Outputs (1992) (0)
- Sequential Synthesis for Testability (1992) (0)
- Conclusions and Directions for Future Work (1992) (0)
- Session details: EDA--this is serious business (2004) (0)
- Session 11 design techniques [breaker page] (1983) (0)
- Relaxation-Based Simulation Techniques (1990) (0)
- CU ' N Test Generation for Highly Sequential Circuits (0)
- Highlight of VLSI at research Berkeley (1986) (0)
- A formal knowledge-based data-fusion language for safety-critical applications (1994) (0)
- Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract) (1990) (0)
- Verification of Sequential Circuits (1992) (0)
- Practical and adaptive multi-stroke symbol recognition (2004) (0)
- Table 2: Power Consumption for Multi-level Implemen- Tation 5 Multi-level Logic Implementation (1994) (0)
- 1995 Keynote Address (1995) (0)
- Session 1 custom and semi-custom design techniques (1984) (0)
- Presentation of the 2001 Phil Kaufman Award to Professor Alberto Sangiovanni-Vincentelli (2010) (0)
- Distributed design data management for electronic design automation (2004) (0)
- Why doesn't EDA get enough respect? (2000) (0)
- Sequential Don’t Cares (1992) (0)
- Test Generation Using RTL Descriptions (1992) (0)
- Microsoft Windows NT And The Competition for Desktop Computing (1994) (0)
- Retiming and resynthesis approach for soft intellectual property integration in system-on-chip design (2001) (0)
- Improvement of stochastic optimization through learning for complex problems (2000) (0)
- CEO Panel: EDA: This is serious business (2004) (0)
- A SYNTHESIS AND OPTIMIZATION PROCEDURE FOR FULLY TESTABLE SEQUENTIAL MACHINES (2015) (0)
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