Alice C. Parker

Q: What Schools Are Affiliated With Alice C. Parker

Alice C. Parker is affiliated with the following schools: University of California, Berkeley, California Institute of Technology, North Carolina State University, University of Southern California, Stanford University, Columbia University

Alice C. Parker's AcademicInfluence.com Rankings

Alice C. Parker

Engineering

#6349

World Rank

#7669

Historical Rank

Electrical Engineering

#2370

World Rank

#2481

Historical Rank

engineering Degrees

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Engineering

Alice C. Parker's Degrees

Masters Electrical Engineering Stanford University
PhD Electrical Engineering Stanford University

Why Is Alice C. Parker Influential?

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According to Wikipedia, Alice Cline Parker is an American electrical engineer. Her early research studied electronic design automation; later in her career, her interests shifted to neuromorphic engineering, biomimetic architecture for computer vision, analog circuits, carbon nanotube field-effect transistors, and nanotechnology. She is Dean's Professor of Electrical and Computer Engineering in the USC Viterbi School of Engineering of the University of Southern California.

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Alice C. Parker's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

The high-level synthesis of digital systems (1990) (649)
Sehwa: a software package for synthesis of pipelines from behavioral specifications (1988) (400)
A Representation for Shape Based on Peaks and Ridges in the Difference of Low-Pass Transform (1984) (352)
REAL: A Program for REgister ALlocation (1987) (342)
MAHA: A Program for Datapath Synthesis (1986) (320)
Tutorial on high-level synthesis (1988) (310)
SOS: Synthesis of application-specific heterogeneous multiprocessor systems (2001) (224)
A design methodology and computer aids for digital VLSI systems (1981) (119)
Techniques for area estimation of VLSI layouts (1989) (112)
3D scheduling: high-level synthesis with floorplanning (1991) (110)
A formal method for the specification, analysis, and design of register-transferlevel digital logic (1988) (93)
A memristor SPICE model for designing memristor circuits (2010) (89)
SEHWA: A Program for Synthesis of Pipelines (1986) (86)
An Extensible Object-Oriented Approach to Databases for VLSI/CAD (1985) (80)
Accuracy sensitive word-length selection for algorithm optimization (1998) (74)
Predicting system-level area and delay for pipelined and nonpipelined designs (1992) (73)
A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic (1981) (72)
Experience with the ADAM Synthesis System (1989) (71)
CHOP: a constraint-driven system-level partitioner (1991) (69)
The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface (1985) (68)
Stochastic Models for Wireability Analysis of Gate Arrays (1986) (66)
Module selection for pipelined synthesis (1988) (64)
Synthesis of Application-Specific Heterogeneous Multiprocessor Systems (1992) (62)
The CMU Design Automation System - An Example of Automated Data Path Design (1979) (60)
Automated Synthesis of Digital Hardware (1982) (57)
A Design Utility Manager: the ADAM Planning Engine (1986) (56)
Critical Path Minimization Using Retiming and Algebraic Speed-Up (1993) (55)
Area-time model for synthesis of non-pipelined designs (1988) (51)
An Abstract Model of Behavior for Hardware Descriptions (1983) (48)
A brain-plausible neuromorphic on-the-fly learning system implemented with magnetic domain wall analog memristors (2019) (48)
Synthesis of application-specific multiprocessor architectures (1991) (47)
Register-Transfer Level Digital Design Automation: The Allocation Process (1978) (45)
Data path tradeoffs using MABAL (1990) (42)
Predicting Area-Time Tradeoffs for Pipelined Design (1987) (37)
Synthesis of Hardware for the Control of Digital Systems (1982) (37)
The ADAM design planning engine (1991) (36)
PLEST: A Program for Area Estimation of VLSI Integrated Circuits (1986) (36)
Automated Synthesis of Digital systems (1984) (33)
Synthesis of Optimal Clocking Schemes (1985) (32)
A carbon nanotube implementation of temporal and spatial dendritic computations (2008) (31)
A carbon nanotube cortical neuron with spike-timing-dependent plasticity (2009) (29)
Synthesis of application-specific multiprocessor systems including memory components (1992) (27)
Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions (1989) (27)
Slide: An I/O Hardware Descriptive Language (1981) (26)
A biomimetic fabricated carbon nanotube synapse for prosthetic applications (2011) (25)
A carbon nanotube cortical neuron with excitatory and inhibitory dendritic computations (2009) (25)
Towards a Nanoscale Artificial Cortex (2006) (25)
Challenges for Brain Emulation: Why is Building a Brain so Difficult? (2012) (24)
PHRAN-SPAN: A Natural Language Interface for System Specifications (1987) (24)
An Astrocyte Neuromorphic Circuit That Influences Neuronal Phase Synchrony (2015) (24)
Experience with Image Compression Chip Design Using Unified System Construction Tools (1994) (22)
A Biomimetic Carbon Nanotube Synapse Circuit (2006) (19)
Representation of control and timing behavior with applications to interface synthesis (1988) (18)
Synaptic Variability in a Cortical Neuromorphic Circuit (2013) (17)
Automating the VLSI design process using expert systems and silicon compilation (1987) (17)
High performance embedded system optimization using algebraic and generalized retiming techniques (1993) (17)
SMASH: a program for scheduling memory-intensive application-specific hardware (1994) (16)
A Data Structure for VLSI Synthesis and Verification (1983) (16)
System-Level Design (2000) (15)
A CMOS neuromorphic approach to emulate neuro-astrocyte interactions (2013) (15)
A General Methodology for Synthesis and Verification of Register-Transfer Designs (1984) (15)
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems (1988) (15)
An in-silico glial microdomain to invoke excitability in cortical neural networks (2011) (14)
High-level synthesis with pin constraints for multiple-chip designs (1992) (14)
Automated design of hierarchical intranets (2002) (13)
Emulation of Neural Networks on a Nanoscale Architecture (2007) (13)
A methodology and design tools to support system-level VLSI design (1995) (13)
Dendritic computations, dendritic spiking and dendritic plasticity in nanoelectronic neurons (2010) (13)
Phrasal Analysis of Long Noun Sequences (1987) (13)
The effects of physical design characteristics on the area - performance tradeoff curve (1991) (13)
A Design Method for Optimal Synthesis of Application-Specific Heterogeneous Multiprocessor Systems (1992) (12)
On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICs (1984) (12)
Digital System Simulation: Current Status and Future Trends or Darwin's Theory of Simulation (1981) (12)
Incorporating Imprecise Computation Into System-level Design Of Application-specific Heterogeneous Multiprocessors (1997) (11)
The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance (1983) (11)
Optimal synthesis of application specific heterogeneous pipelined multiprocessors (1994) (11)
A sub-optimal assignment of application tasks onto heterogeneous systems (1994) (10)
Challenges for Brain Emulation: Why is it so Difficult? (2012) (10)
Astrocyte on neuronal phase synchrony in CMOS (2014) (10)
Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming (1995) (10)
A hybrid neuromorphic circuit demonstrating schizophrenic symptoms (2015) (10)
Algorithms for Multiple-Criterion Design of Microprogrammed Control Hardware (1981) (10)
The Automated Dictionary (1980) (9)
Unified System Construction (USC) (1991) (9)
Synthesis and optimization of application-specific intranets (2001) (8)
A carbon nanotube spiking cortical neuron with tunable refractory period and spiking duration (2010) (8)
Critical Path Analysis (1999) (7)
Transfer Function Analysis of Picture Processing Operators (1980) (7)
Computer-aided system integration for data-intensive multimedia applications (poster session) (2000) (6)
Exploring network topology evolution through evolutionary computations (2006) (6)
Microprogramming: the challenges of VLSI (1981) (6)
Synthesis of application-specific heterogeneous multiprocessor systems (abstract) (1992) (6)
The Application of a Hardware Descriptive Language for Design Automation (1978) (5)
A CMOS circuit implementation of retrograde signaling in astrocyte-neuron networks (2016) (5)
i-CAD: a rapid prototyping CAD tool for intranet design (2003) (5)
A hierarchical artificial retina architecture (2009) (5)
Understanding System Specifications Written in Natural Language (1987) (5)
Modeling intrinsic ion-channel and synaptic variability in a cortical neuromorphic circuit (2011) (5)
Theory and practice in system-level design of application-specific heterogeneous multiprocessors (1997) (5)
Dynamic spike threshold and nonlinear dendritic computation for coincidence detection in neuromorphic circuits (2014) (5)
FREEDOM: statistical behavioral estimation of system energy and power (1998) (5)
Neuromorphic network implementation of the somatosensory cortex (2013) (4)
The EVE VLSI information management environment (1989) (4)
Neural circuits for touch-induced locomotion in Caenorhabditis elegans (2015) (4)
Noisy neuromorphic neurons with RPG on-chip noise source (2017) (4)
A Bus System for the Military Computer Family (1979) (4)
Noisy neuromorphic circuit modeling Obsessive Compulsive Disorder (2016) (3)
An Electronic Neuron with Input-Specific Spiking (2019) (3)
Managing Complexity in an Autonomous Vehicle (2006) (3)
An analog neural network that learns Sudoku-like puzzle rules (2016) (3)
Neuromorphic Circuits With Neural Modulation Enhancing the Information Content of Neural Signaling (2020) (3)
A Natural Language Interface for Specifying Digital Systems (1986) (3)
A neuromorphic circuit mimicking biological short-term memory (2016) (3)
Managing complexity in an autonomous vehicle (2008) (3)
An evolutionary approach to system redesign (1998) (3)
The Slide Simulator: A Facility for the Design and Analysis of Computer Interconnections (1980) (3)
Biomimetic non-linear CMOS adder for neuromorphic circuits (2013) (3)
Taking Thermal Considerations Into Account During High-Level Synthesis (1997) (3)
Data path synthesis of pipelined designs: theoretical foundations (1990) (3)
An adaptable CMOS depressing synapse with detection of changes in input spike rate (2014) (2)
A directionally-selective neuromorphic circuit based on reciprocal synapses in Starburst Amacrine Cells (2011) (2)
Interconnect-based system-level energy and power prediction to guide architecture exploration (2004) (2)
MODELING BRAIN DISORDERS IN SILICON NANOTECHNOLOGIES (2016) (2)
Analog Neurons that Signal with Spiking Frequencies (2019) (2)
A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs (1994) (2)
Synthesizing complex multimedia network topologies using an evolutionary approach (2004) (2)
A comprehensive framework for the specification of hardware/software systems (2001) (2)
Area Estimation of VLSI Integrated Circuits. (1985) (2)
3D Tree-Structured Object Tracking for Autonomous Ground Vehicles (2007) (2)
The Elephant in the Mirror: Bridging the Brain's Explanatory Gap of Consciousness (2017) (2)
Hardware/software tradeoffs in a variable word width, variable queue length buffer memory (1977) (2)
Border ownership in a nano-neuromorphic circuit using nonlinear dendritic computations (2014) (2)
A neuromorphic circuit that computes differential motion (2012) (2)
Rapid synthesis of multi-chip systems (1997) (2)
The POTATO chip architecture: a study in tradeoffs for signal processing chip design (1988) (1)
A Symbolic Approach for Checking Functional and Timing Compatibility of Synthesized Designs (1993) (1)
Specification, Simulation and Automated Design of Interfaces and Digital Circuits. (1979) (1)
An input interface for a real-time digital sound generation system (1976) (1)
Analog Neurons with Dopamine-Modulated STDP (2019) (1)
Proceedings of the 11th annual workshop on Microprogramming, MICRO 1978, Asilomar (Pacific Grove), California, USA, November 19-22, 1978 (1978) (1)
Biomimetic Cortical Nanocircuits (2009) (1)
Symbolic Techniques for Optimal Scheduling 1 (1)
Neuromorphic circuit modeling directional selectivity in the visual cortex (2016) (1)
Computer-Aided Synthesis of Data-Path by using a Simulated-Annealing-based approach (1991) (1)
A frequency-based mathematical model of binocular complex cell responses (2012) (1)
Chapter 8 – THE ADAM DESIGN PLANNING ENGINE (1992) (1)
A neuromorphic circuit mimicking biological short-term memory. (2016) (1)
A bio-inspired electronic mechanism for unsupervised learning using structural plasticity (2016) (1)
Synthesis of Optimal Clocking Schemes for Digital Systems. (1984) (1)
Towards a Nanoscale Artificial Cortex 1 (2006) (0)
A power-efficient biomimetic intra-branch dendritic adder (2017) (0)
A Carbon Nanotube Neuron with Dendritic Computations (2008) (0)
Envelope Control with an Optical Keyboard (1977) (0)
Simulation Studies of Neuronal Modulation Using Magneto-electric Nanoparticles for Astrocyte Stimulation (2019) (0)
Vision-based Autonomous Ground Vehicle Design Within a Mixed Environment (2009) (0)
Neuromorphic circuit modeling directional selectivity in the visual cortex. (2016) (0)
Neuromorphic Autonomous Spiking Encoding (2021) (0)
The design and implementation of a real-time sound generation system (1977) (0)
A methodology for the hardware/software co-design of embedded systems (2007) (0)
Code Generation and Machine Descriptions (2010) (0)
An Input Interface for Real-Time Digital Sound Generation System (1976) (0)
Num Bktrk/ Cost/constraint Exec Example Btk ($) Time (s) Table 4. Hierarchical Behavioral Partition- Ing and Package Design (1996) (0)
A switched-capacitor dendritic arbor for low-power neuromorphic applications (2017) (0)
Don't Lose Your Mind: Brain-Computer Interfaces, Autonomy, and the Necessity of Engineering Ethics (2021) (0)
Description and simulation of microcode execution (1978) (0)
Formal Models of Hardware and Their Applications to VLSI Design Automation. (1986) (0)
Knowledge representation to support reasoning based on multiple models (1990) (0)
CYOS: Scheduling in a Continuous Area-Time Design Space (1990) (0)
Emulation of Neural Networks on a Nanoscale Spin-Wave Architecture 1 (2006) (0)
A biomimetic nanoelectronic neuron with enhanced spike timing (2014) (0)
The Design of a User-Programmable Digital Interface (1976) (0)
Introduction (2020) (0)
Automated Synthesis of Digital Hardware Modules: Simulation and Verification of Interconnections. (1979) (0)
Hardware/Software Tradeoffs (2002) (0)
Towards biomimetic stereo vision (2010) (0)
The Carnegie-Mellon Computer Music System Digital Hardware (1977) (0)
A CMOS Implementation of Neural Dendritic Computations with Cost Analysis (2008) (0)
System-level Design 1 Introduction Design Philosophies and System-level Design @bullet the System Design Space 2 System Specification 3 System Partitioning Constructive Partitioning Techniques @bullet Iterative Partitioning Techniques 4 Scheduling and Allocating Tasks to Processing Modules 5 Allocat (2005) (0)
Structure and function of a general purpose input output processor (1979) (0)
C. elegans neuromorphic neural network exhibiting undulating locomotion (2017) (0)
Emulation of Neural Networks at Nanoscale (2007) (0)
A Representation forShapeBasedon Peaksand RidgesintheDifference ofLow-Pass Transform (1984) (0)
The design of a user-programmable digital interface (Recent Results) (1976) (0)
From Silicon to the Brain Using Microelectronics as a Bridge (2020) (0)

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Other Resources About Alice C. Parker

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What Schools Are Affiliated With Alice C. Parker?

Alice C. Parker is affiliated with the following schools:

Alice C. Parker's Academic­Influence.com Rankings