Anand Raghunathan

Anand Raghunathan's AcademicInfluence.com Rankings

Anand Raghunathan

Engineering

#4972

World Rank

#6201

Historical Rank

Electrical Engineering

#1318

World Rank

#1409

Historical Rank

engineering Degrees

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Engineering

Anand Raghunathan's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

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Anand Raghunathan's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Low-Power Digital Signal Processing Using Approximate Adders (2013) (641)
Security in embedded systems: Design challenges (2004) (509)
Analysis and characterization of inherent application resilience for approximate computing (2013) (450)
A study of the energy consumption characteristics of cryptographic algorithms and security protocols (2006) (447)
Security as a new dimension in embedded system design (2004) (432)
IMPACT: IMPrecise adders for low-power approximate computing (2011) (430)
Battery-driven system design: a new frontier in low power design (2002) (401)
SALSA: Systematic logic synthesis of approximate circuits (2012) (328)
Analyzing the energy consumption of security protocols (2003) (315)
Hijacking an insulin pump: Security attacks and defenses for a diabetes therapy system (2011) (297)
Tarazu: optimizing MapReduce on heterogeneous clusters (2012) (271)
High-Level Power Analysis and Optimization (1997) (269)
Quality programmable vector processors for approximate computing (2013) (259)
MACACO: Modeling and analysis of circuits for approximate computing (2011) (249)
Tamper resistance mechanisms for secure embedded systems (2004) (235)
AxNN: Energy-efficient neuromorphic systems using approximate computing (2014) (230)
Approximate computing and the quest for computing efficiency (2015) (216)
Battery life estimation of mobile embedded systems (2001) (207)
Computing in Memory With Spin-Transfer Torque Magnetic RAM (2017) (193)
Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency (2010) (186)
SCALEDEEP: A scalable compute architecture for learning and evaluating deep networks (2017) (182)
Design of voltage-scalable meta-functions for approximate computing (2011) (181)
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare (2015) (174)
Behavioral synthesis for low power (1994) (160)
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives (2016) (148)
Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits (2013) (146)
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs (2001) (145)
Secure embedded processing through hardware-assisted run-time monitoring (2005) (140)
MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection (2013) (139)
TapeCache: a high density, energy efficient cache based on domain wall memory (2012) (139)
Systematic Software-Based Self-Test for Pipelined Processors (2006) (138)
Evaluation of the traffic-performance characteristics of system-on-chip communication architectures (2001) (137)
A scalable software-based self-test methodology for programmable processors (2003) (135)
Design space exploration for optimizing on-chip communication architectures (2004) (134)
ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters (2014) (132)
Battery discharge characteristics of wireless sensor nodes: an experimental analysis (2005) (131)
Best-effort computing: Re-thinking parallel software and hardware (2010) (124)
Register-transfer level estimation techniques for switching activity and power consumption (1996) (119)
System-level performance analysis for designing on-chipcommunication architectures (2001) (116)
Trustworthiness of Medical Devices and Body Area Networks (2014) (115)
ASLAN: Synthesis of approximate sequential circuits (2014) (114)
Efficient exploration of the SoC communication architecture design space (2000) (113)
Spin-Transfer Torque Memories: Devices, Circuits, and Systems (2016) (111)
Synthesis of custom processors based on extensible platforms (2002) (103)
Custom-instruction synthesis for extensible-processor platforms (2004) (100)
Power analysis of embedded operating systems (2000) (100)
Wearable Medical Sensor-Based System Design: A Survey (2017) (99)
Securing wireless data: system architecture challenges (2002) (99)
Energy-Efficient Long-term Continuous Personal Health Monitoring (2015) (95)
DWM-TAPESTRI - An energy efficient all-spin cache using domain wall shift based writes (2013) (93)
Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture (2012) (92)
Secure Virtual Machine Execution under an Untrusted Management OS (2010) (92)
High-level software energy macro-modeling (2001) (90)
Best-effort parallel execution framework for Recognition and mining applications (2009) (90)
SPINDLE: SPINtronic Deep Learning Engine for large-scale neuromorphic computing (2014) (83)
System design methodologies for a wireless security processing platform (2002) (81)
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors (2006) (78)
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis (1995) (77)
Approximate storage for energy efficient spintronic memories (2015) (77)
Power monitors: a framework for system-level power estimation using heterogeneous power models (2005) (75)
The LOTTERYBUS on-chip communication architecture (2006) (75)
SCALP: an iterative-improvement-based low-power data path synthesis system (1997) (75)
SECA: security-enhanced communication architecture (2005) (75)
An iterative improvement algorithm for low power data path synthesis (1995) (73)
Approximate computing: An integrated hardware approach (2013) (72)
Scalable Effort Hardware Design (2014) (70)
Power emulation: a new paradigm for power estimation (2005) (70)
A Trusted Virtual Machine in an Untrusted Management Environment (2012) (69)
Scalable-effort classifiers for energy-efficient machine learning (2015) (68)
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies (2014) (66)
Design and Management of Battery-Supercapacitor Hybrid Electrical Energy Storage Systems for Regulation Services (2017) (65)
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing (2016) (64)
Safe Java Native Interface (2006) (62)
An ILP formulation for low power based on minimizing switched capacitance during data path allocation (1995) (62)
Emerging Frontiers in Embedded Security (2013) (61)
Optimizing public-key encryption for wireless clients (2002) (60)
Fast performance analysis of bus-based system-on-chip communication architectures (1999) (59)
Register transfer level power optimization with emphasis on glitch analysis and reduction (1999) (59)
CABA: Continuous Authentication Based on BioAura (2017) (59)
Analysis and design of a hardware/software trusted platform module for embedded systems (2008) (58)
Energy macromodeling of embedded operating systems (2005) (56)
Vibration-based secure side channel for medical devices (2015) (56)
Performance analysis of systems with multi-channel communication architectures (2000) (56)
Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips (2000) (55)
A design for testability technique for RTL circuits using control/data flow extraction (1996) (54)
Dynamic effort scaling: Managing the quality-efficiency tradeoff (2011) (54)
A scalable application-specific processor synthesis methodology (2003) (53)
Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors (2005) (53)
Efficient RTL power estimation for large designs (2003) (53)
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks (2014) (51)
A design-for-testability technique for register-transfer level circuits using control/data flow extraction (1998) (49)
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars (2018) (48)
Glitch analysis and reduction in register transfer level power optimization (1996) (48)
A framework for efficient and scalable execution of domain-specific templates on GPUs (2009) (47)
Common-case computation: a high-level technique for power and performance optimization (1999) (46)
EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness against Adversarial Attacks (2020) (45)
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication (2008) (45)
Physiological Information Leakage: A New Frontier in Health Information Security (2016) (45)
Software architectural transformations: a new approach to low energy embedded software (2003) (44)
High performance model based image reconstruction (2016) (44)
Securing mobile appliances: new challenges for the system designer (2003) (43)
Improving the Trustworthiness of Medical Device Software with Formal Verification Methods (2013) (42)
Automated Energy/Performance Macromodeling of Embedded Software (2004) (42)
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications (2015) (42)
Application-specific heterogeneous multiprocessor synthesis using extensible processors (2006) (42)
Cosimulation-based power estimation for system-on-chip design (2002) (42)
Transport protocol optimization for energy efficient wireless embedded systems (2003) (41)
Exploiting the forgiving nature of applications for scalable parallel execution (2010) (41)
ROBESim: A retrofit-oriented building energy simulator based on EnergyPlus (2013) (41)
Energy-Efficient Neural Computing with Approximate Multipliers (2018) (41)
Embedded operating system energy analysis and macro-modeling (2002) (40)
Efficient fingerprint-based user authentication for embedded systems (2005) (39)
Computing approximately, and efficiently (2015) (38)
Spintastic: Spin-based stochastic logic for energy-efficient computing (2015) (38)
Efficient power co-estimation techniques for system-on-chip design (2000) (37)
Design of high-performance system-on-chips using communication architecture tuners (2004) (37)
Approximate computing for spiking neural networks (2017) (37)
Hierarchical test generation and design for testability methods for ASPPs and ASIPs (1999) (37)
Energy-efficient and Secure Sensor Data Transmission Using Encompression (2013) (36)
Relax-and-Retime: A methodology for energy-efficient recovery based design (2013) (35)
Quality configurable reduce-and-rank for energy efficient approximate computing (2015) (34)
Model-based Iterative CT Image Reconstruction on GPUs (2017) (34)
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs (2000) (33)
Energy-optimizing source code transformations for operating system-driven embedded software (2007) (33)
Efficient power co-estimation techniques for system-on-chip design (2000) (32)
Power estimation for cycle-accurate functional descriptions of hardware (2004) (32)
Considering Process Variations During System-Level Power Analysis (2006) (32)
Efficient power profiling for battery-driven embedded system design (2004) (32)
Hybrid simulation for embedded software energy estimation (2005) (32)
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis (2007) (31)
Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions (1998) (31)
STAxCache: An approximate, energy efficient STT-MRAM cache (2017) (30)
Acceleration techniques for dynamic vector compaction (1995) (30)
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations (2012) (30)
Power Management Techniques For Control-flow Intensive Designs (1997) (30)
A Scalable Synthesis Methodology for Application-Specific Processors (2006) (30)
An architecture for secure software defined radio (2009) (29)
A case study on modeling shared memory access effects during performance analysis of HW/SW systems (1998) (29)
Verification of RTL generated from scheduled behavior in a high-level synthesis flow (1998) (29)
Approximate Computing for Long Short Term Memory (LSTM) Neural Networks (2018) (29)
MDR: performance model driven runtime for heterogeneous parallel platforms (2011) (28)
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis (2007) (28)
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges (2020) (28)
Transient power management through high level synthesis (2001) (28)
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology (2005) (28)
Cache Design with Domain Wall Memory (2016) (28)
Accurate power macro-modeling techniques for complex RTL circuits (2001) (28)
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors (2007) (28)
Analysis of power dissipation in embedded systems using real-time operating systems (2003) (28)
Energy and Execution Time Analysis of a Software-based Trusted Platform Module (2007) (28)
Efficient embedded learning for IoT devices (2016) (27)
Communication architecture based power management for battery efficient system design (2002) (27)
Best-effort semantic document search on GPUs (2010) (27)
StoRM: A Stochastic Recognition and Mining processor (2014) (27)
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis (2000) (27)
Architectural support for safe software execution on embedded processors (2006) (26)
Dynamic Binary Instrumentation-Based Framework for Malware Defense (2008) (26)
Efficient power estimation techniques for HW/SW systems (1999) (26)
High-level macro-modeling and estimation techniques for switching activity and power consumption (2003) (26)
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches (2013) (25)
CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems (2020) (25)
Energy Efficient Neural Computing: A Study of Cross-Layer Approximations (2018) (25)
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks (2017) (24)
A comprehensive high-level synthesis system for control-flow intensive behaviors (2003) (24)
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components (2010) (24)
A power management methodology for high-level synthesis (1998) (24)
Variation-Tolerant Dynamic Power Management at the System-Level (2009) (24)
Automatic generation of software pipelines for heterogeneous parallel systems (2012) (23)
Communication-Based Power Management (2002) (23)
Bottleneck removal algorithm for dynamic compaction and test cycles reduction (1995) (23)
Towards trustworthy medical devices and body area networks (2013) (23)
High-level energy macromodeling of embedded software (2002) (22)
Approximate memory compression for energy-efficiency (2017) (22)
Bottleneck removal algorithm for dynamic compaction in sequential circuits (1997) (22)
Hybrid Simulation for Energy Estimation of Embedded Software (2007) (22)
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems (2020) (22)
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques (2006) (21)
An evaluation of energy-saving technologies for residential purposes (2010) (21)
Architectural Support for Run-Time Validation of Program Data Properties (2007) (21)
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations (2017) (21)
High-level synthesis of multi-process behavioral descriptions (2003) (21)
X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks (2019) (21)
A hybrid energy-estimation technique for extensible processors (2004) (20)
Power management in high-level synthesis (1999) (20)
Architectures for efficient face authentication in embedded systems (2006) (19)
Invited — Cross-layer approximations for neuromorphic computing: From devices to circuits and systems (2016) (19)
Designing approximate circuits using clock overgating (2016) (19)
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis (2007) (19)
Manna: An Accelerator for Memory-Augmented Neural Networks (2019) (19)
AXSERBUS: A quality-configurable approximate serial bus for energy-efficient sensing (2017) (19)
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC (2006) (19)
Approximation through logic isolation for the design of quality configurable circuits (2016) (18)
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers (2021) (18)
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation (2007) (18)
Exploring Spin-Transfer-Torque Devices for Logic Applications (2014) (18)
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks (2019) (17)
Algorithm Exploration for Efficient Public-Key Security Processing on Wireless Handsets (2002) (17)
AxBA: An Approximate Bus Architecture Framework (2018) (17)
Approximate Computing (2016) (17)
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited (2017) (17)
A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks (2017) (17)
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management (2015) (17)
Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks (2019) (16)
Design and management of hybrid electrical energy storage systems for regulation services (2014) (16)
Design of Communication Architectures for High-Performance and Energy-Efficient Systems-on-Chips (2005) (16)
Controller-based power management for control-flow intensive designs (1999) (16)
Attacking and Defending a Diabetes Therapy System (2014) (16)
Profiling driven computation reuse: an embedded software synthesis technique for energy and performance optimization (2004) (15)
High-level synthesis of distributed logic-memory architectures (2002) (15)
Energy efficient many-core processor for recognition and mining using spin-based memory (2011) (15)
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks (2020) (15)
RTL-Aware Cycle-Accurate Functional Power Estimation (2006) (15)
Impact of configurability and extensibility on IPSec protocol execution on embedded processors (2006) (15)
DyReCTape: A dynamically reconfigurable cache using domain wall memory tapes (2015) (15)
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design (2002) (15)
A simulation framework for energy-consumption analysis of OS-driven embedded applications (2003) (15)
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis (1996) (15)
On Modeling and Evaluation of Logic Circuits under Timing Variations (2012) (14)
Dynamic test sequence compaction for sequential circuits (1996) (14)
Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs (2016) (14)
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems (2007) (14)
Power Analysis of System-Level On-Chip Communication Architectures (2004) (14)
Neural network accelerator design with resistive crossbars: Opportunities and challenges (2019) (13)
Controller re-specification to minimize switching activity in controller/data path circuits (1996) (13)
A defense framework against malware and vulnerability exploits (2014) (13)
Active Learning Driven Data Acquisition for Sensor Networks (2006) (13)
Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective (2014) (13)
Embedding security in wireless embedded systems (2003) (12)
Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks (2020) (12)
FLEXBAR: A crossbar switching fabric with improved performance and utilization (2002) (12)
Battery-efficient architecture for an 802.11 MAC processor (2002) (12)
Energy-efficient recognition and mining processor using scalable effort design (2013) (11)
Vehicle Lightweighting: 40% and 45% Weight Savings Analysis: Technical Cost Modeling for Vehicle Lightweighting (2015) (11)
Energy estimation for extensible processors (2003) (11)
Considering testability during high-level design (1998) (11)
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars (2018) (11)
Computing-in-memory with spintronics (2018) (11)
Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software (2006) (11)
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components (2016) (11)
Approximate Memory Compression (2020) (10)
Synthesis of heterogeneous distributed architectures for memory-intensive applications (2003) (10)
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks (2021) (10)
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution (2007) (10)
High-level synthesis with SIMD units (2002) (10)
Asymmetric underlapped FinFET based robust SRAM design at 7nm node (2015) (10)
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling (2013) (10)
Adaptation of video encoding to address dynamic thermal management effects (2012) (10)
Variation-Aware System-Level Power Analysis (2010) (10)
Transforming control-flow intensive designs to facilitate power management (1998) (10)
System-on-Chip Power Management Considering Leakage Power Variations (2007) (9)
Domain-Specific Many-core Computing using Spin-based Memory (2014) (9)
Hierarchical Test Generation And Design For Testability Of ASPPs and ASIPs (1997) (9)
Enhancing security through hardware-assisted run-time validation of program data properties (2005) (9)
Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC (2015) (9)
VESPA: Variability emulation for System-on-Chip performance analysis (2011) (9)
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses (2017) (9)
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation (2019) (9)
Hardware accelerated power estimation (2005) (9)
Input space adaptive design: a high-level methodology for energy and performance optimization (2001) (8)
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches (2016) (8)
Designing Chips without Guarantees (2010) (8)
Logic Synthesis of Approximate Circuits (2020) (8)
Reliability and security of implantable and wearable medical devices (2015) (8)
Design for Testability Techniques at the Behavioral and Register-Transfer Levels (1998) (8)
Energy-optimizing source code transformations for OS-driven embedded software (2004) (8)
Energy-Efficient Object Detection Using Semantic Decomposition (2015) (8)
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage (2015) (8)
Test generation for cyclic combinational circuits (1995) (8)
Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing (2018) (7)
Secure reconfiguration of software-defined radio (2012) (7)
PIC: Partitioned Iterative Convergence for Clusters (2012) (7)
Variation-Aware Voltage Level Selection (2012) (7)
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation (1999) (7)
Recovery-based design for variation-tolerant SoCs (2012) (7)
Approximate computing: Energy-efficient computing with good-enough results (2013) (7)
SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones (2018) (7)
DyVEDeep: Dynamic Variable Effort Deep Neural Networks (2017) (6)
Guest Editors' Introduction: Security and Trust in Embedded-Systems Design (2007) (6)
Virtualization-assisted Framework for Prevention of Software Vulnerability Based Security Attacks (2007) (6)
Localized Heating for Building Energy Efficiency (2013) (6)
Resource budgeting for Multiprocess High-level synthesis (2004) (6)
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC (2007) (5)
Trusted Platform based Key Establishment & Management for Sensor Networks (2006) (5)
Secure Embedded Processing through Hardware-assisted (2005) (5)
Domain-wall shift based multi-level MRAM for high-speed, high-density and energy-efficient caches (2013) (5)
A Secure User Interface for Web Applications Running Under an Untrusted Operating System (2010) (5)
Communication-efficient View-Pooling for Distributed Multi-View Neural Networks (2020) (5)
Variation aware cache partitioning for multithreaded programs (2014) (5)
Energy-efficient MRAM access scheme using hybrid circuits based on spin-torque sensors (2013) (4)
Hybrid custom instruction and co-processor synthesis methodology for extensible processors (2006) (4)
Variation tolerant design of a vector processor for recognition, mining and synthesis? (2014) (4)
Valley-Coupled-Spintronic Non-Volatile Memories With Compute-In-Memory Support (2019) (4)
Input space adaptive embedded software synthesis (2002) (4)
ScaleDeep (2017) (4)
PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM (2021) (4)
A Framework for Extensible Processor Based MPSoC Design (2007) (4)
Software Architectural Transformations (2003) (4)
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies (2001) (4)
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory (2005) (4)
Generation of distributed logic-memory architectures through high-level synthesis (2005) (4)
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices (2016) (4)
Optimizing Transformers with Approximate Computing for Faster, Smaller and more Accurate NLP Models (2020) (3)
High-level synthesis using computation-unit integrated memories (2004) (3)
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration (2020) (3)
Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack (2019) (3)
Coping with Variations through System-Level Design (2009) (3)
Adaptive Data Placement in an Embedded Multiprocessor Thread Library (2006) (3)
Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing (2015) (3)
A Case for Generalizable DNN Cost Models for Mobile Devices (2020) (3)
Data Subsetting: A Data-Centric Approach to Approximate Computing (2019) (3)
Considering Testability during High-level Design (Embedded Tutorial). (1998) (3)
Use of Computation-Unit Integrated Memories in High-Level Synthesis (2006) (3)
Value Similarity Extensions for Approximate Computing in General-Purpose Processors (2021) (3)
High-Level Synthesis for Low Power (1998) (3)
CxDNN (2019) (3)
Probabilistic Spike Propagation for Efficient Hardware Implementation of Spiking Neural Networks (2021) (3)
Input space adaptive design: a high-level methodology for optimizing energy and performance (2004) (2)
Functional analysis of circuits under timing variations (2012) (2)
Fast system-level power profiling for battery-efficient system design (2002) (2)
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms (2006) (2)
DyReCTape: a dy namically re configurable c ache using domain wall memory tape s (2015) (2)
Common-case computation: a high-level energy and performance optimization technique (2004) (2)
Approximate Computing and the Efficient Machine Learning Expedition (2022) (2)
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks (2020) (2)
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems (2022) (2)
Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip (2005) (2)
Approximate Error Detection With Stochastic Checkers (2017) (2)
Approximate computing for efficient information processing (2014) (2)
Design Tools for Resistive Crossbar based Machine Learning Accelerators (2021) (2)
Guest Editors' Introduction: Green Buildings (2012) (2)
Low Power Design Methodologies for Systems-on-Chips (1999) (2)
A framework for defending embedded systems against software attacks (2011) (2)
Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks (2020) (2)
EMBIRA: An Accelerator for Model-Based Iterative Reconstruction (2016) (2)
Sparsity-Aware Caches to Accelerate Deep Neural Networks (2020) (2)
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor (2008) (2)
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding (2015) (1)
ACCLIB: Accelerators as libraries (2018) (1)
An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software (2004) (1)
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes (2016) (1)
INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment (2012) (1)
Automatic Synthesis Techniques for Approximate Circuits (2018) (1)
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads (2022) (1)
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007 (2007) (1)
Emerging Neural Workloads and Their Impact on Hardware (2020) (1)
Efficacy of Pruning in Ultra-Low Precision DNNs (2021) (1)
Guest Editors' Introduction (2018) (1)
Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective (2022) (1)
Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems (2021) (1)
AxFormer: Accuracy-driven Approximation of Transformers for Faster, Smaller and more Accurate NLP Models (2020) (1)
Efficiency attacks on spiking neural networks (2022) (1)
Emulation-Based Analysis of System-on-Chip Performance Under Variations (2016) (1)
PIM-DRAM:Accelerating Machine Learning Workloads using Processing in Memory based on DRAM Technology (2021) (1)
Layerwise Disaggregated Evaluation of Spiking Neural Networks (2022) (1)
ECE 595Z Lecture 29: Low Power Design I (2012) (0)
Guest Editors' Introduction - Special Issue on Approximate Computing (2018) (0)
Tutorial T1: Designing Secure SoCs (2007) (0)
ECE 595Z Lecture 5: Advanced Boolean Algerbra III (2012) (0)
Session details: Architectures for cryptography and security applications (2005) (0)
NEC and ICCAD — EDA Partners in Success (2003) (0)
Embedded Systems Specification and Modeling (2010) (0)
HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices (2021) (0)
SparCE: Sparsity aware General Purpose Core Extensions to Accelerate Deep Neural Networks (2017) (0)
Adversarial Sparsity Attacks on Deep Neural Networks (2020) (0)
ECE 595Z Lecture 9: Two-level Logic Synthesis IV (2012) (0)
Variation in I ON and I OFF of transistors ( Source : Intel ) Coping With Variations Through System-level Design (2008) (0)
Design and Performance Analysis of Low Power Multipliers (2020) (0)
ECE 595Z Lecture 20: Multi-level Synthesis VII (2012) (0)
ECE 595Z Lecture 17: Multi-level Synthesis IV (2012) (0)
ECE 595Z Lecture 26: Sequential Logic Optimization III (2012) (0)
Seprox: Sequence-based Approximations for Compressing Ultra-Low Precision Deep Neural Networks (2022) (0)
ECE 595Z Lecture 30: Low Power Design II (2012) (0)
Special session 11B: Hot topic hardware security: Design, test and verification issues (2010) (0)
Efficient ensembles of graph neural networks (2022) (0)
SBIR Phase I Final Report VHDL Behavioral Synthesis Tool for Low Power Based on FRITS Contractor : Alternative System Concepts (2007) (0)
34th International Conference on VLSI Design (2021) (0)
Designers' Forum Committee (2004) (0)
Safe Heterogeneous Applications : Curing the Java Native Interface ∗ (0)
care HCI Security and forensics Education User authentication Deception detection Smart tutoring Teaching assistant Posture recognition Gesture detection (2017) (0)
TEST TECHNOLOGY EDUCATIONAL PROGRAM (TTEP) 2009 (2009) (0)
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 (2006) (0)
Accelerating DNN Training Through Selective Localized Learning (2022) (0)
Exploring Software Partitions for Fast Security (2007) (0)
Architecture-Level Power Estimation (1998) (0)
Energy Efficient Cache Design with Piezoelectric FETs (2022) (0)
Session 10B - Embedded tutorial: hardware and software design of energy efficient sensor platforms (2005) (0)
THE PURDUE UNIVERSITY GRADUATE SCHOOL STATEMENT OF THESIS APPROVAL (2018) (0)
X-Former: In-Memory Acceleration of Transformers (2023) (0)
ECE 595Z Digital Systems Design Automation (2012) (0)
ECE 595Z Lecture 8: Two-level Logic Synthesis III (2012) (0)
ECE 595Z Lecture 16: Multi-level Synthesis III (2012) (0)
ECE 595Z Lecture 13: Boolean Satisfiability III (2012) (0)
A cross-layer approach to cognitive computing: invited (2022) (0)
Network-Aware Content Shaping for Energy Efficient Wireless Web Access (2002) (0)
A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks (2022) (0)
FLEXBUS: A High-Performance System-on-Chip Communication Architecture with a Dynamically (2005) (0)
Floor Plan (2011) (0)
Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective. (2022) (0)
STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection (2016) (0)
Method and apparatus for optimizing the performance of register transfer level, in particular with a glitch analysis and reduction (1998) (0)
IP1 Interactive Presentations (2019) (0)
Front matters (2013) (0)
Session details: Design methodologies meet network applications (2002) (0)
Reading spin-torque memory with spin-torque sensors (2013) (0)
MedMon: A Novel Device for Monitoring Medical Device Security (2012) (0)
Fast System - Leve I Battery-Eff icient Power Profiling System Design for * (2002) (0)
Session details: Dynamic Power and Thermal Management (2016) (0)
Securing mobile appliances: new challenges for the system designer (2003) (0)
Session details: Hot topic - test challenges for low power devices (2008) (0)
Innovations in test automation (2002) (0)
Input space-adaptive optimization for embedded-software synthesis (2005) (0)
ECE 595Z Lecture 19: Multi-level Synthesis VI (2012) (0)
ECE 595Z Lecture 23: Timing Analysis and Optimization III (2012) (0)
STeP-CiM: Strain-Enabled Ternary Precision Computation-In-Memory Based on Non-Volatile 2D Piezoelectric Transistors (2022) (0)
A defense framework against malware and vulnerability exploits (2014) (0)
Emerging challenges in designing secure mobile appliances (2003) (0)
ECE 595Z Lecture 3: Advanced Boolean Algerbra I (2012) (0)

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What Schools Are Affiliated With Anand Raghunathan?

Anand Raghunathan is affiliated with the following schools:

Purdue University