Andr ´ E. Dehon | Academic Influence

Q: What Schools Are Affiliated With Andr ´ E. Dehon

Andr ´ E. Dehon is affiliated with the following schools: California Institute of Technology, University of Pennsylvania

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Andr ´ E. Dehon's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation (2007) (550)
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources (1996) (418)
Reconfigurable architectures for general-purpose computing (1996) (388)
Array-based architecture for FET-based, nanoscale electronics (2003) (365)
The Density Advantage of Configurable Computing (2000) (331)
Nanowire-based programmable architectures (2005) (257)
Nanowire-based sublithographic programmable logic arrays (2004) (214)
DPGA-coupled microprocessors: commodity ICs for the early 21st Century (1994) (200)
Reconfigurable computing: what, why, and implications for design automation (1999) (193)
Seeking Solutions in Configurable Computing (1997) (186)
Floating-point sparse matrix-vector multiply for FPGAs (2005) (185)
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization) (1999) (182)
Stochastic assembly of sublithographic nanoscale interfaces (2003) (180)
Reconfigurable Computing Architectures (2015) (173)
Packet Switched vs. Time Multiplexed FPGA Overlay Networks (2006) (148)
Molecular electronics: devices, systems and tools for gigagate, gigabit chips (2002) (141)
Seven strategies for tolerating highly defective fabrication (2005) (140)
DPGA Utilization and Application (1996) (138)
Fault Secure Encoder and Decoder for NanoMemory Applications (2009) (136)
Pathfinder : A Negotiation-Based Performance-Driven Router for FPGAs (2012) (134)
HSRA: high-speed, hierarchical synchronous reconfigurable array (1999) (132)
Stream Computations Organized for Reconfigurable Execution (SCORE) (2000) (131)
Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density (1996) (124)
A greedy algorithm for tolerating defective crosspoints in nanoPLA design (2004) (122)
Fast module mapping and placement for datapaths in FPGAs (1998) (120)
Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security (2013) (117)
GraphStep: A System Architecture for Sparse-Graph Algorithms (2006) (106)
Nonphotolithographic nanoscale memory density prospects (2005) (104)
Architectural Support for Software-Defined Metadata Processing (2015) (94)
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation (2005) (85)
A verified information-flow architecture (2014) (84)
Stream computations organized for reconfigurable execution (2006) (81)
Design patterns for reconfigurable computing (2004) (76)
FPGA optimized packet-switched NoC using split and merge primitives (2012) (71)
Hardware-assisted simulated annealing with application for fast FPGA placement (2003) (69)
Parallelizing sparse Matrix Solve for SPICE circuit simulation using FPGAs (2009) (61)
Hardware-assisted fast routing (2002) (58)
Compact, multilayer layout for butterfly fat-tree (2000) (58)
Object oriented circuit-generators in Java (1998) (57)
Automatic impedance control (1993) (54)
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder (2011) (52)
Vision for cross-layer optimization to address the dual challenges of energy and reliability (2010) (52)
Comparing computing machines (1998) (52)
Design of FPGA interconnect for multilevel metallization (2003) (50)
Design of programmable interconnect for sublithographic programmable logic arrays (2005) (47)
Array-Based Architecture for Molecular Electronics (2001) (47)
BreakApp: Automated, Flexible Application Compartmentalization (2018) (46)
3D Nanowire-Based Programmable Logic (2006) (44)
Radial addressing of nanowires (2006) (43)
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors (2009) (42)
PUMP: a programmable unit for metadata processing (2014) (42)
Optimistic Parallelization of Floating-Point Accumulation (2007) (40)
Stream Computations Organized for Reconfigurable Execution (SCORE) Extended Abstract (2000) (40)
Accelerating SPICE Model-Evaluation using FPGAs (2009) (39)
METRO: a router architecture for high-performance, short-haul routing networks (1994) (36)
Flightplan: Dataplane Disaggregation and Placement for P4 Programs (2021) (35)
Unifying mesh- and tree-based programmable interconnect (2004) (34)
Array-Based Architecture for FET-Based, (2003) (34)
VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems (2009) (33)
Choose-your-own-adventure routing: Lightweight load-time defect avoidance (2011) (33)
Scalability Simulations for Nanomemory Systems Integrated on the Molecular Scale (2003) (32)
Inversion schemes for sublithographic programmable logic arrays (2009) (31)
A Streaming Multi-Threaded Model (2001) (30)
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration (2011) (30)
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction (2015) (29)
Very Large Scale Spatial Computing (2002) (29)
${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA (2012) (28)
Limit study of energy & delay benefits of component-specific routing (2012) (27)
Birth and adolescence of reconfigurable computing: a survey of the first 20 years of field-programmable custom computing machines (2013) (27)
Preliminary design of the SAFE platform (2011) (26)
Fundamental Underpinnings of Reconfigurable Computing Architectures (2015) (25)
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine (2002) (25)
Deterministic addressing of nanoscale devices assembled at sublithographic pitches (2005) (25)
Entropy, Counting, and Programmable Interconnect (1996) (25)
Protecting the Stack with Metadata Policies and Tagged Hardware (2018) (24)
Impact of Memory Architecture on FPGA Energy Consumption (2015) (24)
Fault Secure Encoder and Decoder for Memory Applications (2007) (24)
Law of large numbers system design (2004) (23)
DeepMatch: practical deep packet inspection in the data plane using network processors (2020) (23)
Robust, High-Speed Network Design for Large-Scale Multiprocessing (1993) (23)
Rent's rule based switching requirements (2001) (21)
Stochastic, spatial routing for hypergraphs, trees, and meshes (2003) (21)
Fault tolerant nano-memory with fault secure encoder and decoder (2007) (21)
Spatial hardware implementation for sparse graph algorithms in GraphStep (2011) (21)
Hardware Support for Safety Interlocks and Introspection (2012) (20)
In-network computing to the rescue of faulty links (2018) (19)
Fat-Tree Routing for Transit (1990) (19)
SAFE: A clean-slate architecture for secure systems (2013) (18)
Final report for CCS cross-layer reliability visioning study (2010) (18)
Delta: prototype for a first-generation dynamically programmable gate array (1995) (18)
Reconfigurable Computing: What, Why, Design Automation Requirements (1999) (17)
Area-Efficient Near-Associative Memories on FPGAs (2015) (17)
Trust-Management, Intrusion-Tolerance, Accountability, and Reconstitution Architecture (TIARA) (2009) (17)
Architecture approaching the atomic scale (2007) (16)
Fault Tolerant Design for Multistage Routing Networks (1990) (16)
Crystals and Snowflakes: Building Computation from Nanowire Crossbars (2011) (15)
1 Volt digital logic circuits realized by stress-resilient ALN parallel dual-beam MEMS relays (2012) (14)
Fault-tolerant sub-lithographic design with rollback recovery (2008) (14)
06361 Executive Report -- Computing Media Languages for Space-Oriented Computation (2007) (14)
Computing Media and Languages for Space-Oriented Computation, 03.09. - 08.09.2006 (2007) (14)
Accurate Parallel Floating-Point Accumulation (2013) (14)
Trends toward spatial computing architectures (1999) (14)
Exploiting partially defective LUTs: Why you don't need perfect fabrication (2013) (14)
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks (2019) (13)
Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations (2014) (12)
GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction (2014) (12)
Variation and Aging Tolerance in FPGAs (2011) (12)
An ultra-low-energy, variation-tolerant fpga architecture using component-specific mapping (2013) (12)
Area-efficient near-associative memories on FPGAs (2013) (11)
The Dover inherently secure processor (2017) (11)
Towards Fine-grained, Automated Application Compartmentalization (2017) (10)
Choose-your-own-adventure routing: lightweight load-time defect avoidance (2009) (10)
Case for Fast FPGA Compilation Using Partial Reconfiguration (2018) (10)
Location, location, location: the role of spatial locality in asymptotic energy minimization (2013) (10)
Stochastic spatial routing for reconfigurable networks (2006) (10)
Impact of Parallelism and Memory Architecture on FPGA Communication Energy (2016) (9)
Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction (2021) (9)
In-system timing extraction and control through scan-based, test-access ports (1994) (9)
Fast Linking of Separately-Compiled FPGA Blocks without a NoC (2020) (8)
Semantic-Aware Hot Data Selection Policy for Flash File System in Android-Based Smartphones (2013) (7)
Energy Reduction through Differential Reliability and Lightweight Checking (2014) (7)
Defect and Fault Tolerance (2008) (7)
Ignis: scaling distribution-oblivious systems with light-touch distribution (2019) (7)
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices (2006) (7)
Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication (2016) (6)
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction (2013) (6)
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development (2022) (6)
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging (2011) (6)
Programming FPGA Applications in VHDL (2008) (5)
Pipelined Parallel Finite Automata Evaluation (2019) (5)
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP) (2016) (5)
Hierarchical Synchronous Recon gurable Array (1999) (5)
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement (2016) (4)
Scan-based testability for fault-tolerant architectures (1992) (4)
μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts (2021) (4)
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads (2011) (4)
Pipelining saturated accumulation (2005) (4)
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays (2017) (4)
MATRIX: A reconfigurable computing device with configurable instruction distribution (1997) (4)
Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks (1994) (4)
Saliency on a chip: a digital approach with an FPGA (2004) (3)
Micro-Policies : A Framework for Verified , Tag-Based Security Monitors (2014) (3)
Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization (2014) (3)
Directions in general-purpose computing architectures (1997) (3)
SAT-based optimal hypergraph partitioning with replication (2006) (3)
Sublithographic pro-grammable logic arrays (2004) (2)
Reliable integration of terascale systems with nanoscale devices (2008) (2)
The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low) (2008) (2)
Operating System Support for Reconfigurable Computing (2008) (2)
06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation (2007) (2)
FCCM ’ 94-- IEEE Workshop on FPGAs for Custom Computing Machines April 10-13 , Napa , CA DPGA-Coupled Microprocessors : Commodity ICs for the Early 21 st Century (2007) (2)
RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks (2014) (2)
Practical schemes for fat-tree network construction (1991) (2)
Pipelining saturated accumulation (2009) (2)
Saliency on a chip (2007) (2)
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation (2022) (2)
Fault tolerance and performance of multipath multistage intereonneetion networks (1992) (2)
The Case for Reconfigurable Processors (2007) (2)
Reconfigurable Computing and Nanoscale Architecture (2008) (2)
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers (2022) (1)
Stochastic Assembly of Sublithographic (2003) (1)
11 Nanowire-Based Programmable Architectures (2010) (1)
CMOS vs Nano: comrades or rivals? (2009) (1)
Mir: Automated Quantifiable Privilege Reduction Against Dynamic Library Compromise in JavaScript (2020) (1)
High Performance, Point-to-Point, Transmission Line Signaling (1998) (1)
Accelerating the SPICE Circuit Simulator Using an FPGA: A Case Study (2013) (1)
DeepMatch (2020) (1)
XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion (2021) (1)
Compute Models and System Architectures (2008) (1)
Self-Adaptive Timing Repair (2017) (1)
Graph parallel actor language --- a programming language for parallel graph algorithms (2013) (1)
Energy minimization in the time-space continuum (2015) (1)
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration (2022) (0)
Three-dimensional storage array (2003) (0)
2012 JETTA Reviewers (2013) (0)
Chapter 9 – Stream Computations Organized for Reconfigurable Execution (2008) (0)
NIRT : Technologies , Architectures and Performance Analysis for Nanoelectronics (2005) (0)
A 11 Patent Number : 5 , 629 , 637 45 Date of Patent : May 13 , 1997 (2017) (0)
Introduction to Special Section on FCCM 2019 (2020) (0)
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays (2006) (0)
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation (2021) (0)
System architectures and design patterns for reconfigurable computing (2005) (0)
Chapter 36 – Theoretical Underpinnings (2008) (0)
Progress Reports - Interconnect: A Fundamental Constraint (2001) (0)
Rent ’ s Rule Based Switching Requirements [ Extended Abstract ] (2001) (0)
Crystals and Snowflakes: Building Computation from Stochastically-Assembled, Defect- and Variation-prone Nanowire Crossbars (2011) (0)
Sublithographic Architecture: Shifting the Responsibility for Perfection (2009) (0)
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays (2007) (0)
Welcome message from the chairs (2021) (0)
Rent ’ s Rule Based Switching Requirements [ Extended (2001) (0)
Guest Editorial (2007) (0)
Fault-tolerant design for multistage routing networks. Memorandum report (1990) (0)
Special Issue on the 2006 International Symposium on Field-Programmable Gate Arrays (2007) (0)
PERFECT case studies demonstrating order of magnitude reduction in power consumption (2016) (0)
Sub-lithographic nano-range storage architecture (2003) (0)
HLS-Compatible, Embedded-Processor Stream Links (2021) (0)
Session details: New directions in FPGA technologies (2005) (0)
Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs (2008) (0)
Tutorial 1: Emerging Technologies for VLSI Design (2006) (0)
Procede et dispositif pour placer un element (2003) (0)
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems (2021) (0)
An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications (2010) (0)
THREE-DIMENSIONAL PACKAGING FOR HIGH-PERFORMANCE INTERCONNECT IN LARGE-SCALE VLSI SYSTEMS (1995) (0)
Appearing: 1992 IEEE Workshop on Defect and Fault Tolerance in VLSI Systems (1992) (0)
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006 (2006) (0)
Low-Power Techniques for FPGAs (2011) (0)
Programming FPGAs for Economics: An Introduction to Electrical Engineering Economics (2022) (0)
High‐Reliability Computing For The Smarter Planet (2011) (0)
Guest Editorial (2007) (0)
Compiling C for Spatial Computing (2008) (0)
Introduction to the Special Section on Nano Systems and Computing (2007) (0)
Recognized as the Best: The ACM\/SIGDA TCFPGA Hall of Fame for FPGAs and Reconfigurable Computing (2018) (0)
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007 (2007) (0)
Fat-Tree Routing for Transit Andr 6 DeHod (0)
The Design of a Polymorphous Cognitive Agent Architecture (PCAA) (2008) (0)
A Streaming Multi-Threaded Model Extended (2001) (0)
Advanced Technologies and Reliable Design for Nanotechnology Systems (2009) (0)
Introduction to Special Issue on Reconfigurable Components with Source Code (2016) (0)
Configurable computing offers the potential of producing powerful new computing systems. Will current research overcome the dearth of commercial applicability to make such systems a reality (1997) (0)
VMATCH:UsingLogicalVariationtoCounteract PhysicalVariationinBottom-Up,NanoscaleSystems (2009) (0)
Session 26: Evening Panel Discussion Nanoelectronics - Now or Never? (2004) (0)
AnNoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-OrientedWorkloads (2019) (0)
What is the right model for programming and using modern FPGAs? (2004) (0)
SCALPEL: Exploring the Limits of Tag-enforced Compartmentalization (2022) (0)

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What Schools Are Affiliated With Andr ´ E. Dehon?

Andr ´ E. Dehon is affiliated with the following schools: