Avinoam Kolodny
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Israeli engineer
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Avinoam Kolodnyengineering Degrees
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Electrical Engineering
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Applied Physics
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#3140
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Engineering
Why Is Avinoam Kolodny Influential?
(Suggest an Edit or Addition)According to Wikipedia, Avinoam Kolodny is an Israeli professor of electrical engineering at Technion. He is an author and co-author of more than 160 books and peer-reviewed articles all of which were cited 6548 times.
Avinoam Kolodny's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- TEAM: ThrEshold Adaptive Memristor Model (2013) (609)
- QNoC: QoS architecture and design process for network on chip (2004) (603)
- MAGIC—Memristor-Aided Logic (2014) (517)
- VTEAM: A General Model for Voltage-Controlled Memristors (2015) (487)
- Interconnect-power dissipation in a microprocessor (2004) (470)
- Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies (2014) (465)
- MRL — Memristor Ratioed Logic (2012) (217)
- Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training (2015) (204)
- Analysis and modeling of floating-gate EEPROM cells (1986) (163)
- Memristor-based IMPLY logic design procedure (2011) (137)
- HNOCS: Modular open-source simulator for Heterogeneous NoCs (2012) (121)
- Cost considerations in network on chip (2004) (113)
- Many-Core vs. Many-Thread Machines: Stay Away From the Valley (2009) (107)
- Effective Radii of On-Chip Decoupling Capacitors (2008) (83)
- QNoC asynchronous router (2009) (82)
- The Power of Priority: NoC Based Distributed Cache Coherency (2007) (79)
- Logic operations in memory using a memristive Akers array (2014) (79)
- The Desired Memristor for Circuit Designers (2013) (77)
- Two components of tunneling current in metal‐oxide‐semiconductor structures (1983) (74)
- Network Delays and Link Capacities in Application-Specific Wormhole NoCs (2007) (65)
- Routing Table Minimization for Irregular Mesh NoCs (2007) (65)
- Efficient Link Capacity and QoS Design for Network-on-Chip (2006) (63)
- The Devolution of Synchronizers (2010) (63)
- Properties of ion-implanted junctions in mercury—cadmium—telluride (1980) (63)
- Models of memristors for SPICE simulations (2012) (63)
- Comparative analysis of serial vs parallel links in NoC (2004) (61)
- Parallel vs. serial on-chip communication (2008) (59)
- Automatic hardware-efficient SoC integration by QoS network on chip (2004) (46)
- Utilizing shared data in chip multiprocessors with the Nahalal architecture (2008) (44)
- On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits (2005) (44)
- Asynchronous Current Mode Serial Communication (2010) (44)
- Best of both worlds: A bus enhanced NoC (BENoC) (2009) (42)
- High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link (2007) (41)
- Access Regulation to Hot-Modules in Wormhole NoCs (2007) (37)
- A Cost Effective Centralized Adaptive Routing for Networks-on-Chip (2011) (36)
- Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip (2005) (35)
- Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With $RC$ Interconnect (2010) (35)
- Delay analysis of wormhole based heterogeneous NoC (2011) (35)
- Fast asynchronous shift register for bit-serial communication (2006) (34)
- Centralized Adaptive Routing for NoCs (2010) (31)
- The response of small photovoltaic detectors to uniform radiation (1977) (31)
- Distributed Adaptive Routing Convergence to Non-Blocking DCN Routing Assignments (2014) (27)
- Efficiency optimization of integrated DC-DC buck converters (2010) (27)
- NoCs simulation framework for OMNeT++ (2011) (27)
- Nahalal: Cache Organization for Chip Multiprocessors (2007) (26)
- Threads vs. caches: Modeling the behavior of parallel workloads (2010) (24)
- Links as a service (LaaS): Guaranteed tenant isolation in the shared cloud (2015) (23)
- Memristor-Based Multithreading (2014) (22)
- Distributed adaptive routing for big-data applications running on Data Center Networks (2012) (20)
- Timing-driven variation-aware nonuniform clock mesh synthesis (2010) (20)
- Handling global traffic in future CMP NoCs (2012) (19)
- Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing (2014) (19)
- A clock tuning circuit for system–on–chip (2003) (19)
- Timing-aware power-optimal ordering of signals (2008) (19)
- Heterogeneous NoC Router Architecture (2015) (18)
- Optimal bus sizing in migration of processor design (2006) (18)
- Low-leakage repeaters for NoC interconnects (2005) (18)
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION ( (2014) (17)
- Crosstalk noise reduction in synthesized digital logic circuits (2003) (16)
- Two-dimensional effects in intrinsic photoconductive infrared detectors (1982) (16)
- Trace cache sampling filter (2005) (16)
- Designing single-cycle long links in hierarchical NoCs (2014) (16)
- Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study (2010) (15)
- An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm (2011) (15)
- A clock tuning circuit for system–on–chip (2002) (15)
- Multistate Register Based on Resistive RAM (2015) (15)
- n-channel MOS transistors in mercury—cadmium—telluride (1980) (15)
- QoS architecture and design process for cost effective Network on Chip (2004) (14)
- Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing (2006) (14)
- Maximum effective distance of on-chip decoupling capacitors in power distribution grids (2006) (14)
- BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP (2008) (14)
- Leveraging symbiotic on-die decoupling capacitance (2005) (14)
- Power-delay optimization in VLSI microprocessors by wire spacing (2009) (12)
- Automated measurement and analysis of MIS interfaces in narrow-bandgap semiconductors (1981) (12)
- The era of many-modules SoC: revisiting the NoC mapping problem (2009) (12)
- Link Division Multiplexing (LDM) for Network-on-Chip Links (2006) (11)
- Design and modelling of network on chip interconnects using transmission lines (2004) (11)
- Performance and Power Aware CMP Thread Allocation Modeling (2010) (11)
- On-die decoupling capacitance: frequency domain analysis of activity radius (2006) (11)
- Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors (2010) (10)
- Nahalal: Memory Organization for Chip Multiprocessors (2006) (10)
- Efficient Routing in Irregular Topology NoCs (10)
- Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs) (2013) (10)
- On optimal ordering of signals in parallel wire bundles (2008) (10)
- Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip Rostislav ( Reuven ) (2004) (10)
- Static timing analysis for modeling QoS in networks-on-chip (2011) (9)
- Low Power Clock Network Design (2011) (9)
- Frequency dependent efficiency model of on-chip DC-DC buck converters (2010) (9)
- Optimizing heterogeneous NoC design (2012) (9)
- ACCMP-assymetric cluster chip-multiprocessing (2004) (8)
- Exploring the limits of GPGPU scheduling in control flow bound applications (2012) (8)
- Diffusion Properties of Cadmium in Indium Antimonide (1978) (8)
- Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization (2006) (8)
- Multi-Net Optimization of VLSI Interconnect (2014) (7)
- Hebbian Learning Rules with Memristors (2013) (7)
- Timing optimization in logic with interconnect (2008) (7)
- Exploration of energy-delay tradeoffs in digital circuit design (2008) (6)
- A useful method for approximating the profile of ions implanted through a thin film (1977) (6)
- Micro-modem - reliability solution for NoC communications (2004) (5)
- Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing (2015) (5)
- EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems (2016) (5)
- Packet-level static timing analysis for NoCs (2009) (5)
- Power grid analysis based on a macro circuit model (2010) (5)
- Design and dynamic management of hierarchical NoCs (2016) (5)
- Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints (2011) (5)
- Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip (2013) (4)
- Interconnect Bundle Sizing Under Discrete Design Rules (2010) (4)
- IIB-1 two components of tunneling current in metal-oxide-semiconductor structures (1983) (4)
- Multi-aggressor capacitive and inductive coupling noise modeling and mitigation (2012) (4)
- Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud (2019) (4)
- Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks (2013) (4)
- Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology (2005) (4)
- Networks on chips: keeping up with rent's rule and moore's law (2007) (4)
- Power efficient tree-based crosslinks for skew reduction (2009) (3)
- Diffusion profiling using the graded C(V) method (1980) (3)
- Optimal resizing of bus wires in layout migration (2004) (3)
- Energy Efficient System Architectures (2017) (3)
- The design of a latency constrained, power optimized NoC for a 4G SoC (2009) (3)
- Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects (2003) (3)
- Gana: A novel low-cost conflict-free NoC architecture (2013) (3)
- Memristive multistate pipeline register (2014) (2)
- Such a CAD! (2010) (2)
- Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696] (2010) (2)
- Special Section on International Symposium on Networks-on-Chip (NOCS) (2009) (2)
- Average latency and link utilization analysis of heterogeneous wormhole NoCs (2015) (2)
- On VLSI interconnect optimization and linear ordering problem (2011) (2)
- ViLoCoN - An ultra-lightweight lossless VLSI video codec (2013) (2)
- An Overview of the VLSI Interconnect Problem (2015) (2)
- Simple Design Criterion for Maximizing Data Rate in NoC Links (2006) (2)
- Links as a Service (LaaS): Feeling Alone in the Shared Cloud (2015) (2)
- Task Scheduling Based On Thread Essence and Resource Limitations (2012) (1)
- Memristors and Related Applications (2011) (1)
- Mercury-Cadmium-Telluride (1980) (1)
- Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization (2004) (1)
- IIB-3 analysis and modeling of floating-gate E2Prom cells (1983) (1)
- Delay analysis of wormhole based heterogeneous NoC (2012) (1)
- Power-Optimal Ordering of Signals in Parallel Wire Bundles (2007) (1)
- Why Not Data Trace Cache (1)
- Optimizing Read-Once Data Flow in Big-Data Applications (2017) (1)
- Performance scalability and dynamic behavior of Parsec benchmarks on many-core processors (2014) (1)
- Curing Hotspots in Wormhole NoCs (2005) (1)
- Dynamic Programming Algorithm for Interconnect Channel Sizing in Discrete Design Rules (2009) (1)
- Thread allocation directed by performance-power tradeoff in NoC-based CMPs (2010) (1)
- An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design (2006) (1)
- Current gain of shallow-junction lateral transistors (1979) (1)
- The complexity of VLSI power-delay optimization by interconnect resizing (2012) (1)
- Interconnects in ULSI Systems: Cu Interconnects Electrical Performance (2009) (1)
- Net-by-Net Wire Optimization (2015) (0)
- Can Hot Traces Improve Value Prediction ? (2003) (0)
- Multiple Multithread Applications on Asymmetric and Symmetric Chip MultiProcessors (2008) (0)
- BENoC : A bus-Enhanced Network on-Chip Isask ' har Walter , Israel Cidon and (2007) (0)
- Interconnect power and delay optimization by dynamic programming in gridded design rules (2010) (0)
- Delay-Optimal Ordering of Wires in Interconnect Channels (2006) (0)
- Trace classification and its use for profile-based trace cache management (2001) (0)
- NOCS 2007 Committees (2007) (0)
- BENoC: A Bus-Enhanced Network on-Chip (2007) (0)
- Nanosession: Logic Devices and Circuit Design (2013) (0)
- Usage of Trace Cache for Predicting Power Saving Opportunities (2008) (0)
- Energy metrics for power efficient crosslink and mesh topologies (2012) (0)
- LinkDivision Multiplexing (LDM)forNetwork-on-Chip Links (2006) (0)
- Interconnect Aspects in Design Methodology and EDA Tools (2015) (0)
- Future Directions in Interconnect Optimization (2015) (0)
- Aneffective technique forsimultaneous interconnect channel delayand noisereduction innanometer VLSIdesign (2006) (0)
- Memory Intensive Computing (2014) (0)
- Multi-net Sizing and Spacing in General Layouts (2015) (0)
- Coping with the Complexity of Microprocessor Design at Intel – A CAD History (2010) (0)
- Scaling Dependent Electrical Modeling of Interconnects (2015) (0)
- Interconnect Optimization by Net Ordering (2015) (0)
- Simple Design Criterion forMaximizing DataRateinNoCLinks (2006) (0)
- Timing aware power minimization in VLSI circuits by simultaneous multilayer wire spacing (2010) (0)
- Frameworks for Interconnect Optimization (2015) (0)
- The complexity of VLSI power-delay optimization by interconnect resizing (2010) (0)
- Symmetric Hill Order - an Optimal Solution of a Linear Ordering Adjacency Problem (2008) (0)
- Multi-net Sizing and Spacing of Bundle Wires (2015) (0)
- Energy efficient addition by two-sided carry-reverse computation (2012) (0)
- Asynchronous Bit-stream Compression (ABC) (2006) (0)
- Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study (2011) (0)
- Wire Spacing , Planar Graphs and the Minimization of Dynamic Power in VLSI Microprocessors (2008) (0)
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What Schools Are Affiliated With Avinoam Kolodny?
Avinoam Kolodny is affiliated with the following schools:
