Axel Jantsch

Q: What Schools Are Affiliated With Axel Jantsch

Axel Jantsch is affiliated with the following schools: TU Wien, Mid Sweden University, KTH Royal Institute of Technology

Axel Jantsch's AcademicInfluence.com Rankings

Axel Jantsch

Computer Science

#8303

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#8729

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Database

#5325

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#5526

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Computer Science

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Axel Jantsch's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A network on chip architecture and design methodology (2002) (1325)
Networks on chip (2003) (621)
Network on Chip : An architecture for billion transistor era (2000) (485)
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (2004) (428)
The Nostrum backbone-a communication protocol stack for Networks on Chip (2004) (240)
Modeling embedded systems and SoCs - concurrency and time in models of computation (2003) (213)
Methods for fault tolerance in networks-on-chip (2013) (204)
Load distribution with the proximity congestion awareness in a network on chip (2003) (189)
Run-time Partial Reconfiguration speed investigation and architectural design space exploration (2009) (181)
System modeling and transformational design refinement in ForSyDe [formal system design] (2004) (166)
SPECTR (2018) (155)
The Benefits of Self-Awareness and Attention in Fog and Mist Computing (2015) (149)
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip (2003) (146)
Fog Computing in the Internet of Things (2018) (114)
An Analytical Latency Model for Networks-on-Chip (2013) (108)
Models of computation and languages for embedded system design (2005) (100)
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router (2013) (100)
Interconnect-Centric Design for Advanced SOC and NOC (2010) (94)
TDM Virtual-Circuit Configuration for Network-on-Chip (2008) (89)
A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip (2010) (86)
NNSE: Nostrum Network-on-Chip Simulation Environment (2005) (84)
Connection-oriented multicasting in wormhole-switched networks on chip (2006) (83)
Evaluation of on-chip networks using deflection routing (2006) (82)
Simulation and Evaluation of a Network on Chip Architecture Using Ns-2 (2002) (69)
Hardware/software partitioning and minimizing memory interface traffic (1994) (68)
Toward Smart Embedded Systems (2016) (64)
Scalability of network-on-chip communication architecture for 3-D meshes (2009) (63)
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip (2008) (61)
Designing 2D and 3D Network-on-Chip Architectures (2013) (56)
Mathematical formalisms for performance evaluation of networks-on-chip (2013) (52)
A High Level Power Model for the Nostrum NoC (2006) (51)
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (2010) (51)
Self-awareness in remote health monitoring systems using wearable electronics (2017) (51)
Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A Survey (2020) (50)
Towards Open Network-on-Chip Benchmarks (2007) (50)
3D Integration for NoC-based SoC Architectures (2010) (49)
Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach (2015) (49)
Power analysis of link level and end-to-end data protection in networks on chip (2005) (47)
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management (2018) (47)
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip (2010) (46)
Models of Computation for Networks on Chip (2006) (45)
Feasibility analysis of messages for on-chip networks using wormhole routing (2005) (45)
Adaptive Power Management for the On-Chip Communication Network (2006) (44)
Network on Chip (2002) (44)
FPGA resource and timing estimation from Matlab execution traces (2002) (43)
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era (2017) (43)
Flow regulation for on-chip communication (2009) (41)
Dark silicon aware runtime mapping for many-core systems: A patterning approach (2015) (41)
Dark silicon aware power management for manycore systems under dynamic workloads (2014) (40)
Neural network based ECG anomaly detection on FPGA and trade-off analysis (2017) (39)
Power-efficient tree-based multicast support for Networks-on-Chip (2011) (39)
Malicious LUT: A stealthy FPGA Trojan injected and triggered by the design flow (2016) (39)
Evaluating NoC communication backbones with simulation (2003) (38)
Buffer Optimization in Network-on-Chip Through Flow Regulation (2010) (37)
Self-Awareness in Systems on Chip— A Survey (2017) (37)
A Network-based System Architecture for Remote Medical Applications (2007) (35)
Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks (2009) (34)
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (2009) (34)
MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip (2015) (33)
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip (2011) (31)
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration (2006) (31)
Will Networks on Chip Close the Productivity Gap? (2003) (30)
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization (2000) (30)
The Dark Side of Silicon (2017) (29)
A software oriented approach to hardware-software co-design (1994) (29)
Self-aware Cyber-Physical Systems-on-Chip (2015) (29)
Computer-aided Arrhythmia Diagnosis with Bio-signal Processing (2019) (29)
On the roles of functions and objects in system specification (2000) (28)
Energy efficient streaming applications with guaranteed throughput on MPSoCs (2008) (28)
Extending platform-based design to network on chip systems (2003) (27)
Comprehensive Observation and its Role in Self-Awareness; An Emotion Recognition System Example (2016) (27)
A case study on hardware/software partitioning (1994) (27)
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads (2006) (27)
Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (2012) (26)
Constrained global scheduling of streaming applications on MPSoCs (2010) (26)
Models of Embedded Computation (2005) (25)
Traffic configuration for evaluating networks on chips (2005) (25)
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip (2007) (24)
Device Driver and DMA Controller Synthesis from HW /SW Communication Protocol Specifications (2001) (24)
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures (2003) (24)
HetMoC: Heterogeneous Modelling in SystemC (2010) (24)
Fog Computing Fundamentals in the Internet-of-Things (2018) (24)
Flit ejection in on-chip wormhole-switched networks with virtual channels (2004) (23)
Layered Switching for Networks on Chip (2007) (22)
MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis (2006) (22)
Flit admission in on-chip wormhole-switched networks with virtual channels (2004) (22)
Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC (2013) (22)
Approximation knob: Power Capping meets energy efficiency (2016) (21)
A survey of memory architecture for 3D chip multi-processors (2014) (21)
Development and application of design transformations in ForSyDe [high level synthesis] (2003) (21)
Parallel probe based dynamic connection setup in TDM NoCs (2014) (21)
adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning (2018) (21)
Formal system design based on the synchrony hypothesis, functional models, and skeletons (1999) (21)
Modeling and analysis of Rayleigh fading channels using stochastic network calculus (2011) (21)
Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation (2018) (20)
An Initiative towards Open Network-on-Chip Benchmarks (2007) (20)
System synthesis based on a formal computational model and skeletons (1999) (20)
A case study of hardware and software synthesis in ForSyDe (2002) (20)
Modelling Adaptive Systems in ForSyDe (2008) (19)
Enhancing the Early Warning Score System Using Data Confidence (2016) (19)
Network Calculus Applied to Verification of Memory Access Performance in SoCs (2007) (19)
A framework of awareness for artificial subjects (2014) (18)
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime (2004) (18)
SAMBA – an architecture for adaptive cognitive control of distributed Cyber-Physical Production Systems based on its self-awareness (2018) (18)
Grammar based modelling and synthesis of device drivers and bus interfaces (1998) (18)
A Perspective on Dark Silicon (2017) (18)
Operating system sensitive device driver synthesis from implementation independent protocol specification (1999) (18)
Efficient Design-for-Test Approach for Networks-on-Chip (2019) (18)
Memristors' Potential for Multi-bit Storage and Pattern Learning (2015) (18)
Special issue on networks on chip (2004) (17)
ATCA-based computation platform for data acquisition and triggering in particle physics experiments (2008) (17)
Towards hierarchical cluster based cache coherence for large-scale network-on-chip (2009) (17)
Non-Blocking Testing for Network-on-Chip (2016) (17)
Enhancement of Classification of Small Data Sets Using Self-awareness — An Iris Flower Case-Study (2018) (17)
A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip (2012) (17)
The Andres Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems (2007) (17)
Interactive Hardware-Software Partitioning and Memory Allocation Based on Data Transfer Profiling (1995) (16)
An algorithm for electing cluster heads based on maximum residual energy (2006) (16)
Optimal regulation of traffic flows in networks-on-chip (2010) (16)
Performance analysis with confidence intervals for embedded software processes (2001) (16)
NoCs: a new contract between hardware and software (2003) (16)
The Rugby Model: a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems (1999) (16)
Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations (2011) (16)
Dynamic Computation Migration at the Edge: Is There an Optimal Choice? (2019) (15)
System level verification of digital signal processing applications based on the polynomial abstraction technique (2005) (15)
ForSyDe: System Design Using a Functional Language and Models of Computation (2017) (15)
Transformational System Design based on a Formal Computational Model and Skeletons (2000) (15)
Performance analysis of reconfiguration in adaptive real-time streaming applications (2008) (15)
Admitting and ejecting flits in wormhole-switched networks on chip (2007) (15)
Self-Aware Fog Computing in Private and Secure Spheres (2018) (15)
Transformation based communication and clock domain refinement for system design (2002) (14)
A Reconfigurable Design Framework for FPGA Adaptive Computing (2009) (14)
HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation (2018) (14)
MASCOT: a specification and cosimulation method integrating data and control flow (2000) (14)
System synthesis utilizing a layered functional model (1999) (14)
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (2010) (14)
Energy-efficient and Reliable Wearable Internet-of-Things through Fog-Assisted Dynamic Goal Management (2019) (13)
EWD: A metamodeling driven customizable multi-MoC system modeling framework (2007) (13)
Verification of design decisions in ForSyDe (2003) (13)
Trends of terascale computing Chips in the next ten years (2009) (13)
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration (2008) (13)
Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals (2019) (13)
Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing (2010) (12)
A flow regulator for On-Chip Communication (2009) (12)
Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips (2010) (12)
TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint (2018) (12)
Hardware/software co-design of an ATCA-based computation platform for data acquisition and triggering (2009) (12)
Modeling of mixed control and dataflow systems in MASCOT (2001) (12)
Speedup analysis of data-parallel applications on Multi-core NoCs (2009) (12)
The usage of stochastic processes in embedded system specifications (2001) (12)
Comparison of Six Languages for System Level Descriptions of Telecom Systems (1998) (12)
A Dynamically Reconfigurable FPGA-based Content Addressable Memory for IP Characterization (2000) (12)
Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip (2012) (11)
Traffic Splitting with Network Calculus for Mesh Sensor Networks (2007) (11)
International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2020, Singapore, September 20-25, 2020 (2020) (11)
SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system (2008) (11)
Heterogeneous system-level cosimulation with SDL and Matlab (2001) (11)
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation (2018) (11)
Fully digital write-in scheme for multi-bit memristive storage (2016) (11)
Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations (2010) (11)
Communication in Hardware/Software Embedded Systems - A Taxonomy and Problem Formulation (1997) (11)
Low-power and error coding for network-on-chip traffic (2004) (11)
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005 (2005) (11)
A framework for designing congestion-aware deterministic routing (2010) (10)
Memory Architecture and Management in an NoC Platform (2012) (10)
Evaluation of deflection routing on various NoC topologies (2011) (10)
Synthesis of DMA controllers from architecture independent descriptions of HW/SW communication protocols (1999) (10)
On the design of context-aware health monitoring without a priori knowledge; an AC-Motor case-study (2017) (10)
VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping (2016) (10)
System design for DSP applications in transaction level modeling paradigm (2004) (10)
High-level synthesis of control and memory intensive communication systems (1995) (10)
ResCoNN: Resource-Efficient FPGA-Accelerated CNN for Traffic Sign Classification (2019) (10)
ADDHard: Arrhythmia Detection with Digital Hardware by Learning ECG Signal (2018) (10)
Low-power and error protection coding for network-on-chip traffic (2008) (10)
MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels (2015) (10)
Is there a Niche for a General Protocol Processor (1998) (10)
Composite signal flow: a computational model combining events, sampled streams, and vectors (2000) (10)
SAMBA: A self-aware health monitoring architecture for distributed industrial systems (2017) (10)
Performance analysis and design space exploration for high-end biomedical applications: Challenges and solutions (2007) (10)
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design (2008) (10)
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory (2010) (9)
Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing (2010) (9)
Highway in TDM NoCs (2015) (9)
Hierarchical dynamic goal management for IoT systems (2018) (9)
Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks (2012) (9)
Performance analysis of on-chip bufferless router with multi-ejection ports (2015) (9)
Towards Verification of Uncertain Cyber-Physical Systems (2017) (9)
Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores (2018) (9)
Multi-FPGA implementation of a Network-on-Chip based many-core architecture with fast barrier synchronization mechanism (2010) (9)
Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics (2007) (9)
Exploring ASIC design space at system level with a neural network estimator (1994) (9)
The Rugby Model : A Framework for the Study of Modelling, Analysis, and Synthesis Concepts in Electronic Systems (1999) (9)
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications (2017) (9)
UMoC++ : Modeling Environment for Heterogeneous Systems based on Generic MoCs (2005) (8)
System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments (2008) (8)
Deterministic Worst-Case Performance Analysis for Wireless Sensor Networks (2008) (8)
IRSYD : An Internal Representation for Heterogeneous Embedded Systems (1998) (8)
Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology (2007) (8)
Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs (2013) (8)
System oriented VLSI curriculum at KTH (1997) (8)
Design of Fault-Tolerant and Reliable Networks-on-Chip (2015) (8)
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns (2013) (8)
Costs and benefits of flexibility in spatial division circuit switched networks-on-chip (2013) (8)
Confidence-Enhanced Early Warning Score Based on Fuzzy Logic (2019) (8)
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems (2011) (8)
Scalability of relaxed consistency models in NoC based multicore architectures (2010) (8)
Toggle MUX: How X-optimism can lead to malicious hardware (2017) (8)
Scalability of weak consistency in NoC based multicore architectures (2010) (8)
Models of computation in the design process (2006) (8)
A Metamodel for Studying Concepts in Electronic System Design (2000) (7)
UMoC++: A C++-Based Multi-MoC Modeling Environment (2006) (7)
Validation of Interface Protocols Using Grammar-based Models (1998) (7)
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation (2014) (7)
Model-free condition monitoring with confidence (2019) (7)
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels (2015) (7)
FPGA-based adaptive computing for correlated multi-stream processing (2010) (7)
The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems (2016) (7)
A novel allocation strategy for control and memory intensive telecommunication circuits (1996) (6)
RoSA: A Framework for Modeling Self-Awareness in Cyber-Physical Systems (2020) (6)
FPGA-Based Particle Recognition in the HADES Experiment (2011) (6)
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks (2011) (6)
A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications (2012) (6)
HW/SW Interface Validation in IP based System Design (1998) (6)
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property (2013) (6)
Distributed SDN architecture for NoC-based many-core SoCs (2019) (6)
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (2012) (6)
An object-oriented concept for intelligent library functions (1998) (6)
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh (2009) (6)
Priority based forced requeue to reduce worst-case latencies for bursty traffic (2009) (6)
Embedded Systems Handbook - CONTENTS (2005) (6)
Improved Machine Learning using Confidence (2019) (6)
A Programmable Protocol Processor Architecture for High Speed Internet Protocol Processing (2000) (6)
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems (2012) (6)
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication (2006) (6)
Communication Performance in Network-on-Chips (2003) (6)
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems (2011) (6)
Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach (2010) (6)
Rescuing healthy cores against disabled routers (2014) (6)
Hardware synthesis of an ATM multiplexer from SDL to VHDL: a case study (1999) (6)
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip (2016) (5)
Self-Adaptive QoS Management of Computation and Communication Resources in Many-Core SoCs (2019) (5)
Formal Design Based on the Synchronous Approach, Functional Models and Skeletons (1999) (5)
System design for DSP applications using the MASIC methodology (2004) (5)
Cooperative communication based barrier synchronization in on-chip mesh architectures (2011) (5)
Scalable Multi Core Architectures (2015) (5)
Modelling Environment for Heterogeneous Systems based on MoCs (2005) (5)
High-level estimation and trade-off analysis for adaptive real-time systems (2009) (5)
Stochastic coverage in event-driven sensor networks (2011) (5)
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation (2018) (5)
Applicability of Context-Aware Health Monitoring to Hydraulic Circuits (2018) (5)
Modelling and Synthesis of Operational and Management System (OAM) of ATM Switch Fabrics (1995) (5)
Zero-load predictive model for performance analysis in deflection routing NoCs (2015) (5)
A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs (2015) (5)
Refinement of A Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication Service (2005) (5)
Grammar-based design of embedded systems (2001) (5)
Testcase Development for Large Telecom Systems (1997) (4)
Hardware/Software Cosynthesis for Reconfigurable Systems (1996) (4)
A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments (2011) (4)
Wireless Network-on-Chips as Autonomous Systems : A Novel Solution for Biomedical Healthcare and Space Exploration Sensor-Networks (2005) (4)
Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs (2014) (4)
The Promises and Limitations of 3-D Integration (2011) (4)
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning (2011) (4)
A power efficient flit-admission scheme for wormhole-switched networks on chip (2005) (4)
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops (2007) (4)
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique (2010) (4)
Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications (2015) (4)
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling (2011) (4)
Multi-Objective Power Management for CMPs in the Dark Silicon Age (2017) (4)
IRSYD - An Internal Representation for System Description. Version 0.1 (1997) (4)
MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences (2020) (4)
Models of Embedded Computation for Distributed Embedded Systems (2009) (4)
Embodied Self-Aware Computing Systems (2020) (4)
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs (2015) (3)
The Spidergon STNoC (2014) (3)
Trade-offs in High-level Synthesis of Telecommunication Circuits (1995) (3)
Evaluation of Languages for Specification of Telecom Systems (1998) (3)
Architecture Exploration of Interconnection Networks as a Communication Layer for Reconfigurable Systems (2003) (3)
DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques (1994) (3)
Network-on-Chip Assembler Language (2003) (3)
A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs (2014) (3)
Nostrum Network-on-Chip Simulation Environment (2005) (3)
On-Chip Dynamic Resource Management (2019) (3)
ANNETTE: Accurate Neural Network Execution Time Estimation With Stacked Models (2021) (3)
Partitioning and Minimizing Memory Interface Traffic (1994) (3)
Neural Network Based Estimator to Explore the Design Space at System Level (1994) (3)
Optimizing the location of ECC protection in Network-on-Chip (2016) (3)
A low-power, medium-resolution, high-speed CMOS pipelined ADC (2010) (3)
Analysis of Traffic Splitting Mechanisms for 2D Mesh Sensor Networks (2008) (3)
Error-Tolerant Interconnect Schemes (2005) (3)
AKKA: a tool-kit for cosynthesis and prototyping (1996) (3)
A Versatile Design Validation Environment by Means of Software Execution, Hardware Simulation, and Emulation (1994) (3)
Refining synchronous communication onto network-on-chip best-effort services (2006) (3)
Trigger algorithm development on FPGA-based Compute Nodes (2009) (3)
Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy (2007) (3)
Trends in On-chip Dynamic Resource Management (2018) (3)
Hybrid Distributed Shared Memory Space in Multi-core Processors (2011) (3)
Multi-phase Validation of Hardware/Software Interfaces based on Generated Simulation Models (1998) (3)
VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments (2018) (3)
TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip (2012) (3)
System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost (2012) (3)
Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication (2018) (3)
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips (2014) (3)
A Survey of Design Transformation Techniques (1999) (3)
Network-on Chip Micro-Benchmarks (2008) (3)
MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks (2019) (3)
Design Space Exploration for an IoT Node: Trade-Offs in Processing and Communication (2021) (3)
Network-on-Chip multicasting with low latency path setup (2011) (3)
Intelligent Management of Mobile Systems through Computational Self-Awareness (2020) (2)
Blackthorn: Latency Estimation Framework for CNNs on Embedded Nvidia Platforms (2021) (2)
C-Based Design of Heterogeneous Embedded Systems (2008) (2)
Area and Performance Optimization of Barrier Synchronization on Multi-core Network-on-Chips (2010) (2)
SmartDPM: Machine Learning-Based Dynamic Power Management for Multi-Core Microprocessors (2018) (2)
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments (2011) (2)
Design of a 1 GIPS Peak Performance Processor using GaAs Technology (1994) (2)
The MOSART Mapping Optimization for Multi-Core ARchiTectures (2010) (2)
Scalability analysis of release and sequential consistency models in NoC based multicore systems (2012) (2)
Autonomous Systems, Trust, and Guarantees (2022) (2)
Control and communication performance analysis of embedded DSP systems in the MASIC methodology (2001) (2)
Refinement of HW/SW Communication Channels : Case Study and Comparision (1998) (2)
Synchronization after design refinements with sensitive delay elements (2007) (2)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2022) (2)
SpaceBall-1G: A 32-bit 1 GIPS Peak Performance MIMD CPU Targeted for GaAs (1995) (2)
Floating- to Fixed-Point Refinement in Matlab with an Object-Oriented Library (1999) (2)
Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases (2000) (2)
A packet-switched interconnect for many-core systems with BE and RT service (2015) (2)
Integrated Circuits and Systems Series (2017) (2)
Efficient distributed memory management in a multi-core H.264 decoder on FPGA (2013) (2)
A rule-based approach for improving allocation of filter structures in HLS (1996) (2)
A comparison of six languages for system level description of telecom applications (2001) (2)
NoC Verification and Testing (2014) (2)
BABBAGE - A Rule basedtool for synthesis of hardware systems (1994) (2)
Estimation of Statistical Bandwidth through Backlog Measurement (2012) (2)
Simulation and analysis of embedded DSP systems using MASIC methodology (2003) (2)
Can Dark Silicon Be Exploited to Prolong System Lifetime? (2017) (2)
A 1 GIPS Peak Performance Multi-Threaded Processor Core Using Interleaved Processing And A Revolving register File Targeted for GaAs (1995) (2)
Towards a Formal Model of Recursive Self-Reflection (2019) (2)
A Network on Chip Simulator Master of Science Thesis in Electronic System Design by Rikard Thid Stockholm August (1)
Exploring stacked main memory architecture for 3D GPGPUs (2015) (1)
Simulation of Real Home Healthcare Sensor Networks Utilizing IEEE 802.11g Biomedical Network-on-Chip (2005) (1)
Multicore Processing and ARTEMIS (2006) (1)
A Case Study on Hardwardsoftware Partitioning (1994) (1)
Collision-Free Deep Reinforcement Learning for Mobile Robots using Crash-Prevention Policy (2021) (1)
A Study of NoC Exit Strategies (2007) (1)
Guest Editorial: Special Issue on Self-Aware Systems on Chip (2017) (1)
Building reliable systems-on-chip in nanoscale technologies (2015) (1)
Empowering autonomy through self-awareness in MPSoCs (2017) (1)
The Pyramid Model : A General Framework for Study of Modelling, Analysis and Synthesis concepts of Electronic Systems (1997) (1)
Proc. IFIP International Conference on Very Large Scale Integration (VLSI-SoC) (2003) (1)
A Generic Scheme for Communication Representation and Mapping (1999) (1)
SDF to Synchronous Cross Domain Analysis in ForSyDe Stream Processing Framework (2006) (1)
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures (2007) (1)
Generalization of Slot Table Size for Virtual Circuits on Nostrum Networks on Chip (2008) (1)
Evaluation of Languages for Specification of Complex Telecom Systems (1998) (1)
Neural Network Compression Through Shunt Connections and Knowledge Distillation for Semantic Segmentation Problems (2021) (1)
Concept and design of exhaustive-parallel search algorithm for Network-on-Chip (2011) (1)
Dynamic Constraints for Mixed-Criticality Systems (2019) (1)
Scalability of Transaction Counter based Relaxed Consistency Models in NoC based Multicore Architectures (2009) (1)
Scalability and Performance Evaluation of Memory Consistency Models in NoC based Multicore SoCs (2012) (1)
The Untimed Model of Computation (2003) (1)
Comparative Cost Analysis of 3-D Integrated Circuits (2011) (1)
Resource Allocation for QoS On-Chip Communication (2009) (1)
Simulation and analysis of embedded DSP systems using Petri nets (2003) (1)
Hardware Design and Synthesis in ForSyDe (2009) (1)
3-D integration and the limits of silicon computation (2011) (1)
A Worst Case Performance Model for TDM Virtual Circuit in NoCs (2010) (1)
Rugby : A Meta-Model to Study Concepts in Electronic System Design (2000) (1)
Polynomial abstraction for verification of sequentially implemented combinational circuits (2004) (1)
A simple state transition control for FSM programmable protocol processors (2000) (1)
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips (2015) (1)
Analytical approaches for performance evaluation of networks-on-chip (2012) (1)
Adaptively Reconfigurable Controller for the Flash Memory (2011) (1)
ADDHard (2018) (1)
A New Protocol for Electing Cluster head Based on Maximum Residual Energy (2006) (1)
A Methodology for Resilient Control and Monitoring in Smart Grids (2020) (1)
A System Design Methodology Based on a Formal Computational Model (1999) (1)
NoC Modeling and Topology Exploration (2014) (1)
Addressing the Execution Control Problem in Mixed-Criticality Systems (2018) (1)
ECG-BIONET : A global biomedical network for human heart monitoring and analysis: Performance needs of an electrocardiogram Telemedicine platform for medical aid at the point-of-need (2006) (1)
Cognitive Architectures for Process Monitoring - an Analysis (2020) (1)
Hardware-Software Codesign for Multirate DSP System Development (1994) (1)
INSTITUT FÜR COMPUTERTECHNIK / INSTITUTE OF COMPUTER TECHNOLOGY (2016) (0)
A Capability Library for High Level Synthesis (1992) (0)
Physical Performance Modelling for Platform-based SoC Design (2002) (0)
Hardware Synthesis of an ATM Multiplexer Modelled in SDL : A Case Study (1999) (0)
An Analysis of the relation between a dataflow graph and its implementations (1992) (0)
Compositional Specification and Verification for System-on-chip Design (1999) (0)
chapter nine – Applications (2003) (0)
Session details: Hot topic - the memory challenge in NoC based systems (2008) (0)
An Analytical Approach for Dimensioning Mixed Traffic Networks (2007) (0)
Control and Com m unication Perform ance Analysis of Em bedded DSP System s in the MASIC Methodology (2001) (0)
The Timed Model of Computation (2003) (0)
Design and Implementation of Lookup Table in Multicast Supported Router (0)
Clearsyde, a Graphical User Interface for the Forsyde Methodology Clearsyde, a Graphical User Interface for the Forsyde Methodology Acknowledgements (2002) (0)
Middleware Memory Management in NoC (2014) (0)
Evaluation of Reinforcement Learning Methods for a Self-learning System (2020) (0)
0 Adaptively Reconfigurable Controller for the Flash Memory (2011) (0)
Introduction to the Speical Issue on Self-Awareness in Resource Constrained CPS (0)
Refinement of Perfectly Synchronous Communication Model (2005) (0)
Special Section on Hardware/Software Codesign and System Synthesis II : Guest editorial (2006) (0)
Multicast Path Setup Incorporating Evicting (2012) (0)
Networks on Chip : Approaches and Challenges (2004) (0)
Modeling the Efficiency of Stacked Silicon Systems: Computational, Thermal and Electrical Performance (2011) (0)
Message from the chairs - Welcome to CODES+ISSS 2004! (2004) (0)
AKKA : A Codesign Environment (1995) (0)
Design and Implementation of a Fat Tree Network on Chip Master of Science (2004) (0)
Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009 (2010) (0)
2009 List of Reviewers (2009) (0)
Two special register addressing modes for internet protocol processing (2002) (0)
The Nostrum Platform Definition (2006) (0)
Dark Silicon Patterning: Efficient Power Utilization Through Run-Time Mapping (2017) (0)
Power and Thermal Effects and Management (2014) (0)
Chapter 2 The Promises and Limitations of 3-D Integration (2019) (0)
Modeling Communication with Synchronized Environments (2008) (0)
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip (2017) (0)
Improving Deep Learning Based Anomaly Detection on Multivariate Time Series Through Separated Anomaly Scoring (2022) (0)
Integration of Physical and Functional Electronic System Representations in Electronic Curriculum (1997) (0)
Editorial introduction (2009) (0)
On-Chip Distributed Architectures (2006) (0)
Interactive Design Considered Harmful (1997) (0)
Implementation of Acoustic Echo Cancellation For PC Applications Using MATLAB Master of (2007) (0)
Fingerprint identification using mathematical morphology Master of Science Thesis in Electronic System Design by Fredrik Claesson (0)
chapter ten – Concluding Remarks (2003) (0)
Parallelized Flight Path Prediction using a Graphics Processing Unit (2017) (0)
Hierarchical multipliers: A framework for high-speed multiple error detecting architectures (2022) (0)
Diagnostic Services in Network Diagnostic Services in Network - - on on - - Chips Chips ⎯ ⎯ Test, Debug, and On Test, Debug, and On - Line Monitoring Line Monitoring ⎯ (2008) (0)
THE PLATFORM AS AN INTERFACE IN A SOC DESIGN CURRICULUM (2004) (0)
Editorial introduction (1997) (0)
Bekka - A System Specification and Design Framework (1997) (0)
Design and Implementation of Router Supporting for Multicast On-chip (2011) (0)
Internal Representation for Specification and Design of Heterogenous Systems (1997) (0)
chapter six – MoC Interfaces (2003) (0)
chapter seven – Tightly Coupled Process Networks (2003) (0)
Master of Science Thesis In Electronic System Design (2009) (0)
On Designing 3-D Platforms (2014) (0)
A Group of Subword Instructions and Design Issues for Network Processing RISC Cores (2003) (0)
Impact of Input Data on Intelligence Partitioning Decisions for IoT Smart Camera Nodes (2021) (0)
Network-on-Chip Assembler Language ( Version 0 . 1 ) (2003) (0)
Improvements of Performance and Use of Buffers in NoCs using Dual Packet Exit (2007) (0)
INVESTIGATION OF A/D CONVERTERS FOR IMPLANTABLE DEVICES Msc Thesis Project (2009) (0)
SAMBA – an architecture for adaptive cognitive control of distributed Cyber-Physical Production Systems based on its self-awareness (2018) (0)
An Authentication Framework for Nomadic (2009) (0)
Latency System Throughput Resource Utilization Power and Energy Life-time Reliability Thermal Stability Performance Driven Throughput Driven Lifetime Reliability Driven Varying Workload and User Demands Time Goal System Aberrations and Constraints Hierarchical Dynamic Goal (2017) (0)
Study of DNN-Based Ragweed Detection from Drones (2022) (0)
Load/Store Unit Design of a Programmable Internet Protocol Processor (2002) (0)
Multicore Processing and ARTEMIS-An incentive to develop the European Multiprocessor research (2006) (0)
NoC-Based System Integration (2014) (0)
Communicating with Synchronized Environments (2006) (0)
Experiences using Akka: A Hardware-Software Codesign Tool Kit in design of Telecommunication systems (1995) (0)
Modelling of Operation and Maintance Functions in the ATM Network (1995) (0)
Network-on-Chip Technology: A Paradigm Shift (2014) (0)
Building reliable systems-on-chip in nanoscale technologies (2015) (0)
Definition of Device Level Interface with QoS : Draft Specification (2007) (0)
Context Aware Monitoring for Smart Grids (2021) (0)
FPGA Based Embedded Neural Network Object Detector (2021) (0)
Modular and Distributed Management of Many-Core SoCs (2021) (0)
Using the Revolver Architecture for Data Processing in Heterogeneous Systems (2001) (0)
Design Issues for Nanoscale CMOS (2005) (0)
On-Chip Dynamic Resource Managemen (2019) (0)
A flexible register access control for programmable protocol processors (2001) (0)
DATE 07 workshop on diagnostic services in NoCs (2007) (0)
Formal System Specification Models for Verification and Refinement (1999) (0)
Limitations of Interactive Design (1997) (0)
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing (2017) (0)
Self-selection pseudo- circuit: a clever crossbar pre-allocation (2012) (0)
The Development and Application of Formal Design Transformations in ForSyDe (2003) (0)
Reliable Power Efficient Systems through Run-time Reconfiguration (2022) (0)
Design of D-AMPS Channel Decoder with Codesign Methodologies (1996) (0)
Resource Constrained Self-Aware Cyber-Physical Systems (Tutorial) (2019) (0)
Projects on Network-on-Chip (2014) (0)
Behavior and Concurrency (2003) (0)
Functional Validation for Large Telecom Systems (2000) (0)
Python Wraps Yosys for Rapid Open-Source EDA Application Development (2019) (0)
Dynamic Fault Tree Models for FPGA Fault Tolerance and Reliability (2021) (0)
Nondeterminism and Probability (2003) (0)
EAMS1: More SystemC for “More than Moore” (2011) (0)
Design Space Exploration with Design Style Description and Estimation Functions (1992) (0)
Two-Volume Slipcase Set Available for a Limited Time Only! (2009) (0)
The Synchronous Model of Computation (2003) (0)
Simulation and Performance Evaluation for Networks on Chip Master of Science Thesis (0)
Orthogonal High-Level Synthesis from Grammar-based Specifications (2001) (0)
A flexible configuration approach for fault-tolerant multicast/unicast (2011) (0)
The SYSMANTIC NoC Design and Prototyping Framework (2014) (0)
Modeling of Dynamic Resource Allocation in a Network on Chip Master of Science Thesis (2005) (0)
Information Flow Tracking Methods for Protecting Cyber-Physical Systems against Hardware Trojans - a Survey (2022) (0)
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004 (2004) (0)
Integrated Electronic Systems Program - A National Research Program (1999) (0)
Area Estimation in the High Level Synthesis Using Neural Networks (1994) (0)
Proc. ACM/IEEE International Symposium on Networks-on-Chip (NOCS) (2011) (0)
A Study on Confidence: An Unsupervised Multiagent Machine Learning Experiment (2022) (0)
MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGA (2021) (0)
Market Research for Data Management Engine (2009) (0)
An algorithm of electing cluster head in beacon node distributions based on maximum residual energy (2005) (0)
Cluster-based Simu ate nnea ing for apin ores onto esh etworks on C 1 (2009) (0)
Performance Analysis and Architectural Refinement of Embedded DSP Systems in the MASIC Methodology (2002) (0)
Run Time Power and Accuracy Management with Approximate Circuits (2022) (0)
Markov Model for Availability Assessment of PLC in Industrial IoT Considering Subsystems Failures (2022) (0)
Hades : An Environment for Design Space Exploration (1993) (0)
Calculation of delivery rate in fault-tolerant network-on-chips (2016) (0)
Refinement for Communication-Based Design (2003) (0)
Introduction to the Special Issue on Self-Aware Cyber-physical Systems (2020) (0)
Object Oriented Approach versus Functional Approach in System Design (2000) (0)

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