Bashir Al-Hashimi | Academic Influence

Bashir Al-Hashimi's AcademicInfluence.com Rankings

Bashir Al-Hashimi

Engineering

#6717

World Rank

#8055

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Electrical Engineering

#2231

World Rank

#2337

Historical Rank

engineering Degrees

Bashir Al-Hashimi

Computer Science

#8168

World Rank

#8590

Historical Rank

Computer Architecture

#65

World Rank

#67

Historical Rank

Computer Engineering

#129

World Rank

#130

Historical Rank

computer-science Degrees

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Engineering
Computer Science

Bashir Al-Hashimi's Degrees

PhD Electronics and Computer Science University of Southampton
Masters Electronics and Computer Science University of Southampton
Bachelors Electronics and Computer Science University of Southampton

Why Is Bashir Al-Hashimi Influential?

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According to Wikipedia, Bashir Mohammed Ali Al-Hashimi, CBE, FRS, FREng, FIEEE, FIET, FBCS is a recognised multidisciplinary global researcher with sustained and pioneering contributions to computer engineering and a prominent academic and higher education leader. He is Vice President and ARM Professor of Computer Engineering at King's College London in the United Kingdom. He was the co-founder and co-director of the ARM-ECS Research Centre, an industry-university collaboration partnership involving the University of Southampton and ARM. He is actively involved in promoting science and engineering for young people and regularly contributes to engineering higher education and skills national debates.

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Bashir Al-Hashimi's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems (2015) (223)
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction (2004) (191)
Variable-length input Huffman coding for system-on-a-chip test (2003) (185)
Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices (2016) (166)
Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression (2002) (143)
Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems (2004) (133)
A survey of multi-source energy harvesting systems (2013) (128)
Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes (2011) (126)
System-Level Design Techniques for Energy-Efficient Embedded Systems (2003) (120)
Energy-efficient mapping and scheduling for DVS enabled distributed embedded systems (2002) (111)
Considering power variations of DVS processing elements for energy minimisation in distributed systems (2001) (105)
Power-constrained testing of VLSI circuits (2003) (103)
Improving routing efficiency for network-on-chip through contention-aware input selection (2006) (103)
Reinforcement learning-based inter- and intra-application thermal optimization for lifetime improvement of multicore systems (2014) (99)
Single fully differential current conveyor biquad filters (2003) (87)
Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs (2017) (80)
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems (2006) (76)
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection (2007) (74)
Modeling SWCNT Bandgap and Effective Mass Variation Using a Monte Carlo Approach (2010) (70)
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks (2013) (70)
Numerically Efficient Modeling of CNT Transistors With Ballistic and Nonballistic Effects for Circuit Simulation (2010) (69)
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks (2010) (69)
Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations (2019) (67)
Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks (2007) (67)
Unified active filter biquad structures (2004) (66)
A Survey of FPGA-Based LDPC Decoders (2016) (66)
Low-Energy Standby-Sparing for Hard Real-Time Systems (2012) (65)
Scheduling and mapping of conditional task graphs for the synthesis of low power embedded systems (2003) (64)
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems (2009) (62)
Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems (2016) (60)
Analytical synthesis of current-mode high-order OTA-C filters (2003) (60)
A comparison of power output from linear and nonlinear kinetic energy harvesters using real vibration data (2013) (60)
Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding (2002) (59)
Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs (2011) (59)
Graceful Performance Modulation for Power-Neutral Transient Computing Systems (2016) (58)
Application of analog adaptive filters for dynamic sensor compensation (2005) (57)
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems (2004) (56)
Energy-Aware Simulation for Wireless Sensor Networks (2009) (56)
Photovoltaic Sample-and-Hold Circuit Enabling MPPT Indoors for Low-Power Systems (2012) (55)
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits (2006) (55)
Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip (2001) (54)
Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing (2000) (53)
Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores (2018) (52)
Cache size selection for performance, energy and reliability of time-constrained systems (2006) (52)
System-on-Chip: Next Generation Electronics (2006) (52)
Adaptive and Hierarchical Runtime Manager for Energy-Aware Thermal Management of Embedded Systems (2016) (51)
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation (2008) (51)
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning (2015) (49)
An Empirical Energy Model for Supercapacitor Powered Wireless Sensor Nodes (2008) (49)
Defect-tolerant n2-transistor structure for reliable nanoelectronic designs (2009) (49)
Rapid generation of thermal-safe test schedules (2005) (48)
Proceedings of the Conference on Design, Automation and Test in Europe (2010) (47)
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving (2006) (46)
VLSI Implementation of Fully Parallel LTE Turbo Decoders (2016) (45)
An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks (2010) (44)
Approaches to Transient Computing for Energy Harvesting Systems: A Quantitative Evaluation (2015) (44)
Dual multiple-polynomial LFSR for low-power mixed-mode BIST (2003) (44)
New high-order filter structures using only single-ended-input OTAs and grounded capacitors (2004) (43)
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits (2002) (43)
Current mode single resistance controlled oscillators using only grounded passive components (2002) (41)
Evaluation and design exploration of solar harvested-energy prediction algorithm (2010) (40)
20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications (2016) (40)
Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry (2009) (40)
Scan architecture for shift and capture cycle power reduction (2002) (40)
Minimization of crosstalk noise, delay and power using a modified bus invert technique (2004) (39)
Energy-driven computing: Rethinking the design of energy harvesting systems (2017) (39)
Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities (2005) (38)
Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs (2017) (38)
A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation (2013) (38)
Dynamic Voltage Scaling Aware Delay Fault Testing (2006) (38)
Enhancing Delay Fault Coverage through Low Power Segmented Scan (2006) (38)
Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture (2011) (38)
Simultaneous scheduling, allocation and binding in high level synthesis ndwidth (1997) (36)
Synchronization overhead in SOC compressed test (2005) (35)
Power profile manipulation: a new approach for reducing test application time under power constraints (2002) (35)
Bridging Fault Test Method With Adaptive Power Management Awareness (2008) (34)
Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems (2016) (34)
A compression-driven test access mechanism design approach (2004) (33)
Aging Benefits in Nanometer CMOS Designs (2017) (31)
Iterative schedule optimization for voltage scalable distributed embedded systems (2004) (31)
Current mode filter structure based on dual output transconductance amplifiers (1996) (31)
Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems (2015) (29)
Online Fault Tolerance Technique for TSV-Based 3-D-IC (2015) (29)
Learning-Based Run-Time Power and Energy Management of Multi/Many-Core Systems: Current and Future Trends (2017) (29)
Integrated universal biquad based on triple-output OTAs and using digitally programmable zeros (1998) (29)
Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems (2015) (29)
Process Variation-Aware Test for Resistive Bridges (2009) (29)
Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones (2015) (28)
A low-power, distributed, pervasive healthcare system for supporting memory (2011) (28)
Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits (2000) (27)
Dual transitions Petri Net based modelling technique for embedded systems specification (2001) (27)
Dynamic Energy and Thermal Management of Multi-core Mobile Platforms: A Survey (2020) (27)
Energy managed reporting for wireless sensor networks (2008) (27)
5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability (2017) (26)
1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications (2016) (26)
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy (2005) (26)
RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework (2012) (24)
Reliable Power Gating With NBTI Aging Benefits (2016) (24)
FPGA implementation of high performance FIR filters (1997) (24)
Current-mode group-delay equalisation using pole–zero mirroring technique (2000) (23)
Battery-aware dynamic voltage scaling in multiprocessor embedded system (2005) (23)
Diagnosis of Multiple-Voltage Design With Bridge Defect (2009) (23)
Power Minimisation Techniques for Testing Low Power VLSI Circuits (2000) (23)
Power conscious test synthesis and scheduling for BIST RTL data paths (2000) (23)
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates (2004) (23)
Sub-clock power-gating technique for minimising leakage power during active mode (2011) (22)
Asynchronous transient resilient links for NoC (2008) (22)
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints (2007) (22)
Dual Flow Nets: Modeling the control/data-flow relation in embedded systems (2006) (21)
Improved DFT for Testing Power Switches (2011) (21)
Energy-driven computing (2019) (21)
Analysing trade-offs in scan power and test data compression for system-on-a-chip (2002) (21)
Workload Change Point Detection for Runtime Thermal Management of Embedded Systems (2016) (20)
Hardware-Validated CPU Performance and Energy Modelling (2018) (20)
AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores (2020) (20)
An integrated approach to energy harvester modeling and performance optimization (2007) (20)
Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing (2002) (20)
The Art of Simulation Using PSpice: Analog and Digital (1995) (19)
Active Mode Subclock Power Gating (2014) (19)
BIST hardware synthesis for RTL data paths based on testcompatibility classes (2000) (19)
Energy Controlled Reporting for Industrial Monitoring Wireless Sensor Networks (2006) (19)
Multilayer Graphene FET Compact Circuit-Level Model With Temperature Effects (2014) (19)
Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes (2011) (19)
BRB: Mitigating Branch Predictor Side-Channels. (2019) (19)
Load cell response correction using analog adaptive techniques (2003) (18)
A co-design methodology for energy-efficient multi-mode embedded systems with consideration of mode execution probabilities (2003) (18)
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density (2008) (18)
Information Managed Wireless Sensor Networks with Energy Aware Nodes (2005) (18)
A New Approach for Transient Fault Injection Using Symbolic Simulation (2008) (17)
Soft error-aware design optimization of low power and time-constrained embedded systems (2010) (17)
Power constrained test scheduling using power profile manipulation (2001) (17)
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating (2015) (17)
Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores (2019) (17)
Minimizing Test Power in SRAM through Reduction of Pre-charge Activity (2006) (16)
Online concurrent workload classification for multi-core energy management (2018) (16)
Transistor-level based defect tolerance for reliable nanoelectronics (2008) (16)
Iterative Decoding for Redistributing Energy Consumption in Wireless Sensor Networks (2008) (16)
Serialized Asynchronous Links for NoC (2008) (16)
Empirical CPU power modelling and estimation in the gem5 simulator (2017) (16)
Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE (2019) (16)
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories (2015) (16)
A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder (2017) (16)
Impact of PVT variation on delay test of resistive open and resistive bridge defects (2013) (15)
A programmable time measurement architecture for embedded memory characterization (2005) (15)
HSPICE implementation of a numerically efficient model of CNT transistor (2009) (15)
A model-based framework for software portability and verification in embedded power management systems (2018) (15)
Current-Mode Delay Equalizer Design Using Multiple Output OTAs (2000) (14)
Machine learning for run-time energy optimisation in many-core systems (2017) (14)
A Structured Hardware/Software Architecture for Embedded Sensor Nodes (2008) (14)
Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs (2016) (14)
A fast, numerical circuit-level model of carbon nanotube transistor (2007) (14)
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip (2009) (14)
Collaborative Adaptation for Energy-Efficient Heterogeneous Mobile SoCs (2020) (14)
Nucleus (2017) (13)
Adaptive sampling in context-aware systems: A machine learning approach (2012) (13)
Synthesizing Energy-Efficient Embedded Systems with LOPOCOS (2002) (13)
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure (2017) (13)
Subthreshold FIR Filter Architecture for Ultra Low Power Applications (2009) (13)
Selective state retention design using symbolic simulation (2009) (13)
The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variation (2016) (13)
Resource aware sensor nodes in wireless sensor networks (2005) (13)
Efficient SI wave elliptic filters based on direct and inverse Bruton transformations (1999) (13)
Improved data compression for serial interconnected network on chip through unused significant bit removal (2006) (13)
An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters (2012) (13)
Robust channel identification scheme: Solving permutation indeterminacy of ICA for artifacts removal from ECG (2010) (13)
Variation resilient adaptive controller for subthreshold circuits (2009) (12)
Systematic generation of current mode dual-output OTA filters using a building block approach (1997) (12)
Sequence-Aware Watermark Design for Soft IP Embedded Processors (2016) (12)
Thermally-aware composite run-time CPU power models (2016) (12)
Exploring ARM mbed support for transient computing in energy harvesting IoT systems (2017) (12)
Modeling the impact of process variation on resistive bridge defects (2010) (12)
An automated design flow for vibration-based energy harvester systems (2009) (12)
Symbolic model checking of dual transition Petri Nets (2002) (12)
PoGo: an application-specific adaptive energy minimisation approach for embedded systems (2015) (12)
Vibration-powered sensing system for engine condition monitoring (2012) (12)
Energy Harvesting and Management for Wireless Autonomous Sensors (2008) (12)
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories (2018) (11)
Compression considerations in test access mechanism design (2005) (11)
Delay Test for Diagnosis of Power Switches (2014) (11)
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories (2007) (11)
Fast Design Space Exploration of Vibration-Based Energy Harvesting Wireless Sensors (2013) (11)
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation (2011) (11)
Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation (2003) (11)
Algorithm and Architecture for N-D Vector Cross-Product Computation (2011) (11)
Resistive Bridging Faults DFT with Adaptive Power Management Awareness (2007) (11)
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution (2006) (10)
Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders (2013) (10)
Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design (2015) (10)
Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters (2012) (10)
Workload-Aware Runtime Energy Management for HPC Systems (2018) (10)
Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry (2009) (10)
Design of Fixed-Point Processing Based Turbo Codes Using Extrinsic Information Transfer Charts (2010) (10)
Efficient scheduling of behavioural descriptions in high-level synthesis (1997) (10)
System-on-Chip: Next Generation Electronics (Circuits, Devices and Systems) (Circuits, Devices and Systems) (2006) (10)
Design of a 3 μm pixel linear CMOS sensor for earth observation (2003) (10)
Integrated approach to energy harvester mixed technology modelling and performance optimisation (2008) (10)
Power-conscious test synthesis and scheduling (2003) (9)
Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach (2013) (9)
Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery (2011) (9)
Dynamic sensor compensation using analogue adaptive filter compatible with digital technology (2005) (9)
Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations (2018) (9)
A PRACTICAL SELFPOWERED SENSOR SYSTEM WITH A TUNABLE VIBRATION ENERGY HARVESTER (2012) (9)
A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects (2011) (9)
Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling (2005) (9)
Advanced SIMD: Extending the reach of contemporary SIMD architectures (2014) (9)
Hardware efficient fixed-point VLSI architecture for 2D Kurtotic FastICA (2009) (9)
MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC (2008) (9)
Momentum: Power-neutral Performance Scaling with Intrinsic MPPT for Energy Harvesting Computing Systems (2019) (9)
Useless memory allocation in system-on-a-chip test: problems and solutions (2002) (9)
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint (2007) (8)
Current-mode elliptic filter design based on symmetrical current switching (2000) (8)
Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique (2011) (8)
A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator (2019) (8)
Transistor-Level Defect Tolerant Digital System Design at the Nanoscale Research Proposal Submitted to Internal Track Research Grant Programs (2010) (8)
Test data compression: the system integrator's perspective (2003) (8)
Co-ordinate rotation based low complexity 2D FastICA algorithm and architecture (2010) (8)
Gate-Sizing-Based Single $V_{\rm dd}$ Test for Bridge Defects in Multivoltage Designs (2010) (8)
Addressing useless test data in core-based system-on-a-chip test (2003) (8)
Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection (2007) (8)
BTI aware thermal management for reliable DVFS designs (2016) (8)
CMOS equaliser for compensating sinc(x) distortion of video D/A converters (1997) (8)
Dataset supporting the article entitled "ITMD: Run-time Management of Concurrent Multi-Threaded Applications on Heterogeneous Multi-cores" (2017) (8)
VHDL-AMS implementation of a numerical ballistic CNT model for logic circuit simulation (2008) (8)
A High-Throughput FPGA Architecture for Joint Source and Channel Decoding (2017) (8)
Voltage Selection for Time-Constrained Multiprocessor Systems (2007) (8)
Advancement in color image processing using Geometric Algebra (2008) (7)
On-chip timing measurement architecture with femtosecond resolution (2006) (7)
Optimising Resource Management for Embedded Machine Learning (2020) (7)
System-level design optimization of reliable and low power multiprocessor system-on-chip (2012) (7)
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation (2013) (7)
Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit (2016) (7)
Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation (2001) (7)
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing (2009) (7)
High Quality Testing of Grid Style Power Gating (2014) (7)
Applying of Quality of Experience to system optimisation (2013) (7)
Voltage Selection for Time-Constrained Multiprocessor Systems on Chip (2007) (7)
Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs (2017) (7)
MALEC: A Multiple Access Low Energy Cache (2013) (6)
Variation Aware Analysis of Bridging Fault Testing (2008) (6)
Ultra Low Power Multi-Operand Adder architecture for subthreshold circuits (2011) (6)
The Circuit Breaker Pattern Targeted to Future IoT Applications (2019) (6)
Reduced Z-datapath Cordic Rotator (2008) (6)
Modeling of Wireless Sensor Nodes Powered by Tunable Energy Harvesters: HDL-Based Approach (2012) (6)
Enabling the discovery of Adaptive Learning Resources for Mobile Learner (2012) (6)
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks (2008) (6)
Runtime Performance and Power Optimization of Parallel Disparity Estimation on Many-Core Platforms (2017) (6)
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation (2016) (6)
Linear programming design of FIR raised cosine filters with >100% excess bandwidth (1996) (6)
Versatile high-level synthesis of self-checking datapaths using an on-line testability metric (2003) (6)
IEE Proceedings: Computers and Digital Techniques Special issue on "Design and Test Conference in Europe", DATE 03 (2003) (6)
Exponential Golomb and Rice Error Correction Codes for Generalized Near-Capacity Joint Source and Channel Coding (2016) (6)
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study (2011) (6)
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links (2007) (6)
Thermal-aware Adaptive Energy Minimization of OpenMP Parallel Applications (2015) (6)
Efficient BIST hardware insertion with low test application time for synthesized data paths (1999) (6)
Low Power Process Assignment for Distributed Embedded Systems using Dynamic Voltage Scaling (2000) (5)
Content-Aware Power Saving Multimedia Adaptation for Mobile Learning (2013) (5)
Flexible and High-Speed System-Level Performance Analysis using Hardware-Accelerated Simulation (2013) (5)
Power-aware design method for class A switched-current wave filters (2004) (5)
High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation (2018) (5)
Improving the Tolerance of Stochastic LDPC Decoders to Overclocking-Induced Timing Errors: A Tutorial and a Design Example (2016) (5)
Reducing Synchronization Overhead in Test Data Compression Environments (2002) (5)
Useless Memory Allocation: Problems and Solutions (2002) (5)
Reducing Power Dissipation in SRAM during Test (2006) (5)
Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems (2017) (5)
Towards Automatic Code Generation of Run-Time Power Management for Embedded Systems Using Formal Methods (2015) (5)
Testing of Level Shifters in Multiple Voltage Designs (2007) (5)
DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test (2015) (5)
Energy minimisation for processor cores using variable supply voltages (2000) (4)
A Wireless Sensor Network for Cleanroom Monitoring (2008) (4)
Architecture Level Power-Performance Tradeoffs for Pipelined Designs (2007) (4)
Incremental Training and Group Convolution Pruning for Runtime DNN Performance Scaling on Heterogeneous Embedded Platforms (2019) (4)
A novel switched-current phase locked loop (2005) (4)
Energy-Aware Adaptation of Educational Multimedia in Mobile Learning (2013) (4)
Sixteenth International Workshop on Power and Timing Modeling, Optimization and Simulation (2006) (4)
Analyzing Trade-offs in Scan Power and Test Data Compression for Systems-ona-Chip (2002) (4)
Energy-Aware Streaming Multimedia Adaptation: An Educational Perspective (2014) (4)
Learner-battery interaction in energy-aware learning multimedia systems (2014) (4)
Online tuning of Dynamic Power Management for efficient execution of interactive workloads (2017) (4)
A new analytical model for predicting SWCNT band-gap from geometrical properties (2008) (4)
Diagnosis of power switches with power-distribution-network consideration (2015) (3)
Design Consideration and Implementation of Analog Adaptive Filters for Sensor Response Correction (2004) (3)
Design and implementation of digital systems for automatic control based on behavioural descriptions (1996) (3)
Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture (2011) (3)
The Unified Framework for Sensor Networks: A Systems Approach (2006) (3)
Scan based methodology for reliable state retention power gating designs (2010) (3)
Accurate and stable empirical CPU power modelling for multi- and many-core systems (2018) (3)
Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs (1999) (3)
Hardware and software innovations in energy-efficient system-reliability monitoring (2017) (3)
Analysis of Low Power Implementational Issues of Turbo-like Codes in Body Area Networks (2009) (3)
High performance distributed arithmetic FPGA decimators for video-frequency applications (1998) (3)
Analytical Synthesis of High-Order Voltage-Mode OTA-C All-Pass filters (2003) (3)
Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example (2017) (3)
Bridge Defect Diagnosis for Multiple-Voltage Design (2008) (3)
Clock-modulation based watermark for protection of embedded processors (2014) (3)
System-Level Design Methodology (2014) (3)
Power Profile Manipulation (2004) (3)
Iterative Schedule Optimisation for Voltage Scalable Distributed Embedded Systems (2003) (3)
Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects (2014) (3)
Minimising power dissipation in partial scan sequential circuits (2001) (3)
New dual output transconductance amplifier based biquad (1996) (3)
Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction (2005) (2)
A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems (2017) (2)
Co-Synthesis with Energy Minimisation for Heterogeneous Distributed Systems containing Power Managed Processing Elements (2001) (2)
A Bayesian Framework for Digital Twin-Based Control, Monitoring, and Data Collection in Wireless Systems (2022) (2)
Exploiting SWCNT structural variability towards the development of a photovoltaic device (2009) (2)
Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable g/sub m/-C structure (1999) (2)
Cost model driven test resource partitioning for socs (2006) (2)
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis (2005) (2)
IC Design and Manufacture for Undergraduates: Theory, Design and Practice (2008) (2)
Momentum (2019) (2)
High frequency active filters using OTAs (1989) (2)
Behavioural simulation of filters (1995) (2)
Generation of current mode filter structures using dual output transconductance amplifiers (1996) (2)
Fully integrated 533 mhz programmable switched current pll in 0.012 mm 2 (2008) (2)
Low-Complexity Architecture for Cyber-Physical Systems Model Identification (2019) (2)
Adaptive iterative detection for expediting the convergence of a serially concatenated Unary Error Correction decoder, turbo decoder and an iterative demodulator (2015) (2)
Efficient Switched Current Wave Elliptic Filters Based on Direct and Inverse Bruton Transformations (1999) (2)
Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing" (1998) (2)
Understand the Fundamental of Passive Video Filters (1996) (2)
Analysis of mirror mismatch and clock-feedthrough in Bruton transformation switched current wave filters (2003) (2)
Integrated high bandwidth wave elliptic lowpass switched-current filter in digital CMOS technology (2005) (2)
Constrained genetic algorithm design of finite precision FIR linear phase raised cosine filters (1998) (2)
Embedded Systems Modelling and Validation based on Extended Petri Nets (2001) (2)
Analogue adaptive filters using wave synthesis technique (2004) (2)
Nucleus: Finding the Sharing Limit of Heterogeneous Cores (2017) (2)
QUAREM: Maximising QoE Through Adaptive Resource Management in Mobile MPSoC Platforms (2022) (2)
Temporal Early Exits for Efficient Video Object Detection (2021) (2)
Design considerations for reliable embedded systems (2015) (2)
Dataset Supporting the article entitled "Predictive Thermal Management for Energy-efficient Execution of Concurrent Applications on Heterogeneous Multi-cores" (2019) (1)
Dataset supporting the article entitled "Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems" (2016) (1)
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space (2001) (1)
Improved stochastic LDPC decoder for correcting both channel-induced transmission errors and clock-scaling-induced timing errors (2013) (1)
Digital Twin-Based Multiple Access Optimization and Monitoring via Model-Driven Bayesian Learning (2022) (1)
Comparative reliability analysis between AMBA and network-on-chip: An MPEG-2 case study (2009) (1)
Non ideal performance of Bruton transformations switched current wave filters (2001) (1)
Collective-Aware System-on-Chips for Dependable IoT Applications (2018) (1)
A computer program for the design and analysis of linear phase FIR raised cosine filters (1996) (1)
The Superchip: Innovative teaching of IC design and manufacture (2008) (1)
Hardware development for pervasive healthcare systems: Current status and future directions (2008) (1)
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs (2018) (1)
Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction (2004) (1)
Analogue Filter IP Cores for Design Reuse (2002) (1)
Embedded microelectronic systems: status and trends (2005) (1)
Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications] (2005) (1)
Simplified logic design methodology for fuzzy membership function based robust detection of maternal modulus maxima location: A low complexity Fetal ECG extraction architecture for mobile health monitoring systems (2011) (1)
Test Strategies for Multivoltage Designs (2010) (1)
Solution of nonlinear equations in the synthesis of linear networks (1988) (1)
Co-Synthesis of Energy Efficient Multi-Mode Embedded Systems (2004) (1)
Low Power Systems-on-Chip (2002) (1)
Novel high-frequency continuous-time low-pass OTA based filters (1990) (1)
Mitigating Interactive Performance Degradation From Mobile Device Thermal Throttling (2020) (1)
Design of a low power MPEG-1 motion vector reconstructor (2009) (1)
Intra- and Inter-Server Smart Task Scheduling for Profit and Energy Optimization of HPC Data Centers (2020) (1)
Analysis and compensation of OTA non-ideal effects in video-frequency CMOS sinc(x) equalizers (1998) (1)
Tunable vibration energy harvester (2013) (1)
Test cost reduction through compression (2003) (1)
Dataset supporting the article entitled “Graceful performance modulation for power neutral transient computing systems" (2016) (1)
Fault-tolerance techniques for hybrid CMOS/nanoarchitecture (2010) (1)
Switched-current wave group delay equalisers (2004) (1)
On the implementation of video filters using current feedback amplifiers (1991) (1)
Complementary dataset to "Nucleus: Finding the sharing limit of heterogeneous cores" (2017) (1)
Graceful Performance Adaption through Hardware-Software Interaction for Autonomous Battery Management of Multicore Smartphones (2018) (1)
Run-time Detection and Mitigation of Power-Noise Viruses (2019) (1)
Application-specific memory protection policies for energy-efficient reliable design (2015) (1)
Comparative study of recursive digital filters using z and δ operators (1996) (1)
Finite and Infinite Model Checking of Dual Transition Petri Net Models (2002) (1)
Improving Compositional Verification of State-based Models by Reducing Modular Unbalance (2003) (1)
Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs (2016) (1)
Active Mode Sub-Clock Power Gating (2012) (1)
Dataset supporting the article entitled "Memory and Thread Synchronization Contention-Aware DVFS for HPC systems" (2018) (1)
System-level Design Techniques for Energy-efficient Embedded Systems System-level Design Techniques for Energy-efficient Embedded Systems Kluwer Academic Publishers (2013) (1)
New VCT based active filter configurations and their synthesis (1988) (1)
Application of group delay equalisation in testing fully-balanced OTA-C filters (2002) (1)
A CAD methodology for switched current analog IP cores (2003) (1)
DejaView: Help with memory, when you need it (2012) (1)
Embedded Systems Design in the UK: Special Issue (2002) (1)
Dataset supporting the article entitled "AdaMD: Adaptive Mapping and DVFS for Energy-efficient Heterogeneous Multi-cores" (2018) (1)
Unified Active Filter Structures (2004) (1)
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism (2009) (1)
Modified isolation rings for parallel test access in core based soc (2000) (1)
Hardware reliability of embedded systems: Are we there yet? (2013) (1)
Dataset for Low-Complexity Architecture for Cyber-Physical Systems Model Identification (2019) (0)
Accelerators and emulators: can they become the platform of choice for hardware verification? (2012) (0)
Symbolic Simulation based Transient Fault Injection Methodology (2008) (0)
dRail: A Novel Physical Layout Methodology for Power Gated Circuits (2012) (0)
ARGEN: A behavioral level compiler for hardware realisation of DSP systems (1998) (0)
An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems (2018) (0)
Dataset supporting the paper entitled "Run-time Performance and Power Optimization of a Parallel Disparity Estimation Algorithm on Many-Core Platforms" (2017) (0)
Testability Trade-Offs for BIST Data Paths (2004) (0)
Supplemental data for flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example (2016) (0)
A New BIST Methodology for Fully-Balanced OTA-C Filters (2002) (0)
Adaptation in heterogeneous multi-core SoCs (2018) (0)
Dataset for Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE (2019) (0)
CMOS Design of Group Delay Equaliser (2000) (0)
Minimizing Test Power in SRAM through Pre-charge Activity Reduction (2017) (0)
Low Power Testing of Digital ICs: Overview (2000) (0)
Computer-Based Circuit Simulation (2001) (0)
Dataset for "Workload-Aware Runtime Energy Management for HPC Systems" (2018) (0)
Dependent Sources (Linear And Nonlinear) (2019) (0)
Complementary dataset to "BRB: Mitigating Branch Predictor Side-Channels." (2019) (0)
Digital and Mixed Analogue/Digital Simulations (2019) (0)
Dynamic DNNs Meet Runtime Resource Management on Mobile and Embedded Platforms (2022) (0)
Data-set supporting the article entitled "Power Neutral Performance Scaling with Intrinsic MPPT for Energy Harvesting Computing Systems" (2018) (0)
Design of Wave Switched-Current Group Delay Equalizers (2002) (0)
VLSI architecture for fetal ECG extraction for personalized healthcare application within resource constrained environmentT (2010) (0)
Learning-based runtime management of energy-efficient and reliable many-core systems (2014) (0)
Transient and Fourier Analyses (2019) (0)
Low power test compatibility classes: exploiting regularity for simultaneous reduction in test application time and power dissipation (2001) (0)
New JETTA Editors, 2006 (2006) (0)
Data-set supporting the article entitled "Coarse-grained Online Monitoring of BTI Aging by Reusing Power Gating Infrastructure" (2016) (0)
Power-conscious design methodology for class-A switched-current wave filters (2004) (0)
Repair techniques for hybrid Nano/CMOS computational architecture (2009) (0)
7th international workshop on Performance Modeling, Evaluation, and Optimization of Ubiquitous Computing and Networked Systems (PMEO-UCNS'08) (2008) (0)
Research data for "A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder" (2017) (0)
Hardware Dependability in the Presence of Soft Errors (2008) (0)
Test Strategies for Multi-Voltage Designs (2009) (0)
Dynamic Voltage Scaling for Control Flow-Intensive Applications (2005) (0)
Conference Reports (2006) (0)
New paper now available with updated analysis and circuit design for photovoltaic energy harvesting (2012) (0)
Dataset supporting the article entitled "Online Concurrent Workload Classification for Multi-core Energy Management" (2017) (0)
On the practical implementation of high performance active audio filters using the FDNR concept (1990) (0)
Architecture-mapped concurrent-transform programmable 2D FIR filters for serial image processing (1999) (0)
Dataset supporting the article entitled "Inter-cluster Thread-to-core Mapping and DVFS on Heterogeneous Multi-cores" (2017) (0)
Predictive Algorithm Based Low Complexity 2D FastICA (2011) (0)
Dataset for Reliable Mapping and Partitioning of Performance-constrained OpenCL Applications on CPU-GPU MPSoCs (2017) (0)
FPGA based video signal decimators for sample rate reduction from 27/28.64 MHz to 13.5/14.32 MHz (1999) (0)
SoC manufacturing test a personal perspective (2005) (0)
Redistributing WSN Energy Consumption (2008) (0)
2015 JETTA Reviewers (2016) (0)
Supplemental data of A High-Throughput FPGA Architecture for Joint Source and Channel Decoding (2016) (0)
Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters (1999) (0)
Subcircuits and Efficient Use of PSpice (2019) (0)
A MASTERS COURSE IN SYSTEM-ON-CHIP Theory, Design and Practice (2006) (0)
Dataset supporting the article entitled "Machine Learning for Run-Time Energy Optimisation in Many-Core Systems" (2016) (0)
Rule Managed Reporting in Energy Controlled Wireless Sensor Networks (2006) (0)
Chapter 8 Test Strategies for Multi-Voltage Designs (2009) (0)
VHDL-AMS Implementation of a Numerical Ballistic CNT Model (2008) (0)
New differential coefficient coding algorithm for recursive FIR filters (1999) (0)
Software-defined PMC for runtime power management of a many-core neuromorphic platform (2017) (0)
Efficient design of switched-current lowpass elliptic wave filters using Bruton transformation (1998) (0)
Dataset for: Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs (2017) (0)
Adaptation in Heterogeneous Mobile SoCs (2018) (0)
Behavioral models of electronic filters (1995) (0)
New paper now available with updated analysis / modelling of supercapacitor leakage (2008) (0)
Low Power Test Compability Classes (2001) (0)
Current mode filters: design, simulation and implementation (1995) (0)
Automated and Robust Channel Identification Algorithm and Architecture to Solve Permutation Problem of ICA for Artifacts Removal from ECG in Remote Health Monitoring Environment (2010) (0)
SoC test challenges (2005) (0)
The Electronics Handbook: 1st edition (1996) (0)
Erratum for 'On-chip timing measurement architecture with femtosecond resolution' (2007) (0)
Dataset supporting the article entitled "Collaborative Adaptation for Energy-Efficient Heterogeneous Mobile SoCs" (2019) (0)
Analogue Behavioural Modelling “Block-Diagram” Simulation Approach (2019) (0)
Will it blend? Merging heterogeneous cores (2018) (0)
Tools and workloads for many-core computing (2019) (0)
A CAD Methodology for Switched Current IP Cores (2003) (0)
Similarity-Aware CNN for Efficient Video Recognition at the Edge (2022) (0)
A Novel Transient Fault Injection Methodology Based on STE Model Checking (2008) (0)
Supplemental data of Exponential Golomb and Rice Error Correction Codes for Generalized Near-Capacity Joint Source and Channel Coding (2016) (0)
Dataset for "Optimising Resource Management for Embedded Machine Learning" (2019) (0)
Guest Editor Introduction (2002) (0)
DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters (2013) (0)
Requirement of 5 G Background on channel codes Turbo codes and decoding LDPC codes and decoding Polar codes and decoding Comparison Information throughput Error correction capability Flexibility Recommendations and conclusion Appendix : Table of survey results (2019) (0)
Ac ce pt ed M an us cr ip t Energy Managed Reporting for Wireless Sensor Networks (2007) (0)
Dataset supporting the paper entitled "Hardware-Validated CPU Performance and Energy Modelling" (2018) (0)
Editorial - special section: low-power systems-on-chip (2002) (0)
The Art of SPICE Simulation: Analog and Digital: 1st (1995) (0)
New resource saving differential coefficient coding algorithm for recursive FIR filter design (1999) (0)
Verifying Cross-Layer Interactions Through Formal Model-Based Assertion Generation (2020) (0)
Efficient design of switched current lowpass elliptic filters using Bruton transformations (1998) (0)
Circuit Entry and Preliminary Analyses (2019) (0)
Run-Time Protection of Multi-Core Processors From Power-Noise Denial-of-Service Attacks (2020) (0)
Supplemental data of Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Trade-offs (2015) (0)
Dataset supporting the article entitled "Energy-Driven Computing: Rethinking the Design of Energy Harvesting Systems" (2016) (0)
BER plot - FPTD vs. Log-BCJR (2016) (0)
Many-Core Computing: Hardware and Software (2019) (0)
Power modelling of multicore systems (2019) (0)
Switched-Current Wave Group Delay (2004) (0)
Energy Harvesting for Bio-sensing by Using Carbon Nanotubes (2011) (0)
Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity (2023) (0)
Dataset supporting the paper entitled "Thermally-Aware Composite Run-Time CPU Power Models" (2016) (0)
Emerging strategies for resource-constrained testing of system chips : Compression considerations in test access mechanism design (2005) (0)
SystemC-based Fault Injection Technique with Improved Fault Representation (2008) (0)
FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz (1998) (0)
Unobtrusive Welfare Monitoring System (2008) (0)
Analogue Device Models and Libraries (2019) (0)
Sensitivity and Monte Carlo Analyses (2019) (0)

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What Schools Are Affiliated With Bashir Al-Hashimi?

Bashir Al-Hashimi is affiliated with the following schools:

University of Southampton