Behzad Razavi
#189,886
Most Influential Person Now
Behzad Razavi's AcademicInfluence.com Rankings
Behzad Razaviengineering Degrees
Engineering
#9153
World Rank
#10840
Historical Rank
Electrical Engineering
#2904
World Rank
#3058
Historical Rank

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Engineering
Behzad Razavi's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- Bachelors Electrical Engineering Sharif University of Technology
Why Is Behzad Razavi Influential?
(Suggest an Edit or Addition)Behzad Razavi's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- A 900 MHz/1.8 GHz CMOS receiver for dual band applications (1998) (342)
- A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology (2004) (244)
- CMOS technology characterization for analog and RF design (1998) (214)
- Challenges in the design of high-speed clock and data recovery circuits (2002) (205)
- Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers (2007) (201)
- Broadband ESD protection circuits in CMOS technology (2003) (135)
- RF transmitter architectures and circuits (1999) (118)
- A 2-GHz 1.6-mW phase-locked loop (1996) (90)
- A New Transceiver Architecture for the 60-GHz Band (2009) (70)
- A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications (1998) (58)
- A Millimeter-Wave Circuit Technique (2008) (55)
- Stacked inductors and 1-to-2 transformers in CMOS technology (2000) (22)
- Design of high-speed circuits for optical communication systems (2001) (20)
- A Receiver Architecture for Dual-Antenna Systems (2007) (16)
- An 8-bit 150-MHz CMOS A/D converter (1999) (8)
- The Design of An LDO Regulator [The Analog Mind] (2022) (4)
- The Design of a Millimeter-Wave VCO [The Analog Mind] (2022) (2)
- Relation Between INL and ACPR of RF DACs (2022) (1)
- A 56-GHz Fractional-N PLL With 110-fs Jitter (2023) (1)
- Phase Noise Integration Limits for Jitter Calculation (2022) (0)
- A 20-GHz PLL With 20.9-fs Random Jitter (2022) (0)
- Optimal Distribution of High-Speed Clocks on Transceiver Chips (2022) (0)
- A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance (2022) (0)
- A Study of Injection Locking in Oscillators and Frequency Dividers (2023) (0)
- Performance Bounds of ADC-based Receivers Due to Clock Jitter (2023) (0)
- The Design of a Millimeter-Wave Frequency Divider [The Analog Mind] (2022) (0)
- Circuit Bandwidth Requirements for NRZ and PAM4 Signals (2022) (0)
- The Design of a Transimpedance Amplifier [The Analog Mind] (2023) (0)
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