Bernd Becker
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German computer scientist and professor
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Bernd Beckercomputer-science Degrees
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Computer Science
Bernd Becker's Degrees
- PhD Computer Science Karlsruhe Institute of Technology
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(Suggest an Edit or Addition)Bernd Becker's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (1994) (228)
- A Definition and Classification of Timing Anomalies (2006) (205)
- Binary Decision Diagrams - Theory and Implementation (2013) (201)
- A Family of Logical Fault Models for Reversible Circuits (2005) (132)
- How robust is the n-cube? (1988) (121)
- A genetic algorithm for variable ordering of obdds (1996) (118)
- Multi-objective Optimisation Based on Relation Favour (2001) (110)
- Testing for missing-gate faults in reversible circuits (2004) (109)
- Multithreaded SAT Solving (2007) (103)
- Fast OFDD based minimization of fixed polarity Reed-Muller expressions (1994) (101)
- Checking equivalence for partial implementations (2001) (96)
- On the Relation between BDDs and FDDs (1995) (73)
- Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis (2009) (72)
- PaMiraXT: Parallel SAT Solving with Threads and Message Passing (2009) (71)
- Simulating Resistive-Bridging and Stuck-At Faults (2003) (66)
- An Analysis Framework for Transient-Error Tolerance (2007) (65)
- Sigref- A Symbolic Bisimulation Tool Box (2006) (63)
- Towards Verification of Artificial Neural Networks (2015) (62)
- X-masking during logic BIST and its impact on defect coverage (2004) (61)
- Accelerating Parametric Probabilistic Verification (2013) (61)
- Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions (1998) (57)
- The K*BMD: A Verification Data Structure (1997) (57)
- Binary decision diagrams (1998) (57)
- A Simulator of Small-Delay Faults Caused by Resistive-Open Defects (2008) (55)
- How many Decomposition Types do we need (1995) (55)
- Small-delay-fault ATPG with waveform accuracy (2012) (53)
- Compositional Dependability Evaluation for STATEMATE (2009) (50)
- Resistive Bridge fault model evolution from conventional to ultra deep submicron (2005) (50)
- Learning heuristics for OKFDD minimization by evolutionary algorithms (1996) (49)
- Finite-State Controllers of POMDPs using Parameter Synthesis (2017) (49)
- X-masking during logic BIST and its impact on defect coverage (2006) (48)
- Automatic Test Pattern Generation for Interconnect Open Defects (2008) (47)
- Minimal Critical Subsystems for Discrete-Time Markov Models (2012) (47)
- SC2: Satisfiability Checking Meets Symbolic Computation - (Project Paper) (2016) (46)
- Counterexample Generation for Discrete-Time Markov Models: An Introductory Survey (2014) (46)
- Synthesis for Testability: Binary Decision Diagrams (1992) (46)
- MORE: an alternative implementation of BDD packages by multi-operand synthesis (1996) (46)
- BDDs in a Branch and Cut Framework (2005) (46)
- Polynomial Formal Verification of Multipliers (1997) (44)
- Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking (2008) (44)
- Recent Improvements in the SMT Solver iSAT (2013) (44)
- Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions (1995) (43)
- A BDD-based algorithm for computation of exact fault detection probabilities (1993) (43)
- Modeling and Mitigating Transient Errors in Logic Circuits (2011) (43)
- A study of cognitive resilience in a JPEG compressor (2008) (42)
- Equivalence checking of partial designs using dependency quantified Boolean formulae (2013) (40)
- DTMC Model Checking by SCC Reduction (2010) (40)
- Optimizing Bounded Model Checking for Linear Hybrid Systems (2005) (40)
- The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults (2004) (40)
- A unified fault model and test generation procedure for interconnect opens and bridges (2005) (39)
- Dynamic minimization of OKFDDs (1995) (39)
- On the generation of multiplexer circuits for pass transistor logic (2000) (39)
- Incremental preprocessing methods for use in BMC (2011) (39)
- Functional simulation using binary decision diagrams (1997) (38)
- Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis (2006) (38)
- A Flexible Framework for the Automatic Generation of SBST Programs (2016) (37)
- Hierarchical Counterexamples for Discrete-Time Markov Chains (2011) (36)
- Selective Hardening in Early Design Steps (2008) (36)
- High-Level Counterexamples for Probabilistic Automata (2013) (36)
- How Robust Is the n-Cube? (Extended Abstract) (1986) (36)
- HQSpre - An Effective Preprocessor for QBF and DQBF (2017) (36)
- Compositional Performability Evaluation for STATEMATE (2006) (36)
- Solving DQBF through quantifier elimination (2015) (35)
- Power Droop Testing (2007) (34)
- PaMira - A Parallel SAT Solver with Knowledge Sharing (2005) (34)
- On the Optimal Layout of Planar Graphs with Fixed Boundary (1987) (33)
- The COMICS Tool - Computing Minimal Counterexamples for DTMCs (2012) (33)
- Orthogonal Hypergraph Drawing for Improved Visibility (2006) (32)
- Efficient Testing of Optimal Time Adders (1988) (31)
- Efficient SAT-Based Search for Longest Sensitisable Paths (2011) (31)
- LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals (2007) (31)
- Transient fault characterization in dynamic noisy environments (2005) (30)
- Automatic test pattern generation for resistive bridging faults (2004) (30)
- Symblicit Calculation of Long-Run Averages for Concurrent Probabilistic Systems (2010) (30)
- Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model (2008) (30)
- Hierarchical Design Based on a Calculus of Nets (1987) (30)
- On variable ordering and decomposition type choice in OKFDDs (1995) (29)
- On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing (2005) (28)
- Laissez-Faire Caching for Parallel #SAT Solving (2015) (28)
- Dynamic Compaction in SAT-Based ATPG (2009) (27)
- Minimal counterexamples for linear-time probabilistic verification (2014) (27)
- On Combining 01X-Logic and QBF (2007) (27)
- A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions (1995) (26)
- On the representational power of bit-level and word-level decision diagrams (1997) (26)
- Testability of 2-Level AND/EXOR Circuits (1997) (25)
- Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits (1999) (25)
- Functional test of small-delay faults using SAT and Craig interpolation (2012) (24)
- Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs (2006) (24)
- Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes (1999) (24)
- A hierarchical approach to fault collapsing (1994) (23)
- OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithms (1994) (23)
- On the (non-)resetability of synchronous sequential circuits (1996) (23)
- Low-Cost Hardening of Image Processing Applications Against Soft Errors (2006) (23)
- Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors (2008) (23)
- Craig Interpolation in the Presence of Non-linear Constraints (2011) (23)
- An effective approach to automatic functional processor test generation for small-delay faults (2014) (23)
- OKFDDs versus OBDDs and OFDDs (1995) (23)
- Exact computation of maximally dominating faults and its application to n-detection tests (2002) (22)
- Power Droop Testing (2006) (22)
- Modeling Feedback Bridging Faults with Non-Zero Resistance (2003) (22)
- QmiraXT - A Multithreaded QBF Solver (2009) (22)
- Verification of partial designs using incremental QBF solving (2012) (22)
- PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization (2016) (22)
- On the optimality of K longest path generation algorithm under memory constraints (2012) (21)
- Provably optimal test cube generation using quantified boolean formula solving (2013) (21)
- Formal verification of secure reconfigurable scan network infrastructure (2016) (21)
- Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up (1992) (21)
- Learning heuristics by genetic algorithms (1995) (21)
- ATPG-based grading of strong fault-secureness (2009) (21)
- On the automatic generation of SBST test programs for in-field test (2015) (21)
- Accurate ICP-based floating-point reasoning (2016) (21)
- A Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition (2013) (21)
- Efficient graph based representation of multi-valued functions with an application to genetic algorithms (1994) (21)
- Overview of decision diagrams (1997) (20)
- SAT-based analysis of sensitisable paths (2011) (20)
- Specification and verification of security in reconfigurable scan networks (2017) (20)
- Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects (2015) (20)
- Counterexample-Guided Strategy Improvement for POMDPs Using Recurrent Neural Networks (2019) (20)
- Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths (2013) (20)
- Motion planning under partial observability using game-based abstraction (2017) (19)
- Speedup Techniques Utilized in Modern SAT Solvers (2005) (19)
- Symbolic counterexample generation for large discrete-time Markov chains (2014) (19)
- Computation of minimal counterexamples by using black box techniques and symbolic methods (2007) (19)
- Parallel SAT Solving in Bounded Model Checking (2006) (19)
- Accurate QBF-based test pattern generation in presence of unknown values (2013) (19)
- Crossing Reduction by Windows Optimization (2002) (19)
- On the Construction of Optimal Time Adders (Extended Abstract) (1988) (19)
- PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing (2009) (18)
- SAT-ATPG using preferences for improved detection of complex defect mechanisms (2012) (18)
- OKFDDs — Algorithms, Applications and Extensions (1996) (18)
- Testing with decision diagrams (1998) (18)
- A hybrid fault simulator for synchronous sequential circuits (1994) (18)
- Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs (2010) (18)
- Early-life-failure detection using SAT-based ATPG (2013) (17)
- AutoFault: Towards Automatic Construction of Algebraic Fault Attacks (2017) (17)
- k-Layer Straightline Crossing Minimization by Speeding Up Sifting (2000) (17)
- Variation-Aware Fault Grading (2012) (17)
- Testability properties of local circuit transformations with respect to the robust path-delay-fault model (1994) (17)
- Synthesis of pseudo Kronecker lattice diagrams (1999) (17)
- Multi-conditional SAT-ATPG for power-droop testing (2012) (17)
- Variation-aware fault modeling (2010) (17)
- Massive statistical process variations: A grand challenge for testing nanoelectronic circuits (2010) (17)
- SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges (2007) (17)
- Small Scale AES Toolbox: Algebraic and Propositional Formulas, Circuit-Implementations and Fault Equations (2016) (17)
- Word-level decision diagrams, WLCDs and division (1998) (17)
- Semi-Automatic Generation and Labeling of Training Data for Non-intrusive Load Monitoring (2019) (16)
- Variation-aware deterministic ATPG (2014) (16)
- Verification of designs containing black boxes (2000) (16)
- Counterexample Generation for Markov Chains Using SMT-Based Bounded Model Checking (2011) (16)
- Towards the formal verification of security properties of a Network-on-Chip router (2018) (16)
- Conflict-Based Selection of Branching Rules (2003) (15)
- Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs (2013) (15)
- Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs (2016) (15)
- Finite-state Controllers of POMDPs via Parameter Synthesis* (2019) (15)
- Dynamic Polynomial Watchdog Encoding for Solving Weighted MaxSAT (2018) (15)
- Resistive Bridging Fault Simulation of Industrial Circuits (2008) (15)
- Efficient SMT-based ATPG for interconnect open defects (2014) (14)
- Sensitized path PUF: A lightweight embedded physical unclonable function (2017) (14)
- On the generation of area-time optimal testable adders (1995) (14)
- Look-up table FPGA synthesis from minimized multi-valued pseudo Kronecker expressions (1998) (14)
- #SAT-based vulnerability analysis of security components — A case study (2012) (14)
- A graphical system for hierarchical specifications and checkups of VLSI circuits (1990) (14)
- Early Conflict Detection Based BCP for SAT Solving (2004) (14)
- On the Expressive Power of OKFDDs (1997) (13)
- Exact stuck-at fault classification in presence of unknowns (2012) (13)
- Dependency Schemes for DQBF (2016) (13)
- Simulating resistive bridging and stuck-at faults (2006) (13)
- On the quality of test vectors for post-silicon characterization (2012) (13)
- Skolem Functions for DQBF (2016) (13)
- Towards Variation-Aware Test Methods (2011) (13)
- Exact channel routing using symbolic representation (1999) (13)
- Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization (2014) (13)
- A uniform test approach for RCC-adders (1991) (12)
- Identification of Critical Errors in Imaging Applications (2007) (12)
- Computations over finite monoids and their test complexity (1989) (12)
- Exact Logic and Fault Simulation in Presence of Unknowns (2014) (12)
- Genetic algorithm for minimisation of fixed polarity Reed-Muller expressions (2000) (12)
- Identification of high power consuming areas with gate type and logic level information (2015) (12)
- Optimal-time multipliers and C-testability (1990) (12)
- The multiple variable order problem for binary decision diagrams: theory and practical application (2001) (11)
- On SAT-based Bounded Invariant Checking of Blackbox Designs (2005) (11)
- Speedup Techniques Utilized in Modern SAT Solvers An Analysis in the MIRA Environment (2005) (11)
- Symbolic Counterexample Generation for Discrete-Time Markov Chains (2012) (11)
- Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation) (2012) (11)
- Checking equivalence for circuits containing incompletely specified boxes (2002) (11)
- Analysis of Large Safety-Critical Systems : A quantitative Approach ? (2006) (11)
- SFB/TR 14 AVACS – Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS – Automatische Verifikation und Analyse komplexer Systeme) (2007) (11)
- Proving QBF-hardness in Bounded Model Checking for Incomplete Designs (2013) (11)
- Efficient bridging fault simulation of sequential circuits based on multi-valued logics (2002) (11)
- ALLQBF Solving by Computational Learning (2012) (11)
- Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems (2004) (11)
- Probabilistic Model Checking and Reliability of Results (2008) (11)
- Minimization of large state spaces using symbolic branching bisimulation (2006) (11)
- Layouts with Wires of Balanced Length (1985) (10)
- On optimizing BIST-architecture by using OBDD-based approaches and genetic algorithms (1997) (10)
- From DQBF to QBF by Dependency Elimination (2017) (10)
- On Secure Data Flow in Reconfigurable Scan Networks (2019) (10)
- A genetic algorithm for RKRO minimization (1997) (10)
- Evolutionary Algorithms in Computer-Aided Design of Integrated Circuits (1999) (10)
- Correctness Issues of Symbolic Bisimulation Computation for Markov Chains (2010) (10)
- Detecting and Resolving Security Violations in Reconfigurable Scan Networks (2018) (10)
- Bounded Model Checking of Incomplete Networks of Timed Automata (2010) (10)
- Evolutionary optimization of Markov sources for pseudo random scan BIST (2003) (10)
- On local transformations and path delay fault testability (1995) (10)
- FIRED: A Fully-labeled hIgh-fRequency Electricity Disaggregation Dataset (2020) (10)
- Using MaxBMC for Pareto-optimal circuit initialization (2014) (10)
- Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing (2011) (10)
- Decision diagrams in synthesis-algorithms, applications and extensions (1997) (10)
- AND/EXOR-based synthesis of testable KFDD-circuits with small depth (1996) (10)
- Cost vs. time in stochastic games and Markov automata (2015) (10)
- Structure based methods for parallel pattern fault simulation in combinational circuits (1991) (9)
- Automatic Test Pattern Generation for Resistive Bridging Faults (2006) (9)
- Estimation of component criticality in early design steps (2011) (9)
- Diagnosis of Realistic Defects Based on the X-Fault Model (2008) (9)
- Implication Graph Compression inside the SMT Solver iSAT3 (2014) (9)
- Improved minimization methods of pseudo Kronecker expressions for multiple output functions (1998) (9)
- MeGARA: Menu-based Game Abstraction and Abstraction Refinement of Markov Automata (2014) (9)
- Parallel QBF Solving with Advanced Knowledge Sharing (2011) (9)
- Accurate Multi-cycle ATPG in Presence of X-Values (2013) (9)
- The (D)QBF Preprocessor HQSpre - Underlying Theory and Its Implementation (2019) (9)
- Improving diagnosis resolution of a fault detection test set (2015) (8)
- SMILE: Smartphones in der Lehre - ein Rück- und Überblick (2013) (8)
- Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support (2019) (8)
- Bounded Fairness for Probabilistic Distributed Algorithms (2011) (8)
- Dependability Engineering of Silent Self-stabilizing Systems (2009) (8)
- Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays (2013) (8)
- Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving (2016) (8)
- Online prevention of security violations in reconfigurable scan networks (2018) (8)
- Securing wireless networks in a university environment (2005) (8)
- Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs (2016) (8)
- Proof certificates and non-linear arithmetic constraints (2011) (8)
- SAT-Based Test Pattern Generation with Improved Dynamic Compaction (2014) (8)
- Hybrid Fault Simulation for Synchronous Sequential Circuits (1999) (8)
- Testability of circuits derived from functional decision diagrams (1994) (7)
- Das TV-Duell und die Landtagswahl in Schleswig-Holstein: Das Debat-O-Meter als neues Instrument der politischen Kommunikationsforschung (2017) (7)
- OBDD-based optimization of input probabilities for weighted random pattern generation (1995) (7)
- Cross Reduction for Orthogonal Circuit Visualization (2003) (7)
- Minimal Critical Subsystems as Counterexamples for ω-Regular DTMC Properties (2011) (7)
- Picoso - A Parallel Interval Constraint Solver (2009) (7)
- Strategy Synthesis for POMDPs in Robot Planning via Game-Based Abstractions (2020) (7)
- Random pattern fault simulation in multi-valued circuits (1995) (7)
- Using interval constraint propagation for pseudo-Boolean constraint solving (2014) (7)
- QBF with Soft Variables (2014) (7)
- Distributed Parallel #SAT Solving (2016) (7)
- On Integrating Lightweight Encryption in Reconfigurable Scan Networks (2019) (7)
- A time optimal robust path-delay-fault self-testable adder (1992) (6)
- Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties (2012) (6)
- Bounded Model Checking with Parametric Data Structures (2007) (6)
- Abstraction-Based Computation of Reward Measures for Markov Automata (2015) (6)
- Verification of partial designs using incremental QBF (2015) (6)
- Exact switchbox routing with search space reduction (2000) (6)
- On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division (2002) (6)
- Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics (2013) (6)
- An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors (2011) (6)
- Exploiting Different Strategies for the Parallelization of an SMT Solver (2010) (6)
- Equivalence Checking for Partial Implementations Revisited (2013) (6)
- Exact Routing with Search Space Reduction (2003) (6)
- Relation between OFDDs and FPRMs (1996) (6)
- Application of linearly transformed BDDs in sequential verification (2001) (6)
- Counterexamples for Expected Rewards (2015) (6)
- Optimization techniques for BDD-based bisimulation computation (2007) (6)
- Minimal Counterexamples for Refuting ω-Regular Properties of Markov Decision Processes – Extended Version – (2012) (6)
- Das Debat-O-Meter: ein neues Instrument zur Analyse von TV-Duellen (2016) (6)
- Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases (2015) (6)
- Search Space Reduction for Low-Power Test Generation (2013) (6)
- Transient Reward Approximation for Continuous-Time Markov Chains (2012) (6)
- Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation (2012) (6)
- Improving test pattern generation in presence of unknown values beyond restricted symbolic logic (2015) (6)
- Effective generation and evaluation of diagnostic SBST programs (2016) (6)
- Test pattern generation in presence of unknown values based on restricted symbolic logic (2014) (6)
- A genetic algorithm for the construction of small and highly testable OKFDD-circuits (1996) (6)
- Grouping heuristics for word-level decision diagrams (1999) (6)
- Satisfiability checking and symbolic computation (2016) (6)
- Using different LUT paths to increase area efficiency of RO-PUFs on Altera FPGAs (2018) (6)
- SAT-Based Combinational and Sequential Dependency Computation (2016) (5)
- Evolutionary optimization in code-based test compression (2005) (5)
- AVACS -- Automatic Verification and Analysis of Complex Systems (2007) (5)
- Orthogonal circuit visualization improved by merging the placement and routing phases (2005) (5)
- Security Compliance Analysis of Reconfigurable Scan Networks (2019) (5)
- Orthogonal hypergraph routing for improved visibility (2004) (5)
- On the impact of structural circuit partitioning on SAT-based combinational circuit verification (2004) (5)
- Regular Structures and Testing: RCC-Adders (1988) (5)
- Distance driven finite state machine traversal (2000) (5)
- Incremental Encoding and Solving of Cardinality Constraints (2014) (5)
- Symbolic simulation using decision diagrams (1997) (5)
- Towards the Fusion of Intrusive and Non-intrusive Load Monitoring: A Hybrid Approach (2018) (5)
- Specialized Hardware for Implementation of Evolutionary Algorithms (2000) (5)
- An IR-Drop Simulation Principle Oriented to Delay Testing (2012) (5)
- Fault simulation in sequential multi-valued logic networks (1997) (5)
- A performance driven generator for efficient testable conditional-sum-adders (1992) (5)
- Word-level Decision Diagrams (1998) (5)
- Advancing Software Model Checking Beyond Linear Arithmetic Theories (2016) (5)
- Formal Vulnerability Analysis of Security Components (2015) (5)
- Exact minimisation of Kronecker expressions for symmetric functions (1996) (5)
- Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns (2016) (5)
- Enhanced Integration of QBF Solving Techniques (2012) (4)
- A Distributed SAT Solver for Microcontroller (2004) (4)
- ICP and IC3 (2021) (4)
- Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG (2017) (4)
- Satisfiability Problems for OFDDs (1996) (4)
- Analysis of Ring Oscillator PUFs on 60 nm FPGAs (2013) (4)
- Manipulation Algorithms for K*BMDs (1997) (4)
- Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas (2011) (4)
- Design reuse by modularity: a scalable dynamical (re)configurable multiprocessor system (2000) (4)
- Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface (2005) (4)
- Integrating Algebraic and SAT Solvers (2017) (4)
- Landfill Mining – ein Beitrag der Abfallwirtschaft zur Ressourcensicherung (2013) (4)
- Comparison of knowledge sharing strategies in a parallel QBF solver (2009) (4)
- Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects (2014) (4)
- Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy (1995) (4)
- Implementation of Delay-Based PUFs on Altera FPGAs (2017) (4)
- On Metrics to Quantify the Inter-Device Uniqueness of PUFs (2016) (4)
- Stochastic Bounded Model Checking: Bounded Rewards and Compositionality (2013) (4)
- Run-time Soft Error Injection and Testing of a Microprocessor using FPGAs (2011) (4)
- On Preprocessing for Weighted MaxSAT (2021) (4)
- An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects (2009) (4)
- The COMICS Tool - Computing Minimal Counterexamples for Discrete-time Markov Chains (2012) (4)
- OKFDD minimization by genetic algorithms with application to circuit design (1999) (4)
- EXOR transform of inputs to design efficient two-level AND/EXOR adders (2000) (4)
- Scalable Delay Fault BIST for Use with Low-Cost ATE (2004) (4)
- Identification of critical variables using an FPGA-based fault injection framework (2013) (4)
- Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation (2007) (4)
- Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor (2021) (3)
- Ed&tc '97 on Cd-rom Fast and Ecient Construction of Bdds by Reordering Based Synthesis (1997) (3)
- Characterization of possibly detected faults by accurately computing their detection probability (2018) (3)
- An easily testable optimal-time VLSI-multiplier (1987) (3)
- Integration of an LP Solver into Interval Constraint Propagation (2011) (3)
- Period of Grace : A New Paradigm for Efficient Soft Error Hardening (2006) (3)
- Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG (2017) (3)
- Minimization of OKFDDs by Genetic Algorithms (1996) (3)
- A parameterizable fault simulator for bridging faults (2000) (3)
- Verifying Incomplete Networks of Timed Automata (2011) (3)
- Early Conflict Detection Based SAT Solving (2004) (3)
- Test generation for (sequential) multi-valued logic networks based on genetic algorithm (1998) (3)
- Minimization of ordered pseudo Kronecker decision diagrams (2000) (3)
- Automatic Construction of Fault Attacks on Cryptographic Hardware Implementations (2019) (3)
- Cmos stuck-open self-test for an optimal-time VLSI-multiplier (1987) (3)
- Testability of circuits derived from lattice diagrams (2000) (3)
- Conflict-based Selection of Branching Rules in SAT-Algorithms (2003) (3)
- Strengthening Deterministic Policies for POMDPs (2020) (3)
- Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics (2001) (3)
- 1 A Model for Transient Faults in Logic Circuits (2006) (3)
- A genetic algorithm for decomposition type choice in OKFDDs (1995) (3)
- Multiple Scan Chain Design for Two-Pattern Testing (2001) (3)
- Polynomial Formal Veri cation of Multipliers (1996) (3)
- No Free Lunch in Soft Error Protection (2008) (3)
- Annoticity: A Smart Annotation Tool and Data Browser for Electricity Datasets (2020) (3)
- Analysis of Incomplete Circuits Using Dependency Quantified Boolean Formulas (2018) (3)
- Lemma exchange in a microcontroller based parallel SAT solver (2005) (3)
- Reducing temperature variability by routing heat pipes (2009) (3)
- On Optimal Power-Aware Path Sensitization (2016) (3)
- Minimization of 2-level AND / XOR Expressionsusing Ordered Kronecker Functional Decision Diagrams (2007) (3)
- Towards mixed structural-functional models for algebraic fault attacks on ciphers (2017) (3)
- On the implementation of an efficient performance driven generator for conditional-sum-adders (1993) (3)
- Placement and routing optimization for circuits derived from BDDs (2004) (3)
- Solving the Multiple Variable Order Problem for Binary Decision Diagrams by Use of Dynamic Reordering Techniques (1999) (3)
- Sequence Length , Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST (2004) (3)
- Integration of orthogonal QBF solving techniques (2011) (3)
- State Traversal guided by Hamming Distance Profiles (2000) (2)
- Local Transformations and Robust Dependent Path Delay (1996) (2)
- A Hardware Lab Anywhere At Any Time∗ (2003) (2)
- A Dynamic QBF Preprocessing Approach for the Verification of Incomplete Designs (2012) (2)
- ICP and IC3 with Stronger Generalization (2021) (2)
- Synthesis of circuits derived from decision diagrams-combining small delay and testability (1999) (2)
- Memory-aware Bounded Model Checking for Linear Hybrid Systems (2006) (2)
- MiraXT – A Multithreaded SAT Solver (2007) (2)
- On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits (2018) (2)
- $$\mathsf {SC}^\mathsf{2} $$: Satisfiability Checking Meets Symbolic Computation (2016) (2)
- Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG (2017) (2)
- Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting (2002) (2)
- On the testability of iterative logic arrays (1995) (2)
- Circuit Partitioning for SAT-based Combinational Circuit Verication A Case Study (2004) (2)
- Correct-by-construction policies for POMDPs (2019) (2)
- On Reducing Circuit Malfunctions Caused by Soft Errors (2008) (2)
- Fault diagnosis aware ATE assisted test response compaction (2011) (2)
- Efficient Pattern-Based Verification of Connections to Intellectual Property Cores (2003) (2)
- GREEDY IIP: partitioning large graphs by greedy iterative improvement (2001) (2)
- A Framework to Generate and Label Datasets for Non-Intrusive Load Monitoring (2020) (2)
- FIRED (2020) (2)
- Exploiting don't cares to minimize *BMDs (2001) (2)
- Collaborative Exercise Management (2006) (2)
- Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model (2017) (2)
- Stop & go BIST (2002) (2)
- TSV and DFT cost aware circuit partitioning for 3D-SOCs (2012) (2)
- CONFIGURING MISR-BASED TWO-PATTERN BIST USING BOOLEAN SATISFIABILITY (2)
- Efficient Testing of Optimal Time Adders (Extended Abstract) (1986) (2)
- Efficient pattern-based verification of connections to IP cores (2001) (2)
- On the crossing-free, rectangular embedding of weighted graphs in the plane (1983) (2)
- High-level Counterexamples for Probabilistic Automata – Extended Version ? – (2013) (2)
- Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams (1997) (1)
- Digital Tarnkappe: Stealth Technology for the Internet of Things (2012) (1)
- Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae (2009) (1)
- SMT-based Counterexample Generation for Markov Chains (2011) (1)
- Satisfiability Checking meets Symbolic Computation (Project Paper) (2016) (1)
- Application of Lifting in Partial Design Analysis (2007) (1)
- Parallel SAT Solving with Microcontrollers (2004) (1)
- SAT-Based Analysis of Sensitizable Paths (2013) (1)
- ACCELERATING BOOLEAN SAT ENGINES USING HYPER-THREADING TECHNOLOGY (2007) (1)
- Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects (2009) (1)
- Local transformations and robust dependent path delay faults (1996) (1)
- Minimization of Decision Diagrams: Classical Methods (1998) (1)
- PICHAFF² — A Hierarchical Parallel SAT Solver (2004) (1)
- Notations and Definitions (1998) (1)
- Efficient SAT-based generation of hazard-activated TSOF tests (2017) (1)
- New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core (2021) (1)
- Decision diagram based minimization of pseudo Kronecker expressions (2000) (1)
- Symbolic Simulation of Algorithms Specified in HDL (2002) (1)
- The Scale4Edge RISC-V Ecosystem (2022) (1)
- Active Stereo Vision with High Resolution on an FPGA (2019) (1)
- Modular structure for data processing (2010) (1)
- A Model for Resistive Open Recursivity in CMOS Random Logic (2008) (1)
- Benchmarking Academic DFT Tools on the OpenSparc Microprocessor (2008) (1)
- (Quasi-) linear path delay fault tests for adders (1997) (1)
- SC 2 : Satisfiability Checking meets (2016) (1)
- Integrating Incremental Flow Pipes into a Symbolic Model Checker for Hybrid Systems (2011) (1)
- Strategy Synthesis in POMDPs via Game-Based Abstractions (2017) (1)
- 10271 Abstracts Collection - Verification over discrete-continuous boundaries (2010) (1)
- Institute of Electrical Engineering and Information Technology , University of Paderborn (1)
- Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures (2009) (1)
- On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata (2007) (1)
- Sequential n-detection criteria: keep it simple! (2002) (1)
- Knowledge Sharing in a Microcontroller based Parallel SAT Solver (2005) (1)
- Accurate Computation of Longest Sensitizable Paths using Answer Set Programming (2012) (1)
- Benchmarking SMT Solvers on Automotive Code (2022) (1)
- Everything You Always Wanted to Know About Generalization of Proof Obligations in PDR (2021) (1)
- SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs (2010) (1)
- Cost vs. time in stochastic games and Markov automata (2017) (1)
- Best paper (2017) (1)
- Reachability analysis for incomplete networks of Markov decision processes (2011) (1)
- Towards SAT-Based SBST Generation for RISC-V Cores (2021) (1)
- Published at Workshop on Post Binary Ultra-Large Scale Integration (ULSI‘96), Santiago de Compostela A Note on Symbolic Simulation using Decision Diagrams (2007) (1)
- Don't Care Minimization of BMDs: Complexity and Algorithms (2001) (1)
- Efficient SAT-Based Circuit Initialization for Larger Designs (2014) (1)
- Reducing ATE Cost in System-on-Chip Test (2003) (1)
- SC2: Satisfiability Checking Meets Symbolic Computation (Project Paper) (2016) (1)
- The Demand for Reliability in Probabilistic Verification (2008) (1)
- # SAT for Vulnerability Analysis of Security Components (2013) (1)
- Digitale Tarnkappe: Anonymisierung in Videoaufnahmen (2016) (1)
- A Versatile High Frequency Electricity Monitoring Framework for Our Future Connected Home (2019) (1)
- Minimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks (2020) (1)
- Accurate Computation of Sensitizable Paths Using Answer Set Programming (2013) (1)
- SAT, SMT, and QBF Solving in a Multi-Core Environment (2009) (1)
- Modeling Unknown Values in Test and Verification (2015) (1)
- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems (2014) (0)
- Preprint Variation-Aware Deterministic (2014) (0)
- Computer Aided Design and Test - BDDs versus SAT (Dagstuhl Seminar 01051) (2021) (0)
- Special Panel Session (2010) (0)
- Transient Reward Approximation for Grids, Crowds, and Viruses (2012) (0)
- S C ] 2 3 Ju l 2 01 6 Satisfiability Checking and Symbolic Computation (2016) (0)
- A method for the systematic treatment of errors (2010) (0)
- Author Index (2005) (0)
- Alle gegen Alle? Die Mehrpersonendebatte der kleinen Parteien in der Analyse (2019) (0)
- Veri cation over discrete-continuous boundaries generate automatically Dagstuhl Seminar (2010) (0)
- Using LUT-specific delays to mitigate biases in delay-based PUFs and increase area efficiency on FPGAs (2016) (0)
- S C ] 2 7 Ju l 2 01 6 SC 2 : Satisfiability Checking meets Symbolic Computation ( Project Paper ) (2016) (0)
- Known unknowns — Knowledge in the presence of unknowns (2016) (0)
- PackSens: A Condition and Transport Monitoring System Based on an Embedded Sensor Platform (2016) (0)
- Verfahren zum betreiben eines common-rail-systems eines kraftfahrzeugs mit einem redundanten raildrucksensor (2014) (0)
- 3 Test Preparation and Generation ( T 2 ) (2018) (0)
- The Case for 2-POF (2003) (0)
- Algorithmen für Decision Diagrams (1998) (0)
- On Metrics to Quantify the Inter-Device Uniqueness of Physically Unclonable Functions (2016) (0)
- Exemplary Achievements SC 2 challenges : when Satisfiability Checking and Symbolic Computation join forces (2017) (0)
- Propositional approximations for bounded model checking of partial circuit designs (2008) (0)
- Controlling Small-Delay Test Power Consumption using Satisfiability Modulo Theory Solving (2013) (0)
- Design based on a Calculus of Nets (1987) (0)
- Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs (2010) (0)
- S E ] 1 7 D ec 2 01 3 Accelerating Parametric Probabilistic Verification ⋆ (2013) (0)
- Minimization Using Symmetries (1998) (0)
- Preprint from Proceedings of ICCAD ’ 98 , San Jose , California , November 8-12 , 1998 Word-Level Decision Diagrams , WLCDs and Division (2014) (0)
- Abstraction-based Model Checking of POMDPs in Motion Planning ∗ (2017) (0)
- Some Remarks on the Test Complexity of Iterative Logic Arrays (1992) (0)
- Preprint from Proceedings of International Symposium on Circuits and Systems , Sydney , Australia , May 2001 EXPLOITING DON ’ T CARES TO MINIMIZE * BMDS (2014) (0)
- A Case Study: Two-Level AND/EXOR Minimization (1998) (0)
- Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT (2023) (0)
- ASimulatorofSmall-DelayFaultsCausedbyResistive-OpenDefects (2008) (0)
- Hohldorn aus Kunststoff (1990) (0)
- Efficient generation of parametric test conditions for AMS chips with an interval constraint solver (2018) (0)
- SC-square: when Satisfiability Checking and Symbolic Computation join forces (2017) (0)
- Supervised Dynamic Recording in Model Checking (2001) (0)
- Validität und Reliabilität virtualisierter RTR-Messungen (2021) (0)
- A Multi-Layer Detailed Routing Approach based onEvolutionary (1997) (0)
- Sympathy-MV: Fast exact minimization of fixed polarity multi-valued linear expressions (1997) (0)
- Applying Tailored Formal Methods to X-ATPG (2016) (0)
- Bit-level Decision Diagrams (1998) (0)
- Testing Nanoelectronic Circuits Under Massive Statistical Process Variations (2010) (0)
- Effective Fault Tolerance for Robust Robotics under Radiation Exposure (2013) (0)
- Computer Aided Design and Test Decision Diagrams - Concepts and Applications (Dagstuhl Seminar 9705) (2021) (0)
- Solving by Computational Learning ⋆ (2012) (0)
- Learning Heuristics by Evolutionary Algorithmswith Variable Size RepresentationNicole (1997) (0)
- Solving DQBF Through Quantifier Elimination by Karina Gitina (2015) (0)
- Computer system and method for operating a computer system (2012) (0)
- The Smart MiniFab: An Industrial IoT Demonstrator Anywhere at Any Time (2017) (0)
- Using Formal Methods to Support the Development of STLs for GPUs (2022) (0)
- Decision Diagram Based Minimization of Pseudo KroneckerExpressionsPer Lindgren (2007) (0)
- On the Generation of Area-Time (1995) (0)
- Evaluation of Knowledge Sharing Strategies in a Parallel QBF Solver (2009) (0)
- Verification of Incomplete Designs (2018) (0)
- Hygienische Aufbereitung von Ultraschallsonden mit einem Desinfektionstuchsystem in Anlehnung an den 4-Felder-Test und DIN EN ISO 17664 (2018) (0)
- Das »Debat-O-Meter« als neues Tool in der E-Partizipation (2020) (0)
- Equivalence Checking in the Presence of Incompletely Specified Boxes (2002) (0)
- Fault Models and Test Algorithms for Nanoscale Technologies (2010) (0)
- Optimal-time multipliers and C-testability 1 ) (1991) (0)
- Published at Reed-muller 97, Oxford Reordering Based Synthesis (1997) (0)
- Automatic Test Pattern Generation for Power Droop Testing (2006) (0)
- Genetic Algorithm for the Construction of Small and Highly (2007) (0)
- High-Coverage AMS Test Space Optimization by Efficient Parametric Test Condition Generation (2018) (0)
- Intelligent Computer Mathematics (2016) (0)
- iHouse: A Voice-Controlled, Centralized, Retrospective Smart Home (2016) (0)
- A process for producing a timing signal (1999) (0)
- Ist die Sarkoidose eine durch Vitamin D getriggerte Krebsabwehr? (2019) (0)
- 7 OKFDDS-ALGORITHMS , APPLICATIONS AND EXTENSIONS (0)
- 09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers (2009) (0)
- Fault Modeling for Simulation and ATPG (2010) (0)
- Analysis and utilisation of deviations in RO-PUFs under altered FPGA designs (2015) (0)
- Interactive circuit diagram visualization (2008) (0)
- On the Testability of Iterative Logic Arrays on the Testability of Iterative Logic Arrays (1994) (0)
- VLSI in Computers & Processors International Conference on Computer Design (2001) (0)
- Introducing MILM: A Hybrid Minimal-Intrusive Load Monitoring Approach: Poster (2021) (0)
- Abstraktions-basierte Verifikation von POMDPs im Motion-Planning-Kontext (2018) (0)
- Performance aware partitioning for 3D-SOCs (2012) (0)
- BDDs in a Branch & Cut Framework ? (2005) (0)
- 2009 27th IEEE VLSI Test Symposium (2009) (0)
- Alternative Minimization Concepts (1998) (0)
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