Bruce Cockburn
#37,970
Most Influential Person Now
Canadian folk/rock guitarist and singer-songwriter
Bruce Cockburn's AcademicInfluence.com Rankings
Bruce Cockburncommunications Degrees
Communications
#3063
World Rank
#4341
Historical Rank
Linguistics
#1659
World Rank
#2088
Historical Rank
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Communications
Why Is Bruce Cockburn Influential?
(Suggest an Edit or Addition)According to Wikipedia, Bruce Douglas Cockburn is a Canadian singer-songwriter and guitarist. His song styles range from folk to folk- and jazz-influenced rock to soundscapes accompanying spoken stories. His lyrics reflect interests in spirituality, human rights, environmental issues, and relationships, and describe his experiences in Central America and Africa.
Bruce Cockburn's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Efficient architectures for 1-D and 2-D lifting-based wavelet transforms (2004) (223)
- Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors (2018) (92)
- A Compact and Accurate Gaussian Variate Generator (2008) (71)
- Compact Rayleigh and Rician fading simulator based on random walk processes (2009) (54)
- Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers (2020) (53)
- Tutorial on semiconductor memory testing (1994) (52)
- An investigation into crosstalk noise in DRAM structures (2002) (43)
- A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy (2019) (37)
- A Single FPGA Filter-Based Multipath Fading Emulator (2009) (36)
- Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs (1995) (36)
- A true random number generator based on parallel STT-MTJs (2017) (35)
- Modeling and Hardware Implementation Aspects of Fading Channel Simulators (2008) (35)
- A scalable LDPC decoder ASIC architecture with bit-serial message exchange (2008) (34)
- An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing (2021) (33)
- Deterministic tests for detecting singleV-coupling faults in RAMs (1994) (28)
- Design, evaluation and fault-tolerance analysis of stochastic FIR filters (2016) (27)
- Efficient implementation of lifting-based discrete wavelet transform (2002) (25)
- A Compact Single-FPGA Fading-Channel Simulator (2008) (22)
- Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs (1995) (22)
- A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels (2008) (21)
- Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures (2016) (21)
- An Improved SOS-Based Fading Channel Emulator (2007) (21)
- Detection of coupling faults in RAMs (1990) (21)
- An Accurate and Compact Rayleigh and Rician Fading Channel Simulator (2008) (20)
- An optimal march test for locating faults in DRAMs (1993) (19)
- Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy (2018) (19)
- Design and Characterization of a Multilevel DRAM (2011) (18)
- A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs (1994) (18)
- An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading (2010) (18)
- Variation-Resilient True Random Number Generators Based on Multiple STT-MTJs (2018) (18)
- Hardware Implementation of Nakagami and Weibull Variate Generators (2012) (17)
- Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders (2010) (17)
- Design of a 3-D fully depleted SOI computational RAM (2005) (17)
- A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes (2009) (17)
- Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder (2007) (16)
- Improved layered MIMO detection algorithm with near-optimal performance (2009) (15)
- A GoP based FEC technique for packet based video streaming (2006) (15)
- Novel architectures for the lifting-based discrete wavelet transform (2002) (15)
- A comparative simulation study of four multilevel DRAMs (1999) (15)
- Accurate multiple-input multiple-output fading channel simulator using a compact and highthroughput reconfigurable architecture (2011) (14)
- Hardware-based Error Rate Testing of Digital Baseband Communication Systems (2008) (14)
- Compact Implementation of a Sum-of-Sinusoids Rayleigh Fading Channel Simulator (2006) (14)
- FPGA-based accelerator for the verification of leading-edge wireless systems (2009) (14)
- Design of a multilevel DRAM with adjustable cell capacity (2001) (13)
- A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions (2010) (13)
- An electrical simulation model for the chalcogenide phase-change memory cell (2003) (12)
- Near-optimal tests for classes of write-triggered coupling faults in RAMs (1992) (12)
- Comparison of different cooperation strategies in the prey-predator problem (2007) (11)
- Hardware Implementation of Rayleigh and Ricean Variate Generators (2011) (11)
- Tutorial on magnetic tunnel junction magnetoresistive random-access memory (2004) (11)
- Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier (2019) (11)
- Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints (2019) (11)
- Efficient allocation of packet-level forward error correction in video streaming over the Internet (2007) (11)
- The emergence of high-density semiconductor-compatible spintronic memory (2003) (10)
- DSP-RAM: A logic-enhanced memory architecture for communication signal processing (1999) (9)
- Area-efficient parallel white Gaussian noise generator (2005) (9)
- Implementation of DSP-RAM: an architecture for parallel digital signal processing in memory (2001) (9)
- A single-FPGA multipath MIMO fading channel simulator (2008) (9)
- Signal classification in digital telephone networks (1995) (9)
- A 20 MHz test vector generator for producing tests that detect single 4- and 5-coupling faults in RAMs (1993) (8)
- Minimizing the number of process corner simulations during design verification (2015) (8)
- Cost models for large file memory DRAMs with ECC and bad block marking (1999) (8)
- Automatic Selection of Process Corner Simulations for Faster Design Verification (2018) (8)
- A multilevel DRAM with hierarchical bitlines and serial sensing (2003) (8)
- Stochastic circuit design and performance evaluation of vector quantization (2015) (8)
- A Flexible Filter Processor for Fading Channel Simulation (2007) (7)
- FPGA-Accelerated Baseband Design and Verification of Broadband MIMO Wireless Systems (2009) (7)
- Fault models and tests for coupling faults in random-access memories (1992) (7)
- High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis (2020) (7)
- Efficient parallel implementation of motion estimation on the Computational RAM architecture (2002) (7)
- On the Effects of Colored Noise on the Performance of LDPC Codes (2006) (7)
- Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density (2006) (7)
- Design and evaluation of stochastic FIR filters (2015) (6)
- HDL2GDS: a fully automated ASIC digital design flow (2005) (6)
- An iterative hardware Gaussian noise generator (2005) (6)
- Test and characterization of a variable-capacity multilevel DRAM (2005) (6)
- Optimization of Low-Density Parity Check decoder performance for OpenCL designs synthesized to FPGAs (2017) (6)
- A flexible layered architecture for accurate digital baseband algorithm development and verification (2009) (6)
- A synthesizable ram bist circuit for applying an O(n log/sub 2/ n) test that detects scrambled static pattern-sensitive faults (1996) (6)
- Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination (2008) (5)
- On the efficiency and accuracy of hybrid pseudo-random number generators for FPGA-based simulations (2008) (5)
- Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation (2012) (5)
- A Reconfigurable SOS-based Rayleigh Fading Channel Simulator (2006) (5)
- An Accurate MIMO Fading Channel Simulator Using a Compact and High-Throughput Reconfigurable Architecture (2010) (5)
- Filter-based fading channel modeling (2012) (5)
- A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes (2008) (5)
- A novel voiceband QAM constellation discrimination technique (1997) (5)
- Improved Iterative Bit Flipping Decoding Algorithms for LDPC Convolutional Codes (2007) (5)
- Fault models and test strategies for a two-bit per cell DRAM (1998) (5)
- Switch-level testability of the dynamic CMOS PLA (1990) (5)
- Voiceband signal classification using statistically optimal combinations of low-complexity discriminant variables (1999) (5)
- Low-Power Approximate Logarithmic Squaring Circuit Design for DSP Applications (2022) (4)
- A Compact and Accurate FPGA Based Nonisotropic Fading Channel Simulator (2007) (4)
- Enhanced MIMO detection with parallel V-BLAST (2011) (4)
- Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression (2019) (4)
- Dynamic combined pattern-parallel and fault-parallel fault simulation on computational RAM (1999) (4)
- Design of a 3D fully-depleted SOI computational RAM (2002) (4)
- Fault Models and Tests for a 2-Bit-per-Cell MLDRAM (1999) (4)
- Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells (2006) (3)
- A versatile fading simulator for on-chip verification of MIMO communication systems (2009) (3)
- High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath (2009) (3)
- Parallel filtering and thresholding of images on the SIMD DSP-RAM architecture (2002) (3)
- Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification (2012) (3)
- A reconfigurable digital IC tester implemented using the ARM Integrator rapid prototyping system (2004) (3)
- Design of an embedded fully-depleted SOI SRAM (2001) (3)
- A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks (2021) (3)
- An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems (2006) (3)
- Transition maximization techniques for enhancing the two-pattern fault coverage of pseudorandom test pattern generators (1998) (3)
- DRAM Architecture and Testing (1999) (2)
- A novel gate grading approach for soft error tolerance in combinational circuits (2016) (2)
- Tutorial on DRAM fault modeling and test pattern design (1998) (2)
- Implementation and evaluation of an accurate real-time voiceband signal classifier (1998) (2)
- Fault modeling and pattern-sensitivity testing for a multilevel DRAM (2002) (2)
- Electromagnetic Energy and Data Transfer in Biological Tissues Using Loop Antennas (2013) (2)
- Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models (2011) (2)
- SRAM memory margin probability failure estimation using Gaussian Process regression (2016) (1)
- Near-optimal and efficient MIMO detectors for 64-QAM symbols (2010) (1)
- A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing (2007) (1)
- Parallel implementations of transition fault simulation on computational RAM (C/spl middot/RAM) (1998) (1)
- Fast and low-power leading-one detectors for energy-efficient logarithmic computing (2021) (1)
- Performance evaluation of three memory sense amplifiers with input offset cancellation (2004) (1)
- Single FPGA Simulator for Geometric MIMO Fading Channel Models (2010) (1)
- Implementation of decoders for symmetric low density parity check codes on parallel computation platforms using OpenCL (2016) (1)
- Performance evaluation of LDPC codes in the presence of colored noise (2005) (1)
- Adaptive dual-threshold neural signal compression suitable for implantable recording (2014) (1)
- Efficient implementation of the discrete wavelet transform on the parallel DSP-RAM architecture (2001) (1)
- Spintronic Solutions for Stochastic Computing (2019) (1)
- Low power asynchronous packet-based baseband transceiver for wireless sensor networks (2012) (1)
- An efficient functional test for the massively-parallel C/spl middot/RAM logic-enhanced memory architecture (2003) (1)
- An Empirical Evaluation of Semiconductor File Memory as a Disk Cache (2006) (1)
- Designing Next-generation Implantable Wireless Telemetry (2014) (1)
- Electromagnetic Energy and Data Transfer for a Neural Implant (2013) (0)
- Neural Spike Compression Using Feature Extraction and a Fuzzy C-Means Codebook (2014) (0)
- Survey of Emerging Nonvolatile Embedded Memory Technologies (2003) (0)
- Experimental evaluation of voiceband fractionally-spaced blind equalizer based on the constant modulus algorithm (2000) (0)
- A Parallel Decoder Algorithm for Low Density Parity Check Convolutional Codes for the XInC Multi-threaded Microprocessor (2006) (0)
- Simplified jitter analysis and performance-enhancing extensions for the SRTS mode of ATM AAL-1 (1997) (0)
- Design and implementation of LT codec architecture with optimized degree distribution (2013) (0)
- Guest Editors' Introduction: DRAM Architecture and Testing (1999) (0)
- Auto-calibration technique for on-chip reference voltage generation in ferroelectric memories (2005) (0)
- Design of an Imaging Payload for Earth Observation from a Nanosatellite (2021) (0)
- Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements (2007) (0)
- Layered space-time multiple-input multiple-output detector with parameterisable performance (2012) (0)
- Quantitative Evaluation of Low Density Parity Check Convolutional Code Encoder and Decoder Algorithms for the XInC MIMD Multithreaded Microprocessor (2007) (0)
- Measuring the potential benefits of a dynamically adaptive cache line size (2005) (0)
- Performance evaluation of LDPC codes in the presence of ISI with application to 10GBASE-T Ethernet (2005) (0)
- A flexible FPGA-based MIMO geometric fading channel simulator for rapid prototyping (2009) (0)
- An investigation into three-level ferroelectric memory (2005) (0)
- Recent developments in dram testing (1996) (0)
- Panel on Advanced Embedded Memory Technologies (2002) (0)
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What Are Bruce Cockburn's Academic Contributions?
Bruce Cockburn is most known for their academic work in the field of communications. They are also known for their academic work in the fields of
Bruce Cockburn has made the following academic contributions:
