Cecilia Metra
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Cecilia Metracomputer-science Degrees
Computer Science
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Computer Engineering
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Computer Science
Cecilia Metra's Degrees
- PhD Computer Science University of Bologna
- Masters Computer Engineering University of Bologna
- Bachelors Computer Engineering University of Bologna
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Why Is Cecilia Metra Influential?
(Suggest an Edit or Addition)According to Wikipedia, Cecilia Metra is an electrical engineer at the University of Bologna in Italy. She was named a Fellow of the Institute of Electrical and Electronics Engineers in 2014 "for her contributions to the online testing and fault-tolerant design of digital circuits and systems".
Cecilia Metra's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Latch Susceptibility to Transient Faults and New Hardening Approach (2007) (134)
- A model for transient fault propagation in combinatorial logic (2003) (131)
- Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA (2008) (106)
- Modeling Crosstalk Effects in CNT Bus Architectures (2007) (103)
- Multiple transient faults in logic: an issue for next generation ICs? (2005) (96)
- High-Performance Robust Latches (2010) (90)
- Exploiting ECC redundancy to minimize crosstalk impact (2005) (85)
- Novel transient fault hardened static latch (2003) (79)
- On-line detection of logic errors due to crosstalk, delay, and transient faults (1998) (75)
- Configurable Error Control Scheme for NoC Signal Integrity (2007) (70)
- Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines (2000) (57)
- Modeling and Detection of Hotspot in Shaded Photovoltaic Cells (2015) (55)
- On transistor level gate sizing for increased robustness to transient faults (2005) (55)
- New ECC for crosstalk impact minimization (2005) (53)
- Error correcting code analysis for cache memory high reliability and performance (2011) (49)
- Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates (2009) (47)
- Low Cost NBTI Degradation Detection and Masking Approaches (2013) (47)
- TMR voting in the presence of crosstalk faults at the voter inputs (2004) (46)
- Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems (1998) (41)
- Reversible and Testable Circuits for Molecular QCA Design (2008) (36)
- Impact of Aging Phenomena on Soft Error Susceptibility (2011) (36)
- Testing Reversible 1D Arrays for Molecular QCA (2006) (35)
- Accurate Linear Model for SET Critical Charge Estimation (2009) (35)
- Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing (1999) (34)
- Power Consumption of Fault Tolerant Busses (2008) (34)
- Transient and permanent fault diagnosis for FPGA-based TMR systems (1999) (33)
- Novel technique for testing FPGAs (1998) (32)
- Coding scheme for low energy consumption fault-tolerant bus (2002) (31)
- Impact of Bias Temperature Instability on Soft Error Susceptibility (2015) (31)
- Implications of clock distribution faults and issues with screening them during manufacturing testing (2004) (30)
- On-line testing scheme for clock's faults (1997) (29)
- Optimization of error detecting codes for the detection of crosstalk originated errors (2001) (29)
- Sensing circuit for on-line detection of delay faults (1996) (29)
- On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits (1997) (28)
- New high speed CMOS self-checking voter (2004) (26)
- Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits (2005) (26)
- Error Correcting Strategy for High Speed and High Density Reliable Flash Memories (2003) (25)
- Online testing approach for very deep-submicron ICs (2002) (24)
- Highly testable and compact single output comparator (1997) (24)
- Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic (2008) (23)
- On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems (2001) (22)
- Self-checking monitor for NBTI due degradation (2010) (21)
- Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition (2011) (20)
- Coding techniques for low switching noise in fault tolerant busses (2005) (20)
- Low cost scheme for on-line clock skew compensation (2005) (20)
- Power consumption of fault tolerant codes: the active elements (2003) (19)
- Concurrent detection of power supply noise (2003) (18)
- Embedded two-rail checkers with on-line testing ability (1996) (18)
- Self-checking scheme for the on-line testing of power supply noise (2002) (17)
- Concurrent Checking of Clock Signal Correctness (1998) (16)
- Novel Berger code checker (1995) (16)
- Achieving fault-tolerance by shifted and rotated operands in TMR non-diverse ALUs (2000) (16)
- Testing of resistive bridging faults in CMOS flip-flop (1993) (15)
- Self-checking scheme for very fast clocks' skew correction (1999) (15)
- Novel low-cost aging sensor (2010) (15)
- Compact and highly testable error indicator for self-checking circuits (1996) (15)
- Clock calibration faults and their impact on quality of high performance microprocessors (2003) (15)
- Compact and low power on-line self-testing voting scheme (1997) (14)
- Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults (1995) (14)
- Fast and low-cost clock deskew buffer (2004) (14)
- Transient Fault and Soft Error On-die Monitoring Scheme (2010) (14)
- Model for Transient Fault Susceptibility of Combinational Circuits (2004) (14)
- Can clock faults be detected through functional test? (2006) (13)
- Novel fault-tolerant adder design for FPGA-based systems (2001) (13)
- Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality? (2007) (13)
- Novel on-chip circuit for jitter testing in high-speed PLLs (2005) (12)
- Novel 1-out-of-n CMOS checker (1994) (12)
- Crosstalk effect minimization for encoded busses (2003) (12)
- High speed and highly testable parallel two-rail code checker (2003) (12)
- New Design for Testability Approach for Clock Fault Testing (2012) (12)
- Novel approach to reduce power droop during scan-based logic BIST (2013) (12)
- The other side of the timing equation: a result of clock faults (2005) (11)
- Impact of Aging Phenomena on Latches’ Robustness (2016) (11)
- On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits (2002) (11)
- On-Chip Clock Faults' Detector (2002) (11)
- Error Correcting Codes for Crosstalk Effect Minimization (2003) (10)
- Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes] (2004) (10)
- Secure communication protocol for wireless sensor networks (2010) (10)
- Low cost and high speed embedded two-rail code checker (2005) (10)
- Low-area on-chip circuit for jitter measurement in a phase-locked loop (2004) (10)
- Novel Approach to Clock Fault Testing for High Performance Microprocessors (2007) (10)
- A highly testable 1-out-of-3 CMOS checker (1993) (10)
- GMOS Checkers with Testable Bridging and Transistor Stuck-on Faults (1992) (9)
- Evaluation of clock distribution networks' most likely faults and produced effects (2001) (9)
- Fast and compact error correcting scheme for reliable multilevel flash memories (2002) (9)
- Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors (2008) (9)
- Novel High Speed Robust Latch (2009) (8)
- On the selection of unidirectional error detecting codes for self-checking circuits area overhead and performance optimization (2005) (8)
- 10th IEEE International On-Line Testing Symposium (2004) (8)
- Tree checkers for applications with low power-delay requirements (1996) (7)
- Low-level error recovery mechanism for self-checking sequential circuits (1997) (7)
- Automatic modification of sequential circuits for self-checking implementation (2003) (7)
- Self-Checking Voter for High Speed TMR Systems (2005) (7)
- Analysis of the impact of bus implemented EDCs on on-chip SSN (2006) (7)
- Testing Resistive Opens and Bridging Faults Through Pulse Propagation (2009) (6)
- Fault-Tolerant Inverters for Reliable Photovoltaic Systems (2019) (6)
- Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST (2017) (6)
- Faults affecting the control blocks of PV arrays and techniques for their concurrent detection (2012) (6)
- Novel compensation scheme for local clocks of high performance microprocessors (2007) (6)
- Fast and area-time efficient Berger code checkers (1997) (6)
- Clock faults' impact on manufacturing testing and their possible detection through on-line testing (2002) (6)
- High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies (2012) (5)
- Problems due to open faults in the interconnections of self-checking data paths (2002) (5)
- Risks for Signal Integrity in System in Package and Possible Remedies (2008) (5)
- Signal coding technique and CMOS gates for strongly fault-secure combinational functional blocks (1998) (5)
- Design rules for CMOS self checking circuits with parametric faults in the functional block (1993) (5)
- Path (min) delay faults and their impact on self-checking circuits operation (2006) (5)
- Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects (2006) (5)
- Testing scheme for IC's clocks (1997) (5)
- Highly testable and compact 1-out-of-n code checker with single output (1998) (4)
- On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter (2010) (4)
- Self-checking design, implementation, and measurement of a controller for track-side railway systems (2003) (4)
- Error correcting codes for crosstalk effect minimization [system buses] (2003) (4)
- Pulse propagation for the detection of small delay defects (2007) (4)
- CMOS self checking circuits with faulty sequential functional blocks (1994) (4)
- Trading Off Dependability and Cost for Nanoscale High Performance Microprocessors : The Clock Distribution Problem (2009) (4)
- Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST (2016) (4)
- Low-Cost On-Chip Clock Jitter Measurement Scheme (2015) (4)
- Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness (2018) (4)
- Intermediacy Prediction for High Speed Berger Code Checkers (2000) (3)
- Are our design for testability features fault secure? (2004) (3)
- Design of CMOS self-checking sequential circuits with improved detectability of bridging faults (1994) (3)
- Checker no-harm alarm robustness (2006) (3)
- Simultaneous Switching Noise: The Relation between Bus Layout and Coding (2008) (3)
- Power droop reduction during Launch-On-Shift scan-based logic BIST (2014) (3)
- Hardware reconfiguration scheme for high availability systems (2004) (3)
- Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC) (2006) (3)
- Fault secureness need for next generation high performance microprocessor design for testability structures (2004) (2)
- Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits (2000) (2)
- Early detection of photovoltaic system inverter faults (2022) (2)
- 1-out-of-3 code checker with single output (1997) (2)
- Low-Cost Strategy for Bus Propagation Delay Reduction (2019) (2)
- Interactive presentation: Pulse propagation for the detection of small delay defects (2007) (2)
- Inverters' self-checking monitors for reliable photovoltaic systems (2016) (2)
- On the design of self-checking functional units based on Shannon circuits (1999) (2)
- Testing Reversible One-Dimensional QCA Arrays for Multiple F (2007) (2)
- Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults (2003) (2)
- Resistive Crossbar Switching Networks for Inherently Fault Tolerant Nano LUTs (2008) (2)
- Design and implementation of a self-checking scheme for railway trackside systems (2002) (2)
- Fast and compact error correcting scheme for reliable multilevel flash memories (2002) (2)
- Intermittent and Transient Fault Diagnosis on Sparse Code Signatures (2015) (2)
- Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection (2013) (2)
- Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors (2010) (2)
- Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder (2013) (1)
- Checkers’ No-Harm Alarms and Design Approaches to Tolerate Them (2008) (1)
- Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures (2001) (1)
- 1-out-of-n dynamic CMOS checker (1995) (1)
- Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems (2011) (1)
- Design and implementation of a self-checking scheme for railway trackside systems (2002) (1)
- Enhanced reliability evaluation for self-checking circuits (1994) (1)
- Cryptanalysis of Simplified-AES Encrypted Communication (2015) (1)
- Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions (2022) (1)
- Low Cost NBTI Degradation Detection & Masking Approaches (2011) (1)
- Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors (2009) (1)
- On-line testing and diagnosis scheme for intermediate voltage values affecting bus lines (2000) (1)
- The 2019 IEEE Computer Society: Hit Target on Member Satisfaction and Technical Excellence (2019) (0)
- Polynomial Based Key Distribution Scheme for WPAN (2013) (0)
- New Approaches for Power Binning of High Performance Microprocessors (2017) (0)
- Session details: Power awareness (2004) (0)
- Seminar of Dr. Gaudiot: "Hardware and Software Issues in the Future" (2017) (0)
- Risks associated with faults within test pattern compactors and their implications on testing (2004) (0)
- A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features (2006) (0)
- Guest Editor's Introduction: Special Section on High Dependability Systems (2020) (0)
- 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - itle Page (2005) (0)
- Bridging Faults in Pipelined Circuits (2000) (0)
- Simultaneous switching noise analysis: The relation between bus layout, coding and switching patterns (2007) (0)
- Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder (2013) (0)
- Welcome message from the chairs (2021) (0)
- Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage (2019) (0)
- Leakage power reduction for reactive computation (2000) (0)
- GUEST EDITORIAL (2012) (0)
- Proceedings, 9th IEEE International On-Line Testing Symposium : IOLTS 2003, 7-9 July 2003, Kos International Convention Center, Kos Island, Greece (2003) (0)
- On-Line Test and Fault Tolerance (2005) (0)
- Seminar of Dr. Zorian: "Automotive Chips Today: Quality, Reliability & Security" (2017) (0)
- [Publisher's information] (2015) (0)
- ATS 2019 Welcome Message (2019) (0)
- On-line testing and diagnosis of bus lines with respect to intermediate voltage values (2000) (0)
- Session details: Soft error evaluation and tolerance (2007) (0)
- Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function (2022) (0)
- Message from the Editor‐in‐Chief (2017) (0)
- Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems (2001) (0)
- Clock Faults Induced Min and Max Delay Violations (2013) (0)
- Clock Faults Induced Min and Max Delay Violations (2014) (0)
- Functional Blocks of CMOS Self-Checking Circuits (1997) (0)
- Seminar of Dr. Canini: "Create New Products: an Industria Perspective" (2017) (0)
- The 2019 IEEE Computer Society: Targeting Member Satisfaction and Technical Excellence (2019) (0)
- Seminar of Prof. Zaslavsky (part 1): "CMOS-Compatible alternative end-of-roadmap devices" (2017) (0)
- Proceedings 10th IEEE International On-Line Testing Symposium (2004) (0)
- VTS 2008 Best Paper Award (2008) (0)
- Guest Editorial (2003) (0)
- Guest Editors' Introduction: The State of the Art in Nanoscale CAD (2007) (0)
- Seminar of Dr. Alt (part 1): "Scan Compression Techniques to Improve Test Time and Quality" (2017) (0)
- Session details: Concurrency and scheduling (2010) (0)
- Guest Editorial (2004) (0)
- Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors (2011) (0)
- Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection (2022) (0)
- Seminar of Dr. Albanese: "New Product Development Process, the 3C: Constrained Collective Creativity" (2018) (0)
- Design of Custom ASIC for Radiation Experiments to Study Single Event Effects (2017) (0)
- International TestConference 2008 Technical Program Committee (2008) (0)
- Highly testable and compact 1-out-of-n CMOS checkers (1994) (0)
- Guest Editorial (2002) (0)
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Cecilia Metra is affiliated with the following schools:
