Charles Zukowski | Academic Influence

Charles Zukowski's AcademicInfluence.com Rankings

Charles Zukowski

Computer Science

#3928

World Rank

#4128

Historical Rank

Machine Learning

#5888

World Rank

#5976

Historical Rank

Artificial Intelligence

#6348

World Rank

#6456

Historical Rank

Database

#9857

World Rank

#10445

Historical Rank

computer-science Degrees

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Computer Science

Charles Zukowski's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science University of California, Berkeley

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Why Is Charles Zukowski Influential?

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According to Wikipedia, Charles Albert Zukowski is a professor and former chair of the Department of Electrical Engineering at Columbia University. Zukowski was born in Buffalo, New York. While still a student at MIT, from 1979 to 1982, Zukowski worked at the Thomas J. Watson Research Center. He received his BS in electrical engineering from the Massachusetts Institute of Technology in 1982. He received the IBM PhD Fellowship from 1982 to 1985; in 1985 he earned his PhD in electrical engineering with a thesis entitled "Design and measurement of a reconfigurable multi-microprocessor machine". The same year, he joined the faculty of Columbia University as assistant professor, and was awarded tenure in 1993. Zukowski is an active member of IEEE and was made an IEEE Fellow in 2000. Zukowski's present research focuses on VLSI circuits and integrated circuit optimization, though in the past he has published in the fields of systems biology and computer architecture.

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Charles Zukowski's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

High-speed parallel CRC circuits in VLSI (1992) (176)
Putting routing tables in silicon (1992) (97)
Use of selective precharge for low-power content-addressable memories (1997) (91)
VLSI implementation of routing tables: tries and CAMs (1991) (54)
Use of selective precharge for low-power on the match lines of content-addressable memories (1997) (44)
An assessment of on-line engineering design problem presentation strategies (2000) (32)
Integrated-Circuit Logarithmic Arithmetic Units (1985) (30)
Convergence properties of waveform relaxation circuit simulation methods (1998) (26)
Relaxing Bounds for Linear RC Mesh Circuits (1986) (24)
The Bounding Approach to VLSI Circuit Simulation (1986) (19)
CMOS transistor sizing for minimization of energy-delay product (1996) (17)
Step response bounds for systems described by M-matrices, with application to timing analysis of digital MOS circuits (1985) (13)
A custom FPGA for the simulation of gene regulatory networks (2003) (12)
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies (2005) (11)
Characterization of monotonic static CMOS gates in a 65nm technology (2005) (10)
The cylinder switch: an architecture for a manageable VLSI giga-cell switch (1990) (8)
High-speed data transmission using low-frequency clocks (1991) (7)
Measuring error propagation in waveform relaxation algorithms (1990) (7)
Sensitivity of Nonlinear One-Port Resistor Networks (1984) (7)
The Waveform Bounding Approach to Timing Analysis of Digital MOS IC's (1983) (6)
Differential high-bandwidth communication circuits (1990) (6)
CMOS optimization including logic family mixing (1991) (6)
Continuous Models for Communication Density Constraints on Multiprocessor Performance (1988) (5)
Convergence of Waveform Relaxation for RC Circuits (1994) (5)
A matched-delay CMOS TDM multiplexer cell (1988) (5)
Characteristics of MS-CMOS logic in sub-32nm technologies (2010) (4)
Jitter due to signal history in digital logic circuits and its control strategies (1993) (4)
Characterization of logic circuit techniques for high leakage CMOS technologies (2004) (4)
Performance comparison of differential static CMOS circuit topologies in SOI technology (1998) (4)
Variable reduction in MOS timing models (1988) (4)
A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology (2006) (3)
Buffer size trade-offs in input/output buffered ATM switches under various conditions (1995) (3)
Comparison of a wide range of differential CMOS logic topologies (1996) (3)
Metastability of SOI CMOS latches (1997) (3)
A VLSI design and cost analysis of broadband ATM switch elements (1994) (3)
Generic queue scheduling: concepts and VLSI (1994) (3)
A self-timed cyclic redundancy check (CRC) in VLSI (1997) (3)
Putting Routing Tables in Silicon Moving routing tables from RAM to custom or semi-custom VLSI can lower cost and boost performance (1992) (3)
Methods for analyzing relaxation-based circuit simulation algorithms (1992) (3)
Analysis of the logic model used in selective precharge (1999) (2)
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004 (2004) (2)
A compiler for communication network interface circuits (1992) (2)
Monotonic static CMOS tradeoffs in sub-100nm technologies (2006) (2)
VLSI design optimization of input/output-buffered broadband ATM switches (1996) (2)
VLSI Circuit Simulation (1986) (2)
High-frequency pattern generation using multiple input channels and combinational logic (1994) (2)
Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage (2004) (1)
Macromodeling BiCMOS gates for circuit optimization (1993) (1)
Analysis and control of timing jitter in digital logic arising from noise voltage sources (1993) (1)
Implementing a high-frequency pattern generator based on combinational merging (1992) (1)
An efficient macromodel for static CMOS multi-port memories (1993) (1)
Reconfigurable Digital/Analog Processor Array for the Simulation of Gene Regulatory Networks (2006) (1)
VLSI implementations of ATM buffer management (1991) (1)
Gene Reguratory Networks IC report (2002) (0)
Application of dynamic power supply scaling in a low-energy ATM interface (2000) (0)
Simulation with Bounds (1986) (0)
The VLSI Circuit Model (1986) (0)
Energy reduction from using selective precharge in two different logic arrays (2000) (0)
Nibble Mode Realization of Parallel CRC (2011) (0)
Delay-time bounds and waveform bounds for RLCG ladder networks (1994) (0)
Self-timed cyclic redundancy check (CRC) in VLSI (1999) (0)
Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits (1996) (0)
Algorithms and Experimental Results (1986) (0)
Accuracy management for mixed-mode digital VLSI simulation (2000) (0)
Design and measurement of a reconfigurable multi-microprocessor machine (1982) (0)
Solid Geometry in Chemistry. (1978) (0)
Introduction: VLSI in the nanometer era (2005) (0)
Trading system performance for energy use in a VLSI implementation of an adaptive equalizer (2000) (0)
Programmable routing of interrupts in a multiprocessor network (1982) (0)
A method for identifying CMOS circuits with multiple DC operating points through topological criteria (1992) (0)

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