Chenming Hu
#9,254
Most Influential Person Now
Electrical engineer working in the USA and Taiwan
Chenming Hu's AcademicInfluence.com Rankings
Chenming Huengineering Degrees
Engineering
#258
World Rank
#483
Historical Rank
Electrical Engineering
#74
World Rank
#86
Historical Rank
Download Badge
Engineering
Chenming Hu's Degrees
- PhD Electrical Engineering University of California, Berkeley
- Masters Electrical Engineering University of California, Berkeley
- Bachelors Electrical Engineering National Taiwan University
Why Is Chenming Hu Influential?
(Suggest an Edit or Addition)According to Wikipedia, Chenming Calvin Hu is a Chinese-American electronic engineer who specializes in microelectronics. He is TSMC Distinguished Professor Emeritus in the electronic engineering and computer science department of the University of California, Berkeley, in the United States. In 2009, the Institute of Electrical and Electronics Engineers described him as a “microelectronics visionary … whose seminal work on metal-oxide semiconductor MOS reliability and device modeling has had enormous impact on the continued scaling of electronic devices”.
Chenming Hu's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- FinFET-a self-aligned double-gate MOSFET scalable to 20 nm (2000) (1486)
- Hot-electron-induced MOSFET degradation—Model, monitor, and improvement (1985) (967)
- MoS2 transistors with 1-nanometer gate lengths (2016) (934)
- A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors (1990) (808)
- Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement (1985) (701)
- FinFET scaling to 10 nm gate length (2002) (574)
- Field-effect transistors built from all two-dimensional material components. (2014) (558)
- Electrical breakdown in thin gate and tunneling oxides (1985) (531)
- Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation (1994) (510)
- New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation (2000) (503)
- MOS capacitance measurements for high-leakage thin dielectrics (1999) (493)
- Modern Semiconductor Devices for Integrated Circuits (2009) (473)
- Threshold voltage model for deep-submicrometer MOSFETs (1993) (456)
- Sub 50-nm FinFET: PMOS (1999) (431)
- Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI (1997) (414)
- Frequency-independent equivalent circuit model for on-chip spiral inductors (2002) (401)
- Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology (2002) (397)
- Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling (2001) (340)
- Enhanced ferroelectricity in ultrathin films grown directly on silicon (2020) (312)
- Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation (2011) (298)
- Sub-50 nm P-channel FinFET (2001) (293)
- Effect of Top Electrode Material on Resistive Switching Properties of $\hbox{ZrO}_{2}$ Film Memory Devices (2007) (292)
- Germanium-source tunnel field effect transistors with record high ION/IOFF (2006) (281)
- Lucky-electron model of channel hot-electron injection in MOSFET'S (1984) (279)
- Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's (1984) (277)
- Extremely scaled silicon nano-CMOS devices (2003) (262)
- A physics-based MOSFET noise model for circuit simulators (1990) (253)
- Sub-60mV-swing negative-capacitance FinFET without hysteresis (2015) (241)
- 2D-2D tunneling field-effect transistors using WSe2/SnSe2 heterostructures (2016) (234)
- A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation (1994) (233)
- 5nm-gate nanowire FinFET (2004) (231)
- Electrical characteristics of ferroelectric PZT thin films for DRAM applications (1992) (229)
- Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime (2000) (224)
- A folded-channel MOSFET for deep-sub-tenth micron era (1998) (222)
- Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/ (2001) (219)
- MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations (2003) (214)
- Sub-20 nm CMOS FinFET technologies (2001) (211)
- Future CMOS scaling and reliability (1993) (209)
- A spacer patterning technology for nanoscale CMOS (2002) (209)
- MOSFET Modeling & BSIM3 User’s Guide (1999) (208)
- Ultrathin-body SOI MOSFET for deep-sub-tenth micron era (2000) (208)
- A comparative study of advanced MOSFET concepts (1996) (205)
- Berkeley reliability tools-BERT (1993) (198)
- Stress-induced current in thin silicon dioxide films (1992) (191)
- Substrate hole current and oxide breakdown (1986) (190)
- Switch-induced error voltage on a switched capacitor (1984) (189)
- A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation (1997) (187)
- Si tunnel transistors with a novel silicided source and 46mV/dec swing (2010) (182)
- An effective gate resistance model for CMOS RF and noise modeling (1998) (179)
- Direct tunneling leakage current and scalability of alternative gate dielectrics (2002) (178)
- An adjustable work function technology using Mo gate for CMOS devices (2002) (178)
- Lucky-electron model of channel hot-electron injection in MOSFET'S (1984) (177)
- 25 nm CMOS Omega FETs (2002) (177)
- Gate length scaling and threshold voltage control of double-gate MOSFETs (2000) (176)
- Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor (2016) (176)
- Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits (2002) (175)
- Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric (2000) (174)
- Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's (1997) (173)
- On thermal effects in deep sub-micron VLSI interconnects (1999) (171)
- Dual work function metal gate CMOS technology using metal interdiffusion (2001) (168)
- Quantum yield of electron impact ionization in silicon (1985) (164)
- Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions (2002) (157)
- Sub-60-nm quasi-planar FinFETs fabricated using a simplified process (2001) (148)
- Nanoscale CMOS spacer FinFET for the terabit era (2002) (145)
- A new look at impact ionization-Part II: Gain and noise in short avalanche photodiodes (1999) (145)
- SOI thermal impedance extraction methodology and its significance for circuit simulation (2001) (145)
- Electromigration in Al(Cu) two-level structures: Effect of Cu and kinetics of damage formation (1993) (144)
- Tunnel Field Effect Transistor With Raised Germanium Source (2010) (141)
- An analytical breakdown model for short-channel MOSFET's (1982) (139)
- Electron-trap generation by recombination of electrons and holes in SiO2 (1987) (132)
- Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics (2016) (130)
- Gate oxide scaling limits and projection (1996) (129)
- Single crystal functional oxides on silicon (2015) (127)
- MOSFET Modeling and Bsim3 User's Guide (1999) (127)
- An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique (1996) (126)
- Temperature acceleration of time-dependent dielectric breakdown (1989) (124)
- A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation (1994) (122)
- Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability (1994) (120)
- Lucky-electron model of channel hot electron emission (1979) (120)
- Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's (1986) (118)
- A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation (1998) (116)
- Prospect of tunneling green transistor for 0.1V CMOS (2010) (114)
- CMOS RF modeling for GHz communication IC's (1998) (114)
- Reliability of thin SiO2 (1994) (113)
- Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model (1992) (113)
- Rapid (<5 min) Identification of Pathogen in Human Blood by Electrokinetic Concentration and Surface-Enhanced Raman Spectroscopy (2013) (112)
- Work Function Engineering of Molybdenum Gate Electrodes by Nitrogen Implantation (2001) (112)
- A capacitorless double-gate DRAM cell (2002) (111)
- Random telegraph noise in flash memories - model and technology scaling (2007) (111)
- Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation (1998) (108)
- A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation (1991) (108)
- Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors (2018) (108)
- MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages (1996) (108)
- Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric (2001) (106)
- Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction (2004) (106)
- BSIM—SPICE Models Enable FinFET and UTB IC Designs (2013) (105)
- FinFET-a quasi-planar double-gate MOSFET (2001) (105)
- Highly crystalline MoS2 thin films grown by pulsed laser deposition (2015) (103)
- Projecting interconnect electromigration lifetime for arbitrary current waveforms (1990) (102)
- Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs (2002) (100)
- Bistable Resistive Switching in Al2O3 Memory Thin Films (2007) (100)
- Ultra-thin body SOI MOSFET for deep-sub-tenth micron era (1999) (99)
- Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages (2008) (99)
- Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions (1993) (98)
- Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits (2000) (96)
- Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation (2016) (96)
- Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology] (2000) (95)
- Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description (2016) (95)
- Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer (2014) (94)
- Optimum design of power MOSFET's (1984) (93)
- 9nm half-pitch functional resistive memory cell with <1µA programming current using thermally oxidized sub-stoichiometric WOx film (2010) (93)
- A unified gate oxide reliability model (1999) (93)
- Simulation of MOSFET lifetime under AC hot-electron stress (1988) (92)
- Modeling Advanced FET Technology in a Compact Model (2006) (88)
- BSIM6: Analog and RF Compact Model for Bulk MOSFET (2014) (87)
- Transistor characteristics with Ta/sub 2/O/sub 5/ gate dielectric (1998) (87)
- Monolithic 3D CMOS Using Layered Semiconductors (2016) (87)
- Hot-electron effects in MOSFETs (1983) (86)
- A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics (2003) (86)
- Effects of temperature and defects on breakdown lifetime of thin SiO/sub 2/ at very low voltages (1994) (85)
- Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion (2002) (85)
- Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation (1998) (85)
- Ultrathin body InAs tunneling field-effect transistors on Si substrates (2011) (84)
- Electron trapping in very thin thermal silicon dioxides (1981) (83)
- Modeling of pocket implanted MOSFETs for anomalous analog behavior (1999) (82)
- TOPICAL REVIEW: Thin gate oxide damage due to plasma processing (1996) (81)
- Quantum effect in oxide thickness determination from capacitance measurement (1999) (81)
- A charge sheet capacitance model of short channel MOSFETs for SPICE (1991) (81)
- FinFET modeling for IC simulation and design (2015) (78)
- Performance of thin separate absorption, charge, and multiplication avalanche photodiodes (1998) (78)
- High-current failure model for VLSI interconnects under short-pulse stress conditions (1997) (76)
- The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal (1996) (73)
- The impact of device scaling and power supply change on CMOS gate performance (1996) (73)
- A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation (1997) (72)
- Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics (1998) (72)
- Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects (1997) (71)
- Gate engineering for deep-submicron CMOS transistors (1998) (71)
- Hot-carrier-induced MOSFET degradation under AC stress (1987) (70)
- Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide (2019) (69)
- Compact models of negative-capacitance FinFETs: Lumped and distributed charge models (2016) (67)
- Advanced Compact Models for MOSFETs (2005) (67)
- A simple subcircuit extension of the BSIM3v3 model for CMOS RF design (2000) (66)
- Characterization of VLSI circuit interconnect heating and failure under ESD conditions (1996) (64)
- Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation (1997) (64)
- Green Transistor - A VDD Scaling Path for Future Low Power ICs (2008) (64)
- Correlation between substrate and gate currents in MOSFET's (1982) (63)
- Optimum doping profile for minimum ohmic resistance and high-breakdown voltage (1979) (63)
- Effect of low and high temperature anneal on process-induced damage of gate oxide (1994) (63)
- An AC conductance technique for measuring self-heating in SOI MOSFET's (1995) (63)
- A capacitorless DRAM cell on SOI substrate (1993) (63)
- Low power negative capacitance FETs for future quantum-well body technology (2013) (62)
- An electromigration failure model for interconnects under pulsed and bidirectional current stressing (1994) (62)
- Self-heating characterization for SOI MOSFET based on AC output conductance (1999) (61)
- Formation of buried oxide in silicon using separation by plasma implantation of oxygen (1995) (60)
- Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics (2017) (60)
- BSIM-CMG: A Compact Model for Multi-Gate Transistors (2008) (60)
- Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages (1999) (60)
- Liquid-crystal waveguides for integrated optics (1977) (60)
- A 0.1-/spl mu/m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy (1998) (60)
- Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery (2017) (60)
- A parametric study of power MOSFETs (1979) (60)
- Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel (2000) (58)
- Design in hot-carrier reliability for high performance logic applications (1998) (58)
- BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design (2007) (58)
- FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard (2015) (58)
- Engineering Negative Differential Resistance in NCFETs for Analog Applications (2018) (58)
- Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era (2002) (58)
- Losses of a nematic liquid-crystal optical waveguide* (1974) (56)
- Chapter 3 - Hot-Carrier Effects (1989) (56)
- BSIM4 and MOSFET Modeling For IC Simulation (2011) (56)
- Gate oxide scaling limits and projection (1996) (55)
- Interconnect scaling: signal integrity and performance in future high-speed CMOS designs (1998) (54)
- A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications (2003) (54)
- Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers (1992) (54)
- Device challenges and opportunities (2004) (54)
- Effects of global interconnect optimizations on performance estimation of deep submicron design (2000) (53)
- Nanoscale CMOS spacer FinFET for the terabit era (2002) (53)
- Green transistor as a solution to the IC power crisis (2008) (52)
- Optimum doping profile for minimum ohmic resistance and high-breakdown voltage (1979) (52)
- Performance and Vdd scaling in deep submicrometer CMOS (1998) (50)
- Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET (1996) (49)
- A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation (1993) (48)
- Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion (2002) (48)
- Programming characteristics of the steep turn-on/off feedback FET (FBFET) (2006) (48)
- Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors (2019) (47)
- Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium (2000) (47)
- An analytical model for the power bipolar-MOS transistor (1986) (47)
- BSIM-CMG: Standard FinFET compact model for advanced circuit design (2015) (47)
- MOSFET design for forward body biasing scheme (2006) (47)
- High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application (1995) (46)
- Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review (2014) (46)
- Dual-metal gate technology for deep-submicron CMOS transistors (2000) (46)
- Accelerated testing of SiO/sub 2/ reliability (1996) (45)
- Low-voltage CMOS device scaling (1994) (45)
- Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM (2013) (45)
- Hot-carrier-induced degradation of metal-oxide-semiconductor field-effect transistors: Oxide charge versus interface traps (1989) (44)
- Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights (2012) (44)
- Stabilization of ferroelectric phase in tungsten capped Hf0.8Zr0.2O2 (2017) (44)
- Ion-cut silicon-on-insulator fabrication with plasma immersion ion implantation (1997) (43)
- 35 nm CMOS FinFETs (2002) (43)
- E-T based statistical modeling and compact statistical circuit simulation methodologies (1996) (42)
- Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing (2012) (42)
- Metal gate work function adjustment for future CMOS technology (2001) (42)
- 50-Å gate-Oxide MOSFET's at 77 K (1987) (42)
- Device and Technology Impact on Low Power Electronics (1996) (42)
- Electromigration reliability of tungsten and aluminum vias and improvements under AC current stress (1993) (41)
- Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's (1986) (41)
- Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors (2022) (41)
- Modeling and characterization of electromigration failures under bidirectional current stress (1996) (40)
- Compact Modeling of Variation in FinFET SRAM Cells (2010) (40)
- Comparison of ESD protection capability of SOI and bulk CMOS output buffers (1994) (39)
- A simplified model of short-channel MOSFET characteristics in the breakdown mode (1983) (39)
- A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide (1999) (39)
- Circuit reliability simulator for interconnect, via, and contact electromigration (1992) (39)
- A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation (2007) (39)
- BSIM-CMG 110.0.0: Multi-gate MOSFET compact model: technical manual (2014) (39)
- Plasma etching charge-up damage to thin oxides (1993) (38)
- 0.2V adiabatic NC-FinFET with 0.6mA/µm ION and 0.1nA/µm IOFF (2015) (38)
- Efficient generation of delay change curves for noise-aware static timing analysis (2002) (38)
- Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles (2021) (37)
- Effect of oxide field on hot‐carrier‐induced degradation of metal‐oxide‐semiconductor field‐effect transistors (1987) (37)
- Modeling of GaN-Based Normally-Off FinFET (2014) (37)
- Hot-carrier reliability design guidelines for CMOS logic circuits (1993) (37)
- MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications (2001) (37)
- Polarity asymmetry of oxides grown on polycrystalline silicon (1988) (37)
- Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation (1994) (37)
- RLC signal integrity analysis of high-speed global interconnects [CMOS] (2000) (36)
- A thermal activation view of low voltage impact ionization in MOSFETs (2002) (36)
- Moore's law lives on [CMOS transistors] (2003) (35)
- Simulation Study of a 3-D Device Integrating FinFET and UTBFET (2015) (35)
- MOS memory using germanium nanocrystals formed by thermal oxidation of Si/sub 1-x/Ge/sub x/ (1998) (35)
- Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET) (2020) (35)
- Low-voltage green transistor using ultra shallow junction and hetero-tunneling (2008) (35)
- FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits (2017) (35)
- New insight into high-field mobility enhancement of nitrided-oxide N-MOSFET's based on noise measurement (1994) (35)
- An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness (1999) (35)
- Patterning sub-30-nm MOSFET gate with i-line lithography (2001) (34)
- Solar cells : from basics to advanced systems (2012) (34)
- Gate-induced band-to-band tunneling leakage current in LDD MOSFETs (1992) (34)
- A versatile, SOI BiCMOS technology with complementary lateral BJT's (1992) (34)
- A compact IGFET charge model (1984) (34)
- Loop-based interconnect modeling and optimization approach for multigigahertz clock network design (2003) (33)
- Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect (2018) (33)
- The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability (1991) (33)
- BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs (2000) (33)
- A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis (1991) (32)
- Molybdenum as a gate electrode for deep sub-micron CMOS technology (2000) (32)
- RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model (2016) (32)
- Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits (1995) (32)
- Electrical Characteristics of n, p-In0.53Ga0.47As MOSCAPs With In Situ PEALD-AlN Interfacial Passivation Layer (2014) (32)
- Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel (2002) (31)
- A 0 . 1m Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy (1998) (31)
- Silicon nanoelectronics for the 21st century (1999) (31)
- High-field transport of inversion-layer electrons and holes including velocity overshoot (1997) (31)
- Monitoring plasma-process induced damage in thin oxide (1993) (31)
- Toward a practical computer-aid for thyristor circuit design (1980) (31)
- An electro-thermal model for metal-oxide-metal antifuses (1995) (31)
- TMD FinFET with 4 nm thin body and back gate control for future low power technology (2015) (31)
- Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs (2013) (30)
- Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs (2004) (30)
- Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate (2013) (30)
- Direct sampling methodology for statistical analysis of scaled CMOS technologies (1999) (30)
- MOSFET hot-carrier reliability improvement by forward-body bias (2006) (30)
- Experimental Demonstration of a Ferroelectric HfO2-Based Content Addressable Memory Cell (2020) (30)
- Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves (2003) (30)
- Remote charge scattering in MOSFETs with ultra-thin gate dielectrics (1998) (30)
- FinFET With High- $\kappa $ Spacers for Improved Drive Current (2016) (30)
- Determination of diffusion length and surface recombination velocity by light excitation (1978) (30)
- Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate (1999) (29)
- Recovery of threshold voltage after hot-carrier stressing (1988) (29)
- A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates (2011) (29)
- Thermal characteristics of submicron vias studied by scanning Joule expansion microscopy (2000) (29)
- Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain (2001) (29)
- Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs (2001) (29)
- Impact of time dependent dielectric breakdown and stress-induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO/sub 3/ thin-film capacitors for Gbit-scale DRAMs (1999) (29)
- BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations (2012) (29)
- Dc electrical oxide thickness model for quantization of the inversion layer in MOSFETs (1998) (29)
- Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain (2001) (28)
- Separation of plasma implantation of oxygen to form silicon on insulator (1997) (28)
- A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs using SPP approach (2004) (28)
- Differential voltage amplification from ferroelectric negative capacitance (2017) (28)
- 2 D-2 D tunneling field-effect transistors using WSe 2 / SnSe 2 heterostructures (2016) (28)
- Second breakdown of vertical power MOSFET's (1982) (28)
- Modeling electromigration lifetime under bidirectional current stress (1995) (27)
- Nonvolatile semiconductor memories : technologies, design, and applications (1991) (27)
- Characterization of interconnect coupling noise using in-situ delay-change curve measurements (2000) (27)
- Electromigration under time-varying current stress (1998) (27)
- Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design (2005) (27)
- Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates (1999) (27)
- Impact of plasma charging damage and diode protection on scaled thin oxide (1993) (27)
- Performance-Aware Corner Model for Design for Manufacturing (2009) (27)
- 30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D (2000) (27)
- The Berkeley reliability simulator BERT: an IC reliability simulator (1992) (27)
- A Low Voltage Steep Turn-Off Tunnel Transistor Design (2009) (26)
- Plasma Enhanced Atomic Layer Deposition Passivated HfO2/AlN/In0.53Ga0.47As MOSCAPs With Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density (2015) (26)
- The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films (1987) (26)
- Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs (2013) (26)
- A capacitorless double-gate DRAM cell design for high density applications (2002) (26)
- Thin oxide reliability (1985) (26)
- Characterization of contact and via failure under short duration high pulsed current stress (1997) (26)
- Plasma charging damage on ultrathin gate oxides (1998) (26)
- Nearly defect-free Ge gate-all-around FETs on Si substrates (2011) (25)
- A non-quasi-static MOSFET model for SPICE-AC analysis (1992) (25)
- Interconnect devices for field programmable gate array (1992) (25)
- Thin-body FinFET as scalable low voltage transistor (2012) (25)
- Topographic measurement of electromigration-induced stress gradients in aluminum conductor lines (2000) (25)
- Enhancement of PMOS device performance with poly-SiGe gate (1999) (25)
- Circuit performance variability decomposition (1999) (25)
- Modeling the impact of substrate depletion in FDSOI MOSFETs (2015) (24)
- A non-charge-sheet analytic theory for undoped symmetric double-gate MOSFETs from the exact solution of Poisson's equation using SPP approach (2004) (24)
- Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications (1995) (24)
- MOSFET drain breakdown voltage (1986) (24)
- Oxides grown on textured single-crystal silicon-dependence on process and application of EEPROMs (1990) (24)
- A simple punchthrough model for short-channel MOSFET's (1983) (24)
- BSIM compact MOSFET models for SPICE simulation (2013) (24)
- Non-hysteretic negative capacitance FET with Sub- 30mV/dec swing over 106X current range and ION of 0.3mA/μm without strain enhancement at 0.3V VDD (2012) (24)
- Response Speed of Negative Capacitance FinFETs (2018) (24)
- A simple method for on-chip, sub-femto Farad interconnect capacitance measurement (1997) (24)
- Quasi-planar NMOS FinFETs with sub-100 nm gate lengths (2001) (24)
- A new analytical delay and noise model for on-chip RLC interconnect (2000) (23)
- Spacer Engineering in Negative Capacitance FinFETs (2019) (23)
- BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs (2020) (23)
- Optimum doping profile of power MOSFET epitaxial layer (1982) (23)
- Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gates (2001) (23)
- Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance (2018) (23)
- Ultra-thin body PMOSFETs with selectively deposited Ge source/drain (2001) (23)
- Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling (1997) (22)
- Circuit-level simulation of TDDB failure in digital CMOS circuits (1995) (22)
- Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor (2018) (22)
- Interfacial layer-free ZrO2 on Ge with 0.39-nm EOT, κ∼43, ∼2×10−3 A/cm2 gate leakage, SS =85 mV/dec, Ion/Ioff =6×105, and high strain response (2012) (22)
- Piezoelectricity-Induced Schottky Barrier Height Variations in AlGaN/GaN High Electron Mobility Transistors (2015) (22)
- Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack (2020) (22)
- A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain (2000) (22)
- Accurate in situ measurement of peak noise and delay change induced by interconnect coupling (2001) (22)
- Real-time x-ray microbeam characterization of electromigration effects in Al(Cu) wires (2001) (22)
- BSIM5 MOSFET Model (2004) (22)
- Optimization of gate oxide N/sub 2/O anneal for CMOSFET's at room and cryogenic temperatures (1994) (22)
- Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs (2019) (22)
- Capacitance Modeling in III–V FinFETs (2015) (22)
- Punchthrough diode as the transient voltage suppressor for low-voltage electronics (1996) (21)
- BSIM model for circuit design using advanced technologies (2001) (21)
- Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model (2014) (21)
- NCFET Design Considering Maximum Interface Electric Field (2018) (21)
- Separation by plasma implantation of oxygen (SPIMOX) operational phase space (1997) (21)
- A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin (2013) (21)
- Projecting CMOS circuit hot-carrier reliability from DC device lifetime (1993) (21)
- A unified MOSFET channel charge model for device modeling in circuit simulation (1998) (21)
- A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes (2012) (20)
- Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs (2014) (20)
- Ultra‐large‐scale integration device scaling and reliability (1994) (20)
- Absorption processes associated with anti‐Stokes fluorescence in rhodamine B solutions (1973) (20)
- Sub-60nm Si tunnel field effect transistors with Ion >100 µA/µm (2010) (20)
- Sub-50nm FinFET : PMOS (1999) (20)
- Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits (1994) (20)
- Plasma etching antenna effect on oxide-silicon interface reliability (1993) (20)
- Submicron CMOS thermal noise modeling from an RF perspective (1999) (20)
- MOSFETs with 9 to 13 A thick gate oxides (1999) (20)
- Threshold Vacuum Switch (TVS) on 3D-stackable and 4F2 cross-point bipolar and unipolar resistive random access memory (2012) (20)
- Design of FinFET SRAM Cells Using a Statistical Compact Model (2009) (20)
- A 65nm node strained SOI technology with slim spacer (2003) (20)
- A new bi-directional PMOSFET hot-carrier degradation model for circuit reliability simulation (1992) (19)
- Plasma Charging Damage On Ultra-thin Gate Oxides (1997) (19)
- Linearly graded doping drift region: A novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances (2002) (19)
- Full chip power benefits with negative capacitance FETs (2017) (19)
- Ultra-thin silicon-dioxide breakdown characteristics of MOS devices with n+and p+polysilicon gates (1987) (19)
- Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model (2015) (19)
- Charge-based core and the model architecture of BSIM5 (2005) (19)
- AC Charge Centroid Model For Quantization Of Inversion Layer In N-MOSFET (1997) (19)
- Air-Spacer MOSFET With Self-Aligned Contact for Future Dense Memories (2009) (19)
- High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response (2010) (19)
- Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits (2019) (19)
- Bulk FinFET With Low- $\kappa $ Spacers for Continued Scaling (2017) (19)
- Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport (2016) (18)
- SOI (Silicon-on-insulator) for high speed ultra large scale integration (1994) (18)
- Compact modeling of flicker noise variability in small size MOSFETs (2009) (18)
- Modeling the impact of back-end process variation on circuit performance (1999) (18)
- Reliability phenomena under AC stress (1998) (18)
- Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs (2015) (18)
- Observation of anti-Stokes fluorescence in organic dye solutions (1972) (18)
- Hot carrier reliability of n-MOSFET with ultra-thin HfO/sub 2/ gate dielectric and poly-Si gate (2002) (18)
- Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support (2015) (18)
- Intra-field gate CD variability and its impact on circuit performance (1999) (18)
- Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels (2012) (18)
- Arsenic‐implanted Si layers annealed using a cw Xe arc lamp (1981) (18)
- Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors (2020) (18)
- Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal–Oxide–Semiconductor Field-Effect Transistors (2016) (18)
- A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation (2003) (18)
- Thin‐film dye laser with etched cavity (1976) (18)
- On the body-source built-in potential lowering of SOI MOSFETs (2003) (17)
- Operation of CMOS devices with a floating well (1987) (17)
- Light Amplification in a Thin Film (1972) (17)
- Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs (2020) (17)
- Effects of Annealing on Ferroelectric Hafnium–Zirconium–Oxide-Based Transistor Technology (2019) (17)
- Interfacial layer reduction and high permittivity tetragonal ZrO2 on germanium reaching ultrathin 0.39 nm equivalent oxide thickness (2013) (17)
- Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS (2001) (17)
- Dynamic Threshold-Voltage MOSFET (1999) (17)
- MOSFET degradation due to stressing of thin oxide (1982) (17)
- Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft (2018) (17)
- SOI and nanoscale MOSFETs (2001) (17)
- Low power device technology with SiGe channel, HfSiON, and poly-Si gate (2004) (17)
- A Nitrided Interfacial Oxide for Interface State Improvement in Hafnium Zirconium Oxide-Based Ferroelectric Transistor Technology (2018) (17)
- MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability (2016) (17)
- Negative capacitance enables FinFET and FDSOI scaling to 2 nm node (2017) (17)
- A complete radiation reliability software simulator (1994) (16)
- Enhanced substrate current in SOI MOSFETs (2002) (16)
- Reverse short-channel effects and channel-engineering in deep-submicron MOSFETs: modeling and optimization (1996) (16)
- AC output conductance of SOI MOSFETs and impact on analog applications (1997) (16)
- Novel dual-metal gate technology using Mo-MoSi/sub x/ combination (2006) (16)
- Realistic worst-case SPICE file extraction using BSIM3 (1995) (16)
- Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel (2019) (16)
- Carrier recombination through donors/acceptors in heavily doped silicon (1979) (16)
- Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices (1999) (16)
- A Predictive Tunnel FET Compact Model With Atomistic Simulation Validation (2017) (16)
- Two-dimensional to three-dimensional tunneling in InAs/AlSb/GaSb quantum well heterojunctions (2013) (16)
- Comparison of short-channel effect and offstate leakage in symmetric vs. asymmetric double gate MOSFETs (2000) (16)
- Suppressing Non-Uniform Tunneling in InAs/GaSb TFET With Dual-Metal Gate (2016) (16)
- Global parameter extraction for a multi-gate MOSFETs compact model (2010) (16)
- Reliability of thin SiO/sub 2/ at direct-tunneling voltages (1994) (16)
- Improved a priori interconnect predictions and technology extrapolation in the GTX system (2003) (16)
- Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs (1993) (16)
- MOSFET scaling into the 10 nm regime (2000) (16)
- Multi-Gate MOSFET Compact Model BSIM-MG (2010) (16)
- Characterization and modeling of a highly reliable metal-to-metal antifuse for high-performance and high-density field-programmable gate arrays (1997) (16)
- Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications (2017) (15)
- An Advanced Surface-Potential-Plus MOSFET Model (2003) (15)
- Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG (2016) (15)
- Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology (1998) (15)
- Excess hot-carrier currents in SOI MOSFETs and its implications (2002) (15)
- Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectrics (2000) (15)
- A Physical and Scalable – Model in BSIM 3 v 3 for Analog / Digital Circuit Simulation (1998) (15)
- 0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology (1998) (15)
- Contact-pad design for high-frequency silicon measurements (2000) (15)
- Air spacer MOSFET technology for 20nm node and beyond (2008) (15)
- Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors (1997) (15)
- Punchthrough transient voltage suppressor for low-voltage electronics (1995) (15)
- Statistical Compact Modeling of Variations in Nano MOSFETs (2008) (15)
- Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μA/μm (2011) (15)
- Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node (2019) (15)
- Enhanced hot-carrier induced degradation in shallow trench isolated narrow channel PMOSFET's (1998) (15)
- A measurement-based charge sheet capacitance model of short-channel MOSFET's for SPICE (1986) (15)
- Circuit performance of double-gate SOI CMOS (2003) (15)
- A relaxation time approach to model the non-quasi-static transient effects in MOSFETs (1994) (14)
- Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors (2019) (14)
- 2D layered materials: From materials properties to device applications (2015) (14)
- Characterization of RF Noise in UTBB FD-SOI MOSFET (2016) (14)
- High endurance ultra-thin tunnel oxide for dynamic memory application (1995) (14)
- JVD silicon nitride as tunnel dielectric in p-channel flash memory (2002) (14)
- Temperature and current effects on small-geometry-contact resistance (1997) (14)
- The influence of substrate compensation on inter-electrode leakage and back-gating in GaAs MESFETs (1991) (14)
- New industry standard FinFET compact model for future technology nodes (2015) (14)
- Modeling of nonlinear thermal resistance in FinFETs (2016) (14)
- Comparison of GIDL in p/sup +/-poly PMOS and n/sup +/-poly PMOS devices (1996) (14)
- Investigation of self-heating phenomenon in small geometry vias using scanning Joule expansion microscopy (1999) (14)
- Role of electrode-induced oxygen vacancies in regulating polarization wake-up in ferroelectric capacitors (2020) (14)
- Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation (2019) (14)
- Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation (1992) (14)
- Saturation velocity and velocity overshoot of inversion layer electrons and holes (1994) (14)
- Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect (2017) (14)
- EFFECTS OF HIGH ELECTRIC FIELD TRANSIENTS ON THIN GATE OXIDE MOSFETs. (1987) (14)
- Hot-carrier degradation in bipolar transistors at 300 and 110 K-effect on BiCMOS inverter performance (1990) (13)
- A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6 (2012) (13)
- A Density Metric for Semiconductor Technology [Point of View] (2020) (13)
- Correlation between channel hot-electron degradation and radiation-induced interface trapping in MOS devices (1989) (13)
- Effect of Fluorine Incorporation on 1/f Noise of HfSiON FETs for Future Mixed-Signal CMOS (2006) (13)
- Field-realigned nematic-liquid-crystal optical waveguides (1974) (13)
- Velocity overshoot of electrons and holes in Si inversion layers (1997) (13)
- Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling (2000) (13)
- Efficient gate oxide defect screen for VLSI reliability (1994) (13)
- 60 nm planarized ultra-thin body solid phase epitaxy MOSFETs (2000) (13)
- A framework for generic physics based double-gate MOSFET modeling (2003) (13)
- Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation (1997) (13)
- Electron wavefunction penetration into gate dielectric and interface scattering-an alternative to surface roughness scattering model (2001) (13)
- BSIM6: Symmetric Bulk MOSFET Model (2012) (13)
- Modeling of small size MOSFETs with reverse short channel and narrow width effects for circuit simulation (1997) (13)
- Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits (2018) (13)
- Electromigration design rules for bidirectional current (1996) (13)
- Simulating process-induced gate oxide damage in circuits (1997) (12)
- Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs (2017) (12)
- Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition (2018) (12)
- Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing (2020) (12)
- Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut (1998) (12)
- New sub-20nm transistors — Why and how (2011) (12)
- 16nm functional 0.039µm2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate (2009) (12)
- Electromigration Challenges for Nanoscale Cu Wiring (2009) (12)
- 35nm CMOS FinFETs (2002) (12)
- SiON/Ta/sub 2/O/sub 5//TiN gate-stack transistor with 1.8 nm equivalent SiO/sub 2/ thickness (1998) (12)
- Simulating hot-carrier effects on circuit performance (1992) (12)
- Polysilicon gate depletion effect on IC performance (1995) (12)
- Current‐field characteristics of oxides grown from polycrystalline silicon (1979) (12)
- Impact of AlN Interfacial Dipole on Effective Work Function of Ni and Band Alignment of Ni/HfO2/In0.53Ga0.47As Gate-Stack (2015) (12)
- Nanoscale CMOS at low temperature: design, reliability, and scaling trend (2001) (12)
- A statistical performance simulation methodology for VLSI circuits (1998) (12)
- Complementary metal‐oxide‐silicon field‐effect transistors fabricated in 4‐MeV boron‐implanted silicon (1984) (12)
- Oxide Breakdown Model For Very Low Voltages (1993) (12)
- Electromigration characteristics of TiN barrier layer material (1995) (12)
- 3D FinFET and other sub-22nm transistors (2012) (12)
- Spice up your MOSFET modelling (2003) (12)
- Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling (2017) (12)
- The Enhancement of Gate-Induced-Drain-Leakage (gidl) Current in Soi Mosfet and its Impact on Soi Device Scaling (1992) (12)
- Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators (2019) (11)
- Thin gate oxide damage due to plasma processing (1996) (11)
- AC effects in IC reliability (1996) (11)
- Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs (2016) (11)
- 49.2: Invited Paper: A Transparent AMOLED with On‐cell Touch Function Driven by IGZO Thin‐Film Transistors (2011) (11)
- Normalized mutual integral difference method to extract threshold voltage of MOSFETs (2002) (11)
- Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling (2003) (11)
- Compact Model for Geometry Dependent Mobility in Nanosheet FETs (2020) (11)
- Modeling of Subsurface Leakage Current in Low $V_{\mathrm {TH}}$ Short Channel MOSFET at Accumulation Bias (2016) (11)
- Errors in threshold-voltage measurements of MOS transistors for dopant-profile determinations (1981) (11)
- Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology (2012) (11)
- Efficient generation of pre-silicon MOS model parameters for early circuit design (2001) (11)
- The prospect of process-induced charging damage in future thin gate oxides (1999) (11)
- Design analysis of thin-body silicide source/drain devices (2001) (11)
- SOI MOSFET thermal conductance and its geometry dependence (2000) (11)
- Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures (2021) (11)
- BSIM-IMG: Compact model for RF-SOI MOSFETs (2015) (11)
- Optical deflection in thin-film nematic-liquid-crystal waveguides (1974) (11)
- Molybdenum Gate Electrode Technology For Deep Sub-Micron CMOS Generations (2001) (11)
- Design Optimization Techniques in Nanosheet Transistor for RF Applications (2020) (11)
- Structure and Numerical Simulation of Field Effect Solar Cell (1996) (11)
- BSIM-IMG 102.8.0: independent multi-gate MOSFET compact model: technical manual (2016) (10)
- Impact of Nitrogen ( N ) Implantation into Polysilicon Gate on High-Performance Dual-Gate CMOS Transistors (1998) (10)
- In0.53Ga0.47As FinFET and GAA-FET With Remote-Plasma Treatment (2018) (10)
- A high speed SOI technology with 12 ps/18 ps gate delay operating at 5 V/1.5 V (1992) (10)
- 45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell (2004) (10)
- A non-quasistatic MOSFET model for SPICE (1987) (10)
- JVD silicon nitride as tunnel dielectric in p-channel flash memory (2002) (10)
- Noise modeling and characterization for 1.5-V 1.8-GHz SOI low-noise amplifier (2001) (10)
- Analytical performance models for RLC interconnects and application to clock optimization (2002) (10)
- Planarized Copper Interconnects by Selective Electroless Plating (1992) (10)
- Excess noise in GaAs avalanche photodiodes with thin multiplication regions (1997) (10)
- Fabrication of metal–oxide–semiconductor devices with extreme ultraviolet lithography (1996) (10)
- A 128K flash EEPROM using double polysilicon technology (1987) (10)
- SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity (1995) (10)
- ICM-an analytical inversion charge model for accurate modeling of thin gate oxide MOSFETs (1997) (10)
- Effects of substrate resistance on CMOS latchup holding voltages (1987) (10)
- Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs (2018) (10)
- Publisher Correction: Enhanced ferroelectricity in ultrathin films grown directly on silicon (2020) (10)
- Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET (2001) (10)
- Substrate resistance calculation for latchup modeling (1984) (10)
- Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric (2001) (10)
- A charge-conserving non-quasistatic MOSFET model for SPICE transient analysis (1988) (10)
- Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs (2019) (10)
- Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON (2008) (10)
- Threshold voltage shift by quantum confinement in ultra-thin body device (2001) (10)
- Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model (2017) (10)
- Ferroelectricity in HfO2 thin films as a function of Zr doping (2017) (9)
- Bias polarity dependent effects of P+floating gate EEPROMs (2004) (9)
- A comparative study of advanced MOSFET structures (1996) (9)
- RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology (2003) (9)
- Statistical circuit characterization for deep-submicron CMOS designs (1998) (9)
- New analysis of a high‐voltage vertical multijunction solar cell (1977) (9)
- Oscillations during inductive turn-off in rectifiers (1999) (9)
- Some issues of power MOSFETs (1982) (9)
- Compact models for sub-22nm MOSFETs (2011) (9)
- Correlation of electromigration lifetime distribution to failure mode in dual damascene Cu/SiLK interconnects (2003) (9)
- BSIM4 and BSIM Multi-Gate Progress (2006) (9)
- Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap (2016) (9)
- Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD (2002) (9)
- Spacer FinFET: nano-scale CMOS technology for the terabit era (2001) (9)
- Thermal analysis of the fusion limits of metal interconnect under short duration current pulses (1996) (9)
- Improvement of Charge Trapping Char act er is tics of N, 0- Annealed and Reoxidized N,O-Annealed Thin Oxides (1992) (9)
- The engineering of BSIM for the nano-technology era and beyond (2002) (9)
- 45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell (2004) (9)
- Copper Interconnect: Fabrication And Reliability (1997) (9)
- A full-process damage detection method using small MOSFET and protection diode (1996) (9)
- Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs (2011) (9)
- Effect of Polycrystallinity and Presence of Dielectric Phases on NC-FinFET Variability (2018) (9)
- Simulation of SOI devices and circuits using BSIM3SOI (1998) (9)
- Impact of HfSiON Induced Flicker Noise on Scaling of Future Mixed-Signal CMOS (2006) (9)
- Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs (1996) (8)
- MOSFET inversion layer capacitance model based on Fermi-Dirac statistics for wide temperature range (1997) (8)
- Flicker noise in advanced CMOS technology: Effects of halo implant (2013) (8)
- An investigation on the robustness, accuracy and simulation performance of a physics-based deep-submicronmeter BSIM model for analog/digital circuit simulation (1996) (8)
- Characteristics of field effect a-Si:H solar cells (1998) (8)
- Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling (2022) (8)
- A comprehensive study of Ge1−xSix on Ge for the Ge nMOSFETs with tensile stress, shallow junctions and reduced leakage (2009) (8)
- Improved Sub-micron Cmos Device Performance Due To Fluorine In Cvd Tungsten Silicide (1991) (8)
- Floating well CMOS and latchup (1985) (8)
- The operation of power MOSFET in reverse mode (1983) (8)
- Thermal Stability of Copper Contact Metallization Using Ru-Containing Liner (2011) (8)
- Characteristics of CMOS devices in high-energy boron-implanted substrates (1988) (8)
- Improved performance of ultra-thin HfO/sub 2/ CMOSFETs using poly-SiGe gate (2002) (8)
- Effect Of Impurity On Cu Electromigration (2010) (8)
- Plasma charging damage on ultrathin gate oxides (1998) (8)
- MOSFET saturation voltage (1994) (8)
- Tunnel FET-based pass-transistor logic for ultra-low-power applications (2011) (8)
- Modeling of direct tunneling current in multi-layer gate stacks (2003) (8)
- SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films (1995) (8)
- A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET (2020) (8)
- Small signal electron charge centroid model for quantization of inversion layer in a metal-on-insulator field-effect transistor (1998) (8)
- The next generation BSIM for sub-100nm mixed-signal circuit simulation (2004) (8)
- New Ti-SALICIDE Process Using Sb and Ge Preamorphization for Sub-0 . 2 m CMOS Technology (1998) (8)
- Charge transport and trapping model for scaled nitride-oxide stacked films (1987) (8)
- Normalized mutual integral difference method to extract threshold voltage of MOSFETs (2002) (8)
- Computer analysis on the collection of alpha-generated charge for reflecting and absorbing surface conditions around the collector (1984) (8)
- Evidence of hole direct tunneling through ultrathin gate oxide using P/sup +/ poly-SiGe gate (1999) (8)
- Deep-submicron CMOS process integration of HfO/sub 2/ gate dielectric with poly-si gate (2001) (7)
- Modeling and design study of nanocrystal memory devices (2001) (7)
- Methods for Extracting Flat Band Voltage in the InGaAs High Mobility Materials (2016) (7)
- (Invited) FinFET and UTB--How to Make Very Short Channel MOSFETs (2013) (7)
- Second breakdown of vertical power MOSFET's (1982) (7)
- Simulation of deep submicron SOI N-MOSFET considering the velocity overshoot effect (1995) (7)
- Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics (2003) (7)
- Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model (2017) (7)
- BSIM-IMG with improved surface potential calculation recipe (2014) (7)
- Fast Read-After-Write and Depolarization Fields in High Endurance n-Type Ferroelectric FETs (2022) (7)
- Optimization of epitaxial layers for power bipolar-MOS transistor (1986) (7)
- Next generation CMOS compact models for RF and microwave applications (2005) (7)
- Molybdenum Gate Work Function Engineering for Ultra-Thin-Body Silicon-on-Insulator (UTB SOI) MOSFETs (2003) (7)
- Bifacial CIGS (11% efficiency)/Si solar cells by Cd-free and sodium-free green process integrated with CIGS TFTs (2011) (7)
- Quasi-2D Compact Modeling for Double-Gate MOSFET (2004) (7)
- 3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration (2012) (7)
- Oxides grown on textured single‐crystal silicon for enhanced conduction (1988) (7)
- High-gain monolithic 3D CMOS inverter using layered semiconductors (2017) (7)
- Extraction of Front and Buried Oxide Interface Trap Densities in Fully Depleted Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor (2013) (7)
- An Analytical Crosstalk Model with Application to ULSI Interconnect Scaling (1998) (7)
- High Vth enhancement mode GaN power devices with high ID, max using hybrid ferroelectric charge trap gate stack (2017) (7)
- Modeling SiGe FinFETs With Thin Fin and Current-Dependent Source/Drain Resistance (2015) (7)
- SiON / Ta 2 O 5 / TiN Gate-Stack Transistor with 1 . 8 nm Equivalent SiO 2 Thickness (1998) (7)
- Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs (2016) (7)
- Modeling STI Edge Parasitic Current for Accurate Circuit Simulations (2015) (7)
- Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design (2002) (7)
- Characterization and modeling of electromigration failures in multilayered interconnects and barrier layer materials (1996) (7)
- Enhanced conductivity and breakdown of oxides grown on heavily implanted substrates (1991) (7)
- A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide (1999) (6)
- Scaling of CMOS FinFETs towards 10 nm (2003) (6)
- Device characteristics of mosfets in MeV implanted substrates (1987) (6)
- Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions (2002) (6)
- Predictive effective mobility model for FDSOI transistors using technology parameters (2016) (6)
- A Compact Quantum-Mechanical Model for Double-Gate MOSFET (2006) (6)
- van der Waals epitaxy of 2D h-AlN on TMDs by atomic layer deposition at 250 °C (2022) (6)
- Bipolar transistor degradation under dynamic hot carrier stress (1995) (6)
- Novel 140°C hybrid thin film solar cell/transistor technology with 9.6% conversion efficiency and 1.1 cm2/V-s electron mobility for low-temperature substrates (2010) (6)
- Analysis and modeling of capacitances in halo-implanted MOSFETs (2017) (6)
- A model of power transistor turn-off dynamics (1980) (6)
- A dynamic depletion SOI MOSFET model for SPICE (1998) (6)
- Statistical variation of NMOSFET hot-carrier lifetime and its impact on digital circuit reliability (1995) (6)
- BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design (2019) (6)
- Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation (2001) (6)
- ESD reliability and protection schemes in SOI CMOS output buffers (1995) (6)
- Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs (2016) (6)
- Accurate and Computationally Efficient Modeling of Nonquasi Static Effects in MOSFETs for Millimeter-Wave Applications (2019) (6)
- Correlating the channel, substrate, gate and minority-carrier currents in MOSFETs (1983) (6)
- Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits (1989) (6)
- Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology (1997) (6)
- Hot-carrier effect in ultra-thin-film (UTF) fully-depleted SOI MOSFETs (1996) (5)
- Modeling reverse short channel and narrow width effects in small size MOSFET's for circuit simulation (1997) (5)
- SPICE macro model for the simulation of zener diode current-voltage characteristics (1991) (5)
- Impacts of surface nitridation on crystalline ferroelectric phase of Hf1-xZrxO2 and ferroelectric FET performance (2021) (5)
- A resistive-gated IGFET tetrode (1971) (5)
- Modeling of threshold voltage for operating point using industry standard BSIM-IMG model (2016) (5)
- Reliability of Thin Si02 at Direct-Thnneling Voltages (1994) (5)
- Enabling circuit design using FinFETs through close ecosystem collaboration (2013) (5)
- Compact models for real device effects in FinFETs: Quantum-mechanical confinement and double junctions in FinFETs (2012) (5)
- BSIM-IMG: A Turnkey compact model for fully depleted technologies (2012) (5)
- Improved Modeling of Bulk Charge Effect for BSIM-BULK Model (2019) (5)
- Body-bias effect in SOI FinFET for low-power applications: Gate length dependence (2014) (5)
- The effects of vacuum spacer transistors between high performance and low stand-by power devices beyond 16nm (2010) (5)
- Investigation of Mo/Ti/AlN/HfO2 High-k Metal Gate Stack for Low Power Consumption InGaAs NMOS Device Application (2017) (5)
- Low-voltage green transistor using hetero-tunneling (2008) (5)
- Measurement of Electron and Hole Saturation Velocities in Silicon Inversion Layers Using Soi Mosfets (1992) (5)
- Reduce IC power consumption by >10x with a green transistor? (2009) (5)
- An Impact Ionization Model for SO1 Circuit Simulation (2002) (5)
- Temperature effects on MOSFET driving capability and voltage gain (1996) (5)
- Compact Modeling for RF and Microwave Integrated Circuits (2003) (5)
- Polycrystalline silicon/metal stacked gate for threshold voltage control in metal–oxide–semiconductor field-effect transistors (2000) (5)
- Modeling of high voltage LDMOSFET using industry standard BSIM6 MOS model (2016) (5)
- Device and technology optimizations for low power design in deep sub-micron regime (1997) (5)
- Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology (1997) (5)
- BSIM3 MOSFET model accuracy for RF circuit simulation (1998) (5)
- A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication (2011) (5)
- Industry Standard FDSOI Compact Model BSIM-IMG for IC Design (2019) (5)
- Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations (2011) (5)
- Observation of Reduced Boron Penetration and Gate Depletion for Poly-Si Ge Gated PMOS Devices (1999) (5)
- Temperature Effects of the Inversion Layer Electron and Hole Mobility of MOSFETs from 85K to 500K (1993) (5)
- Enhanced ion implantation charging damage on thin gate oxide due to photoresist (1996) (5)
- New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs (2018) (5)
- Investigation of Poly-Si 1 x Ge x for Dual-Gate CMOS Technology (1998) (5)
- Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance (2000) (5)
- RETRACTED: Normalized mutual integral difference operator: a novel experimental method for extracting threshold voltage of MOSFETs (2002) (4)
- A Compact Model of Polycrystalline Ferroelectric Capacitor (2021) (4)
- Non-volatile memory device with true CMOS compatibility (1999) (4)
- On gate leakage current partition for MOSFET compact model (2006) (4)
- Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET (2018) (4)
- Deep Learning-Based BSIM-CMG Parameter Extraction for 10-nm FinFET (2022) (4)
- Visualizing Ferroelectric Uniformity of Hf1-xZrxO2 Films Using X-ray Mapping. (2021) (4)
- A physics-based analytical surface potential and capacitance model of MOSFET's operation from accumulation to depletion region (2003) (4)
- Device-circuit mixed simulation of VDMOS charge transients (1991) (4)
- Thin dielectric degradation during silicon selective epitaxial growth process (1995) (4)
- Negative capacitance enables GAA scaling VDD to 0.5 V (2021) (4)
- A full-process damage detection method using small MOSFET and protection diode (1996) (4)
- Drift collection of alpha generated carriers and design implications (1982) (4)
- Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics (2001) (4)
- Ultra Thin Body Silicon-On-Insulator (UTB SOI) MOSFET with Metal Gate Work-function Engineering for sub-70 nm Technology Node (2002) (4)
- Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity (2020) (4)
- Optimum doping profile of power MOSFET epitaxial layer (1982) (4)
- High current effects in silicide films for sub-0.25 μm VLSI technologies (1998) (4)
- A Compact Model of Metal–Ferroelectric-Insulator–Semiconductor Tunnel Junction (2022) (4)
- Simulating total-dose radiation effects on circuit behavior (1994) (4)
- Present Status and Future Direction of BSIM SOI Model for High- Performance/Low-Power/RF Application (2001) (4)
- Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design (2015) (4)
- Engineering Hf0.5Zr0.5O2 Ferroelectric/Anti- Ferroelectric Phases With Oxygen Vacancy and Interface Energy Achieving High Remanent Polarization and Dielectric Constants (2022) (4)
- Experimental studies on deep submicron CMOS scaling (1998) (4)
- A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices (2002) (4)
- Denser and more stable FinFET SRAM using multiple fin heights (2011) (4)
- 45nm Node Planar-SO1 Technology with 0.296pm2 6T-SUM Cell (2004) (4)
- Investigation of Multilayer TiNi Alloys as the Gate Metal for nMOS In0.53Ga0.47As (2016) (4)
- Channel width effect on MOSFET breakdown (1992) (4)
- Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects (1997) (4)
- Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model (2016) (4)
- Tendency for full depletion due to gate tunneling current (2002) (4)
- An exercise of ET/UTBB SOI CMOS modeling and simulation with BSIM-IMG (2011) (4)
- Low-pressure chemical vapor deposited oxide process for MOS device application. (1988) (4)
- Punchthrough transient voltage suppressor for EOS/ESD protection of low-voltage IC's (1995) (4)
- A Unified BSIM I-V Model for Circuit Simulation (1995) (4)
- Physical origin of SILC and noisy breakdown in very thin silicon nitride gate dielectric (2001) (4)
- Negative Capacitance Enables FinFET Scaling Beyond 3nm Node (2020) (4)
- Optical second‐harmonic reflection from polycrystalline silicon and its relation to grain boundaries (1994) (4)
- Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET (2021) (4)
- Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates (1989) (3)
- Observation of Reduced Poly‐Gate Depletion Effect for Poly ‐ Si0.8Ge0.2 ‐ Gated NMOS Devices (1999) (3)
- Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation (2018) (3)
- Hot carrier reliability considerations for low Vdd CMOS technology (1995) (3)
- Hot-carrier currents of SOI MOSFETs (1993) (3)
- Optimization of epitaxial layers for power bipolar-MOS transistor (1986) (3)
- Effect of substrate contact on ESD failure of advanced CMOS integrated circuits (1993) (3)
- Formation of silicon on insulator (SOI) with separation by plasma implantation of oxygen (SPIMOX) (1994) (3)
- Robust Compact Model of High-Voltage MOSFET’s Drift Region (2023) (3)
- Scaling CMOS devices through alternative structures (2007) (3)
- Dual Work Function Metal Gate CMOS Transistors (2002) (3)
- GaAs MESFET model for circuit simulation (1989) (3)
- CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30×40 cm2 glass panels for self powered electronics (2012) (3)
- Tunneling through multi-layer gate dielectrics - an analytical model (2002) (3)
- A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications (2016) (3)
- Overestimation of oxide defects density in large test capacitors due to plasma processing (1997) (3)
- Suppressing Flash EEPROM Erase Leakage With Negative Gate Bias And LDD Erase Junction (1993) (3)
- Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies (2003) (3)
- Modeling independent multi-gate MOSFETs (2016) (3)
- Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET (2020) (3)
- Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET (2020) (3)
- Electromigration failures under bidirectional current stress (1998) (3)
- BSIM—making the first international standard MOSFET model (2008) (3)
- Two experimental methods to characterize load capacitance of a CMOS gate (1998) (3)
- Correction to "Determination of nonuniform diffusion length and electric field in semiconductors" (1978) (3)
- High performance bulk MOSFET fabricated on SOI substrate for ESD protection and circuit applications (1994) (3)
- A versatile multi-gate MOSFET compact model: BSIM-MG (2007) (3)
- Toward 44% switching energy reduction for FinFETs with vacuum gate spacer (2012) (3)
- Electron trapping in oxide grown from polycrystalline silicon (1979) (3)
- Characterization of Mos Structures with Ultra-Thin Tunneling Oxynitride (1995) (3)
- A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect (2018) (3)
- The operation of power MOSFET in reverse mode (1983) (3)
- Effects of the field-edge transistor on SOI MOSFETs (1991) (3)
- Cycling induced degradation of a 65nm FPGA flash memory switch (2010) (3)
- High field-effect performance and intrinsic scattering in the two-dimensional MoS2 semiconductors (2021) (3)
- Electrical Characteristics of MOSFET's Using Low-Pressure Chemical-Vapor-Deposited (1988) (3)
- Silicon-on-Insulator for High Speed ULSI (1993) (3)
- Accurate models for CMOS scaling and gate delay in deep sub-micron regime (1997) (3)
- PLASMA CHARGING DAMAGE DURING OVER-ETCH TIME OF ALUMINUM (1998) (3)
- Electromigration characteristics of Al/W via contact under unidirectional and bidirectional current conditions (1991) (2)
- Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs (2020) (2)
- Deep-Trap Stress Induced Leakage Current Model for Nominal and Weak Oxides (2008) (2)
- Liquid crystals in integrated optics (1973) (2)
- Effective Charge Modification Between SiO2 and Silicon (1989) (2)
- Distortion simulation of 90 nm nMOSFET for RF applications (2001) (2)
- Quantitative analysis of SILCs (stress-induced leakage currents) based on the inelastic trap-assisted tunneling model (1999) (2)
- Neural Network-Based and Modeling With High Accuracy and Potential Model Speed (2022) (2)
- Modeling of Nonlinear Thermal Resistance in FinFET (2015) (2)
- An accurate non-quasistatic MOSFET model for simulation of RF and high speed circuits (2000) (2)
- Visualizing correlation between carrier mobility and defect density in MoS2 FET (2022) (2)
- Thin gate oxides promise high reliability (1998) (2)
- Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs (2014) (2)
- Simulating radiation reliability with BERT (1995) (2)
- Measurement-Based Interconnect Capacitance Characterization for Circuit Simulations (1998) (2)
- Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices (1999) (2)
- Modeling off-state leakage current of DG-SOI MOSFETs for low-voltage design (1996) (2)
- Analysis and modeling of low frequency noise in presence of doping non-uniformity in MOSFETs (2016) (2)
- Field-dependent light scattering in nematic liquid crystals (1976) (2)
- Field-E ff ect Transistors Built from All Two-DimensionalMaterialComponents (2014) (2)
- Low-voltage, fast-programming P-channel flash memory with JVD tunneling nitride (2001) (2)
- Ferroelectric Si-doped HfO2 Capacitors for Next-Generation Memories (2019) (2)
- InGaAs FinFET modeling using industry standard compact model BSIM-CMG (2014) (2)
- Anomalous Subthreshold Behaviors in Negative Capacitance Transistors (2020) (2)
- Reverse antenna effect due to process-induced quasi-breakdown of gate oxide (1996) (2)
- Recent Developments in BSIM for CMOS RF ac and Noise Modeling (1999) (2)
- BSIM-CG: A compact model of cylindrical gate / nanowire MOSFETs for circuit simulations (2011) (2)
- A p-v-n diode model for CMOS latchup (1991) (2)
- BSIM and IC Simulation (2011) (2)
- Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs (2017) (2)
- Compact modeling for the changing transistor (2013) (2)
- Vacuum-sheath interconnect structure for dense memory (2009) (2)
- UTBSOI MOSFET with corner spacers for energy-efficient applications (2018) (2)
- Analysis of silicon solar cells with stripe geometry junctions (1977) (2)
- Dual Work Function Metal Gate Technology for Future CMOS Devices (2002) (2)
- Schottky barrier free NiSi/Si junction technology by Yb-implantation for 1xnm CMOS applications (2013) (2)
- Gate last MOSFET with air spacer and self-aligned contacts for dense memories (2009) (2)
- Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors (2021) (2)
- Extremely scaled ultra-thin-body and finfet CMOS devices (2003) (2)
- Two Silicon Nitride Technologies for Post (2001) (2)
- Compact Device Models for FinFET and Beyond (2020) (2)
- Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs (2019) (2)
- Dynamic Behavior Model for High-k MOSFETs (2006) (2)
- Direct tunneling RAM (DT-RAM) for high-density memory applications (2003) (2)
- Modeling electromigration lifetime under pulsed and AC current stress (1993) (2)
- A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS2 FET (2016) (2)
- Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation (1998) (2)
- odeling and Characterization of Electro (1996) (2)
- Interface characterization of fully-depleted SOI MOSFET by a subthreshold I-V method (1994) (2)
- Deep Sub-Micron, Bipolar-Mos Hybrid Transistors Fabricated on Simox (1992) (2)
- Modeling Short-channel Effects Of Cmosfet's Taking Account For Channel-engineering, Defect-enhanced-diffusion And Gate-depletion (1997) (2)
- Critical Importance of Nonuniform Polarization and Fringe Field Effects for Scaled Ferroelectric FinFET Memory (2022) (1)
- Approaches and options for modeling sub-0.1 /spl mu/m CMOS devices (2002) (1)
- Energy Storage and Reuse in Negative Capacitance (2021) (1)
- Compact Modeling for New Transistor Structures (2007) (1)
- Gate Engineering for (1998) (1)
- A Low-Barrier Body-Contact Scheme for SOI MOSFETs to Eliminate the Floating Body Effect (1993) (1)
- Non-quasistatic modeling of the BJT quasi-neutral base (1993) (1)
- Molecular beam epitaxy growth of resonant‐cavity separate‐absorption‐and‐multiplication avalanche photodiodes (1996) (1)
- Hot-carrier induced degradation of critical paths modeled by rule-based analysis (1995) (1)
- Analysis of latch-up holding voltage for shallow trench CMOS (1986) (1)
- Frequency Dependence of Capacitance Measurement for Advanced Gate Dielectrics (2002) (1)
- Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performancess (2010) (1)
- BSIM4 and MOSFET modeling for IC simulation : theory and engineering of MOSFET modeling for IC simulation (2011) (1)
- BERT- Circuit Oxide Reliability Simulator (CORS) (1990) (1)
- A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient (1996) (1)
- Write Disturb-Free Ferroelectric FETs With Non-Accumulative Switching Dynamics (2022) (1)
- Symmetry realization of BSIM model with dynamic reference method for circuit simulation (2002) (1)
- S-Curve Engineering for ON-State Performance Using Anti-Ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET (2021) (1)
- Computer analysis of the significance of surface boundary conditions on the collection of α-induced charge (1983) (1)
- New CMOS devices and compact modeling (2007) (1)
- Nanometer circuit performance analysis: device and interconnect (2002) (1)
- A Versatile, SO4 BiCMOS Technology with Complenientary Lateral B JT's (1992) (1)
- Modeling of a MOSFET's parasitic resistance's narrow width and body bias effects for an IC simulator (1996) (1)
- Complementary, High-Performance Lateral Bjts in a Simox C-Bicmos Technology (1992) (1)
- Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density (2012) (1)
- Quarter-micrometre surface and buried channel PMOSFET modelling for circuit simulation (1996) (1)
- Electromigration Reliability in Nanoscale Cu Interconnects (2007) (1)
- Field effect solar cell (2008) (1)
- Model for photo-induced long-term drain current transients in GaAs MESFETs (1990) (1)
- Sub-fM DNA sensitivity by self-aligned maskless thin-film transistor-based SoC bioelectronics (2012) (1)
- BSIM — Industry standard compact MOSFET models (2012) (1)
- Optimized poly-Si/sub 1-x/Ge/sub x/-gate technology for dual gate CMOS application (1998) (1)
- User verify and disturb mechanisms in a 65nm flash FPGA (2011) (1)
- Ferroelectric HfO$_2$ Memory Transistors with High-$\kappa$ Interfacial Layer and Write Endurance Exceeding $10^{10}$ Cycles (2021) (1)
- Scaling cmos memories (2002) (1)
- Transistor Characteristics with TaO Gate Dielectric (1998) (1)
- An exact analytic model of undoped body MOSFETs using the SPP approach (2004) (1)
- Impact of channel doping on the device and NBTI performance in FinFETs for low power applications (2014) (1)
- A Compact Model of Antiferroelectric Capacitor (2022) (1)
- Electrical characterization of inversion layer carrier profile in deep-submicron p-MOSFETs (1997) (1)
- Determination of Carrier Lifetime Ramp Recovery Waveform (1988) (1)
- BSIM-CMG Compact Model for IC CAD: from FinFET to Gate-All-Around FET Technology (2020) (1)
- Comparison of Ni-Metal Induced Lateral Crystallization Thin-Film Transistors Fabricated by Rapid Thermal Annealing and Conventional Furnace Annealing at 565 °C (2007) (1)
- An Extension Of BSIM3 Model Incorporating Velocity Overshoot (1997) (1)
- EUV degradation of high performance Ge MOSFETs (2013) (1)
- Electromigration Performance of Electroless Plated Copper (1992) (1)
- Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits (2021) (1)
- Hot-carrier effects in depletion-mode MOSFETs (1989) (1)
- Room temperature observation of velocity overshoot in silicon inversion layers (1993) (1)
- Statistical models, methods, and algorithms for computer-aided design for manufacturing (2001) (1)
- LED charge-control model and speed at high currents (1978) (1)
- Interfacial charge modification between SiO2 and silicon (1989) (1)
- Competitive Oxidation During Buried Oxide Formation Using Separation by Plasma Implantation of Oxygen (Spimox) (1995) (1)
- Unified compact model for gate all around fets-nanosheets, nanowires, multi bridge channel MOSFETs (2018) (1)
- Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET (2019) (1)
- Quasi-2 D Compact Modeling for Double-Gate MOSFET (2004) (1)
- SOI MOSFET on low cost SPIMOX substrate (1998) (0)
- Modeling CMOS Non-Quasi-Static Effects in a Quasi-Static Simulation Engine (2004) (0)
- A Compact Model of Nanoscale Ferroelectric Capacitor (2022) (0)
- Invited Paper Gate Oxide Scaling Limits and Projection (1996) (0)
- Reliability Issues of MOS and Bipolar ICs (Invited Paper) (1989) (0)
- Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC (2019) (0)
- Performance enhancement in deep-submicron poly-SiGe-gated CMOS devices (1999) (0)
- Hybrid CIS/Si near-IR sensor and 16% PV energy-harvesting technology (2012) (0)
- ccelerated Testing of Si02 Reliability (1996) (0)
- Annual Grant Progress Report (FDP) for Contract N00014-92-J-1757 (University of California) (1993) (0)
- Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs (2023) (0)
- Advanced Silicon FET Physics and Device Structures (1998) (0)
- Reliability and Scaling of Thin Gate Oxide (1997) (0)
- Improved MOSFET electron mobility model for advanced gate dielectric stacks (2002) (0)
- A Comparison of Cw Laser and Electron-Beam Recrystallization of Polysilicon in Multilayer Structures (1982) (0)
- Enabling circuit design using FinFETs through close ecosystem collaboration (2013) (0)
- Linear cofactor difference extrema of MOSFET's drain current and their application in parameter extraction (2004) (0)
- Core Model for Independent Multigate MOSFETs (2019) (0)
- A novel self-aligned punchthrough implant: A simulation study (1996) (0)
- Paths to energy efficient ICs (2010) (0)
- Operational phase-space of separation by plasma implantation of oxygen (SPIMOX) (1996) (0)
- Compact Model for Trap Assisted Tunneling based GIDL (2022) (0)
- Publisher's Note: "Differential voltage amplification from ferroelectric negative capacitance" [Appl. Phys. Lett. 111, 253501 (2017)] (2018) (0)
- Challenges in Compact Modeling for RF and Microwave Applications (2005) (0)
- Invited Paper SO1 and Device Scaling (1998) (0)
- Extremely Scaled FinFETs and Ultra-Thin Body SOI CMOS Devices (2003) (0)
- SUBMICRON DEVICE RELIABILITY RESEARCH (1989) (0)
- Multi-Gate Transistor Model (2011) (0)
- Stressor design for FinFETs with air-gap spacers (2017) (0)
- JSEP Augmentation Proposal: Velocity Overshoot in Silicon Inversion Layer (1997) (0)
- High performance 0.1 /spl mu/m PD SOI tunneling-biased MOSFETs (TBMOS) (2001) (0)
- A Study of Deep-submicron MOSFET Technology Prediction and Scaling with BSIM3 (1996) (0)
- High temperature and extended endurance characteristics of EEROM (1983) (0)
- Non-Quasi-Static and Parasitic Gate and Body Resistances (2011) (0)
- GaN versus SiC versus Superjunction power devices (2019) (0)
- MOTIONS OF 2D BODIES AT SMALL FORWARD SPEED (1990) (0)
- A novel SOI CBiCMOS compatible device structure for analog and mixed-mode circuits (1995) (0)
- IC RELIABILITY SIMULATION (Invited Paper) (1991) (0)
- WATER PLASMA §IS OF BURIED OXIDE BY PLASMA IMPLANTATION WITH OXYGEN AND (1995) (0)
- Durchbruchtransierter low-voltage-suppressor with two-layer base (1996) (0)
- Crystal-Orientation-Tolerant Voltage Regulator using Monolithic 3D BEOL FinFETs in Single-Crystal Islands for On-Chip Power Delivery Network (2020) (0)
- Research in VLSI Reliability. (1986) (0)
- Dram gets no Capacity on silicon-on-insulator substrate (1994) (0)
- Hot-Electron-Induced Traps Studied Through (1991) (0)
- A Compact Model of Ferroelectric Field-Effect Transistor (2022) (0)
- Retraction notice to "Normalized mutual integral difference operator: A novel experimental method for extracting threshold voltage of MOSFETs" [Microelectronics Journal 33 (2002) 667-670] (2010) (0)
- First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro (2020) (0)
- Tunneling current through MIS structures with ultra-thin insulators (1996) (0)
- Charge and Capacitance Models (2011) (0)
- Circuit Reliability Simulation (1995) (0)
- Compact Modeling for the Changing Transistor (Plenary Paper) (2013) (0)
- A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin (2013) (0)
- Hot-Carrier Reliability of 0.1 μm Delta-Doped MOSFETs (1995) (0)
- Elimination of stress induced oxide leakage in textured tunneling oxide (1992) (0)
- A Comparative Study of High-Field Endurance for Reoxidized-Nitrided and Fluorinated Oxides (1991) (0)
- Surface-potential-plus approach for next generation CMOS device modeling (2004) (0)
- Analysis of Floating Body Effect in Non-fully Depleted SOI MOSFETs based on Capacitive Coupling (1997) (0)
- A compact model for rapidly shrinking MOSFETs (2001) (0)
- Oxide implantation for threshold voltage control (1990) (0)
- Fully-Depleted Silicon on Oxide Transistor and Compact Model (2019) (0)
- Simulation of 2-Dimensional Hole Gas for PMOS Devices with Phosphorus Pile-Up (1997) (0)
- MOSFET Carrier Mobility Model Based on the Density-of-State at the DC-Centroid in the Quantized Inversion Layer (1997) (0)
- The Next Generation BSIM Model Extending from Conventional to Double-Gate MOSFETs (2004) (0)
- THIN OXIDE RELIABILITY (Invited Paper) (1985) (0)
- A Programmable Control System for Small Radio Telescope Dishes (1988) (0)
- Novel Ti-SALICIDE process with low resistivity for sub-0.2 /spl mu/m CMOS technology (1998) (0)
- 3D-CMOS-TMDs AdvancedMaterials-2016-SI (2016) (0)
- Channel DC Current and Output Resistance (2011) (0)
- Atomic-scale ferroic HfO 2-ZrO 2 superlattice gate stack for 1 advanced transistors 2 (2021) (0)
- Impact of Al content on InAs/AlSb/Al x Ga1−x Sb tunnelling diode (2017) (0)
- Impact of Al content on InAs/AlSb/Al<i><sub>x</sub></i> Ga<sub>1â‹TM<i>x</i></sub> Sb tunnelling diode (2020) (0)
- Drift collection of alpha generated carriers and design implications (1982) (0)
- Air-spacer Self-Aligned Contact MOSFET for future dense memories (2008) (0)
- FinFET--How to Make a Very Short Channel MOSFET (2012) (0)
- Residential time-of-use kilowatthour meter (1986) (0)
- Field-dependent light scattering in nematic liquid crystals (1976) (0)
- Simulating hot-carrier effects on circuit performance (1992) (0)
- High sensitivity DNA sieving technology by entropic trapping in 3D artificial nano-channel matrices (2013) (0)
- Electrooptic modulation in grain-oriented ZnO films (1975) (0)
- Electrooptic modulation in grain-oriented ZnO films (1975) (0)
- On Integrating a Polycide-ONO-Poly Capacitor into a 0.8㎛ Digital Technology for Mixed-Signal ASICs (1993) (0)
- A model of CMOS gate delay and projection of future trend (1996) (0)
- Introductory invited paper The prospect of process-induced charging damage in future thin gate oxides (1999) (0)
- Characterization of Global Inversion Layer in Thin-Gate-Oxide Deep-Submicron p-MOSFETs (1998) (0)
- The Impact of Line Edge Roughness on lOOnm MOSFET Devices (2017) (0)
- MOS memory using germanium nanocrystals formed by thermal oxidation of Si/sub 1-x/Ge/sub x/ (1998) (0)
- SPICE Implementation Example: The Methodology with BSIM4 Transient NQS (2011) (0)
- Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs (2022) (0)
- Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology (1998) (0)
- Fundamental MOSFET Physical Effects and Their Models for BSIM4 (2011) (0)
- Reliability of thin SiO2 (1994) (0)
- A Simple Method for Analyzing Bulk Versus Surface Punchthrough Current (1993) (0)
- A novel bottom-up Ag contact (30nm diameter and 6.5 aspect ratio) technology by electroplating for 1Xnm and beyond technology (2011) (0)
- The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films (1987) (0)
- Novel Strained-Si Substrate Technology for Transistor Performance Enhancement (2002) (0)
- High Performance 0.1 pm PD SO1 Tunneling-Biased MOSFETs (TBMOS) (2000) (0)
- Studies of Coulomb Blockade , Single-Trangister Dynamic Memory , and Oxide Trap Charge State Based on the Random Telegraph Noise Modeling (1997) (0)
- Low-Input-Harmonics Power Supplies. (1982) (0)
- Optimization of Deep Learning-Based BSIM-CMG I-V Parameter Extraction in Seconds (2022) (0)
- New Method of Extracting Inversion Layer Thickness and Charge Profile and Its Impact on Scaled MOSFETs (1996) (0)
- Determination of nonuniform diffusion length and electric field in semiconductors (1978) (0)
- Monitoring Plasma-Process Induced Damage in (1993) (0)
- Dc electrical oxide thickness model for quantization of the inversion layer in MOSFETs (1998) (0)
- Two experimental methods to characterize load capacitance of a CMOS gate (1998) (0)
- Silicon nanoelectronics for the 21st century (1999) (0)
- Hot-carrier reliability of p-MOSFET with ultra-thin silicon nitride gate dielectric (2001) (0)
- Junction Diode IV and CV Models (2011) (0)
- Silicide barrier engineering induced random telegraph noise in 1Xnm CMOS contacts (2011) (0)
- P 4-7 tr ' requency Dependence of Capacitance Measurement for Advanced Gate Dielectrics (2008) (0)
- Gate Direct-Tunneling and Body Currents (2011) (0)
- LED charge-control model and speed at high currents (1978) (0)
- Quarter-micrometre surface and buried channel PMOSFET modelling for circuit simulation (1996) (0)
- SESSION I: DEVICE MODELING AND CHARACTERIZATION (1981) (0)
- VLSI Reliability Research (1992) (0)
- Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models (1996) (0)
- Design of Negative Capacitance Field-Effect Transistor (2020) (0)
- Experimental and analytical studies on CMOS scaling in deep submicron regime including quantum and polysilicon gate depletion effects (1997) (0)
- Dual work function metal gate CMOS transistors fabricated by Ni-Ti interdiffusion (2001) (0)
- Nanoscale SiGe-Channel Ultra-Thin-Body Silicon-on-Insulator P-MOSFETs (1999) (0)
- Source and Drain Parasitics: Layout-Dependence Model (2011) (0)
- Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances (2002) (0)
- Scaling limit of silicon nitride gate dielectric for future CMOS technologies (2000) (0)
- Analytical surface-potential calculation in UTBSOI MOSFETs with independent back-gate control (2012) (0)
- Compact Modeling of Impact Ionization in High-Voltage Devices (2023) (0)
- A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation (1997) (0)
- Ge Single-Crystal-Island (Ge-SCI) Technique and BEOL Ge FinFET Switch Arrays on Top of Si Circuits for Monolithic 3D Voltage Regulators (2021) (0)
- Optimizing the Ferroelectric Properties of Hf1–xZrxO2 Films via Crystal Orientation (2023) (0)
- Toward Perfect Surfaces of Transition Metal Dichalcogenides with Ion Bombardment and Annealing Treatment. (2023) (0)
- Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode (2022) (0)
- On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs (2022) (0)
- Comprehensive High-Voltage Parameter Extraction Strategy for BSIM-BULK HV Model (2023) (0)
- Publisher Correction: Enhanced ferroelectricity in ultrathin films grown directly on silicon (2020) (0)
- An Improved Robust Infinitely Differentiable Drift Resistance Model for BSIM High Voltage Compact Model (2023) (0)
- Neural Network-Based $\textit{I}$–$\textit{V}$ and $\textit{C}$–$\textit{V}$ Modeling With High Accuracy and Potential Model Speed (2022) (0)
- Spatially resolved steady-state negative capacitance (2019) (0)
- Enhanced ferroelectricity in ultrathin films grown directly on silicon (2020) (0)
- Neural Network-Based BSIM Transistor Model Framework: Currents, Charges, Variability, and Circuit Simulation (2023) (0)
- Plasma Charging Damage on Ultrathin Gate Oxides Donggun Park and Chenming Hu (1998) (0)
This paper list is powered by the following services:
Other Resources About Chenming Hu
What Schools Are Affiliated With Chenming Hu?
Chenming Hu is affiliated with the following schools:
