Chih-Kong Ken Yang
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Chih-Kong Ken Yang's AcademicInfluence.com Rankings
Chih-Kong Ken Yangengineering Degrees
Engineering
#4806
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#6027
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Electrical Engineering
#1757
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#1856
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Applied Physics
#3295
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#3379
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Engineering
Chih-Kong Ken Yang's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Chih-Kong Ken Yang Influential?
(Suggest an Edit or Addition)According to Wikipedia, Chih-Kong Ken Yang is a professor of electrical engineering at the University of California, Los Angeles , Director of the Integrated Circuits and Systems Laboratories , and co-founder of Pluribus Networks, Inc.
Chih-Kong Ken Yang's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- High-speed electrical signaling: overview and limitations (1998) (208)
- Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops (2002) (186)
- A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling (1998) (155)
- A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver (2000) (139)
- Jitter optimization based on phase-locked loop design parameters (2002) (129)
- A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation (2003) (110)
- Offset compensation in comparators with minimum input-referred supply noise (2004) (109)
- A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter (1998) (103)
- A 27-mW 3.6-gb/s I/O transceiver (2004) (95)
- A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter (1999) (93)
- Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs (2012) (89)
- A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE (2007) (81)
- A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 /spl mu/m CMOS (2001) (75)
- A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links (1996) (74)
- Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies (2007) (60)
- Power Optimized ADC-Based Serial Link Receiver (2012) (57)
- Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric (2008) (50)
- A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation (1999) (48)
- A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning (2011) (47)
- Edge and Data Adaptive Equalization of Serial-Link Transceivers (2008) (43)
- ADC-based serial I/O receivers (2009) (42)
- A 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection (2013) (41)
- A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization (2009) (39)
- A Comprehensive Delay Model for CMOS CML Circuits (2008) (39)
- A 10-mW 3.6-Gbps I/O transmitter (2003) (39)
- A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions (2007) (36)
- Design of high-speed serial links in CMOS (1998) (35)
- A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS (2013) (33)
- A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology (2015) (33)
- Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages (2009) (32)
- Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming (2010) (30)
- Design and Optimization of Multipath Ring Oscillators (2011) (30)
- A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs) (2012) (30)
- Power-centric design of high-speed I/Os (2006) (28)
- 23.8 A 34V charge pump in 65nm bulk CMOS technology (2014) (27)
- Precursor ISI Reduction in High-Speed I/O (2007) (27)
- A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration (2006) (26)
- A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology (2015) (26)
- Multilevel Power Optimization of Pipelined A/D Converters (2011) (25)
- A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications (2004) (23)
- Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links (2011) (20)
- A 0.6m CMOS 4Gb/s Transceiver With Data Recovery Using Oversampling (1997) (20)
- A Cmos 500 Mbps/pin Synchronous Point to Point Link Interface (1994) (20)
- Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs (2013) (20)
- A Serial-Link Transceiver with Transition Equalization (2006) (19)
- A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology (2010) (19)
- A low-power low-jitter adaptive-bandwidth PLL and clock buffer (2003) (19)
- Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors (2013) (18)
- Methodology for on-chip adaptive jitter minimization in phase-locked loops (2003) (17)
- A Study of the Optimal Data Rate for Minimum Power of I/Os (2006) (15)
- A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology (2017) (15)
- A Comprehensive Phase-Transfer Model for Delay-Locked Loops (2007) (14)
- A sub-10-ps multiphase sampling system using redundancy (2006) (14)
- Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators (2013) (13)
- Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression (2014) (13)
- Power analysis for high-speed I/O transmitters (2004) (13)
- Circuit-Level Performance Evaluation of Schottky Tunneling Transistor in Mixed-Signal Applications (2011) (11)
- A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter (2006) (10)
- A low-power highly multiplexed parallel PRBS generator (2012) (10)
- A sub-10ps multi-phase sampling system using redundancy (2005) (10)
- 10Gb/s serial I/O receiver based on variable reference ADC (2011) (9)
- Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage (2008) (9)
- Adaptive low-jitter LC-based clock distribution (2007) (9)
- Energy-Performance Characterization of CMOS / Magnetic Tunnel Junction ( MTJ ) Hybrid Logic Circuits (2011) (9)
- Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs (2007) (9)
- A Large-Swing Transformer-Boosted Serial Link Transmitter With $>{\rm V}_{\rm DD}$ Swing (2007) (8)
- Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters (2014) (8)
- Evaluation of fully-integrated switching regulators for CMOS process technologies (2003) (8)
- Analysis of STT-RAM cell design with multiple MTJs per access (2011) (7)
- A multi-phase multi-frequency clock generator using superharmonic injection locked multipath ring oscillators as frequency dividers (2012) (7)
- Scalability and design-space analysis of a 1T-1MTJ memory cell (2011) (7)
- Device-circuit co-optimization for mixed-mode circuit design via geometric programming (2007) (6)
- A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS (2014) (6)
- A 12-V charge pump-based square wave driver in 65-nm CMOS technology (2014) (5)
- An INL Yield Model of the Digital-to-Analog Converter (2013) (5)
- Phase correction of a resonant clocking system using resonant interpolators (2008) (5)
- Design and analysis of a jitter-tolerant digital delay-locked-loop based fraction-of-clock delay line (2004) (5)
- A low-PDP and low-area repeater using passive CTLE for on-chip interconnects (2015) (5)
- A 0.6pm CMOS 4Gb/s Transceiver with Data Recovery usi (1997) (5)
- A 9-μm Precision 5-MSa/s Pulsed-Coherent Lidar System With Subsampling Receiver (2020) (5)
- A compact stacked-device output driver in low-voltage CMOS Technology (2014) (5)
- A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters (2015) (4)
- An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications (2019) (4)
- Analysis of timing recovery for multi-Gbps PAM transceivers (2003) (4)
- A nonlinear phase detector for digital phase locked loops (2009) (4)
- A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS (2013) (4)
- A 92%-Efficiency Battery Powered Hybrid DC-DC Converter for IoT Applications (2020) (4)
- In Situ SRAM Static Stability Estimation in 65-nm CMOS (2013) (4)
- A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems (2019) (3)
- An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving (2013) (3)
- A bandwidth tracking technique for a 65nm CMOS digital phase-locked loop (2009) (3)
- A bipolar >40-V driver in 45-nm SOI CMOS technology (2013) (3)
- Error Reduction Techniques in Geometric Programming based Mixed-Mode Circuit Design Optimization (2004) (3)
- A stochastic jitter model for analyzing digital timing-recovery circuits (2009) (3)
- Electrostatic bottom-driven rotary stage on multiple conductive liquid-ring bearings (2013) (3)
- An LC-Based Clock Buffer With Tunable Injection Locking (2009) (3)
- A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot (2020) (3)
- BER-based Adaptation of I/O Link Equalizers (2007) (3)
- An 8Gb/s Transformer-Boosted Transmitter with >V/sub 00/ swing (2006) (2)
- A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS (2021) (2)
- Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter (2012) (2)
- A Scalable 20V Charge-Pump-Based Driver in 65nm CMOS Technology (2021) (1)
- An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications (2019) (1)
- FP 12.4: A 0.8~ CMOS 2.5Gb/s Oversampled Receiver for Serial Links (1996) (1)
- A 14-bit, 5-MHz digital-to-analog converter using multi-bit /spl Sigma//spl Delta/ modulation (1998) (1)
- Clocking Links in Multi-chip Packages: A Case Study (2010) (1)
- A 0.1–1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection (2012) (1)
- A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding (2013) (1)
- ADC-Based Serial I/O Receivers (2010) (1)
- A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding (2012) (0)
- FPGA Implementation of Network Optimization for Flash ADC Calibration (2011) (0)
- A Schottky-Diode-Based Wake-Up Receiver for IoT Applications (2021) (0)
- CMOS LC oscillator using variable mean frequency (2003) (0)
- A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input (2022) (0)
- Effects of Active Cooling on Workload Management in High Performance Processors (2015) (0)
- A 19-GHz Pulsed-Coherent ToF Receiver With 40- $\mu$ m Precision for Laser Ranging Systems (2019) (0)
- Guest Editorial for Special Issue on High-Performance Multichip Interconnections (2010) (0)
- Input/Output Devices (2004) (0)
- with >VDD Swing (2006) (0)
- A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS (2021) (0)
- A Low Power 100 GHz Static CML Frequency Divider in 0.18 μm SiGe BiCMOS Technology (2023) (0)
- A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA (2021) (0)
- SE4 Circuits and Applications for Organic Electronics (2004) (0)
- Mark Horowitz's Link to Chip-to-Chip Communication: His Significant and Fundamental Contributions (2016) (0)
- On-chip soliton based pulsed-coherent AMCW LiDAR (2022) (0)
- CMOS Scaling on I/O Design (2004) (0)
- Design and Optimization of Multipath (2011) (0)
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What Schools Are Affiliated With Chih-Kong Ken Yang?
Chih-Kong Ken Yang is affiliated with the following schools:
