Choi Ki-young | Academic Influence

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Choi Ki-young

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#13

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Choi Ki-young

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#14866

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Engineering
Philosophy

Choi Ki-young's Degrees

Bachelors Electrical Engineering Seoul National University
Masters Computer Science KAIST

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Why Is Choi Ki-young Influential?

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According to Wikipedia, Choi Ki-young is a South Korean professor of electrical engineering at Seoul National University who served as Minister of Science and ICT under President Moon Jae-in from 2019 to 2021. After working at now-LG Electronics and Cadence Design Systems, he return to his first alma mater. He took several roles in his faculty including the director of Neural Processing Research Center and Embedded Systems Research Center.

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Choi Ki-young's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A scalable processing-in-memory accelerator for parallel graph processing (2015) (631)
PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture (2015) (421)
Power conscious fixed priority scheduling for hard real-time systems (1999) (391)
Power optimization of real-time embedded systems on variable speed processors (2000) (274)
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks (2016) (128)
Benzene (2018) (127)
Partial bus-invert coding for power optimization of application-specific systems (2001) (119)
Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization (2005) (99)
Compilation approach for coarse-grained reconfigurable architectures (2003) (96)
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture (2014) (92)
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array (2016) (88)
Power minimization of functional units partially guarded computation (2000) (85)
Partial bus-invert coding for power optimization of system level bus (1998) (80)
Deep neural networks with weighted spikes (2018) (72)
Instruction set synthesis with efficient instruction encoding for configurable processors (2007) (58)
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator (2017) (57)
Efficient instruction encoding for automatic instruction set design of configurable ASIPs (2002) (57)
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures (2006) (55)
Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture (2006) (55)
Behavior-to-placed RTL synthesis with performance-driven placement (2001) (54)
High-level synthesis under multi-cycle interconnect delay (2001) (54)
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures (2011) (53)
An algorithm for mapping loops onto coarse-grained reconfigurable architectures (2003) (53)
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs (2000) (50)
FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability (2009) (50)
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture (2016) (45)
An energy-efficient random number generator for stochastic circuits (2016) (40)
Exploiting New Interconnect Technologies in On-Chip Communication (2012) (38)
Power minimization of functional units by partially guarded computation (2000) (37)
Coarse-Grained Reconfigurable Array: Architecture and Application Mapping (2011) (37)
Design space exploration of FPGA accelerators for convolutional neural networks (2017) (34)
Performance-driven high-level synthesis with bit-level chaining andclock selection (2001) (34)
SoCDAL: System-on-chip design AcceLerator (2008) (34)
Schedulability-driven performance analysis of multiple mode embedded real-time systems (2000) (33)
Configurable Processors for Embedded Computing (2003) (32)
Power-conscious High Level Synthesis Using Loop Folding (1997) (32)
Approximate de-randomizer for stochastic circuits (2015) (32)
Write intensity prediction for energy-efficient non-volatile caches (2013) (32)
Dynamic operand interchange for low power (1997) (31)
Fast functional simulation: an incremental approach (1988) (29)
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture (2010) (29)
Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture (2009) (28)
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA (2013) (28)
Scheduler implementation in MP SoC design (2005) (27)
Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks (2017) (27)
Narrow bus encoding for low power systems (2000) (27)
Optimistic distributed timed cosimulation based on thread simulation model (1998) (27)
Narrow bus encoding for low-power DSP systems (2001) (27)
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model (2002) (26)
Incremental-in-time algorithm for digital simulation (1988) (25)
Lower-bits cache for low power STT-RAM caches (2012) (25)
Performance improvement of multi-processor systems cosimulation based on SW analysis (2001) (25)
Scalable stochastic-computing accelerator for convolutional neural networks (2017) (24)
A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers (2016) (24)
Communication Architecture Synthesis of Cascaded Bus Matrix (2007) (24)
Loop pipelining in hardware-software partitioning (1998) (24)
Low power high level synthesis by increasing data correlation (1997) (24)
Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus (2009) (23)
Energy-efficient instruction set synthesis for application-specific processors (2003) (22)
Mapping control intensive kernels onto coarse-grained reconfigurable array architecture (2008) (21)
AIM (2003) (21)
Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing (2002) (21)
Acceleration of control flow on CGRA using advanced predicated execution (2010) (21)
Dynamic power management of off-chip links for Hybrid Memory Cubes (2014) (20)
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model (2002) (19)
Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip (2007) (19)
State-based full predication for low power coarse-grained reconfigurable architecture (2012) (19)
An integrated hardware-software cosimulation environment with automated interface generation (1996) (19)
Compiling control-intensive loops for CGRAs with state-based full predication (2013) (19)
Design and Evaluation of a Coarse-Grained Reconfigurable Architecture (2004) (19)
Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint (2013) (18)
Interleaving partial bus-invert coding for low power reconfiguration of FPGAs (1999) (17)
Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations (2006) (17)
Synchronization Overhead Reduction in Timed Cosimulation (1997) (17)
An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping (1998) (16)
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture (2010) (16)
A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections (2013) (16)
Reduction of bus transitions with partial bus-invert coding (1998) (15)
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching (2016) (15)
Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis (2007) (15)
An FPGA implementation of high-throughput key-value store using Bloom filter (2014) (15)
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM (2015) (15)
Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques (2008) (15)
Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures (2003) (15)
Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design (2003) (14)
Enforcing schedulability of multi-task systems by hardware-software codesign (1997) (14)
3D network-on-chip with wireless links through inductive coupling (2011) (14)
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches (2013) (14)
Binary acceleration using coarse-grained reconfigurable architecture (2010) (14)
ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator (2018) (14)
New address generation scheme for memory-based FFT processor using multiple radix-2 butterflies (2008) (13)
ODALRISC: A small, low power, and configurable 32-bit RISC processor (2008) (13)
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent (2021) (13)
Low power pipelining of linear systems: A common operand centric approach (2001) (13)
Fast Prototyping of an IS-95 CDMA Cellular Phone : a Case Study (1999) (13)
REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections (2015) (13)
Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture (2007) (13)
An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth (2012) (12)
A space- and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures (2017) (12)
Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic (2016) (12)
Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture (2010) (11)
An approach to code compression for CGRA (2011) (11)
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping (1995) (11)
Autoencoder-Based Incremental Class Learning without Retraining on Old Data (2019) (11)
Thor user''s manual: tutorial and commands (1988) (11)
Scheduling-based code size reduction in processors with indirect addressing mode (2001) (11)
Reconfigurable ALU Array Architecture with Conditional Execution (2004) (10)
Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip (2016) (10)
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems (2018) (10)
Software synthesis through task decomposition by dependency analysis (1996) (10)
Memory-Centric Communication Architecture for Reconfigurable Computing (2010) (10)
Energy-efficient partitioning of hybrid caches in multi-core architecture (2014) (10)
Tree-Mesh Heterogeneous Topology for Low-Latency NoC (2014) (9)
Exploration of trade-offs in the design of volatile STT-RAM cache (2016) (9)
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (2006) (9)
Multiprocessor system-on-chip designs with active memory processors for higher memory efficiency (2009) (9)
Aging Compensation With Dynamic Computation Approximation (2020) (9)
Efficient Design Space Exploration for Domain-Specific Optimization of Coarse-Grained Reconfigurable Architecture (2005) (9)
Optimizing Timed Cosimulation by Hybrid Synchronization (2000) (8)
Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction (2007) (8)
A host-accelerator communication architecture design for efficient binary acceleration (2011) (8)
Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization (1999) (8)
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures (2015) (8)
Deflection routing in 3D Network-on-Chip with TSV serialization (2013) (8)
Architectures and algorithms for user customization of CNNs (2018) (8)
Active Memory Processor for Network-on-Chip-Based Architecture (2012) (8)
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips (2012) (8)
Effective synthesis algorithm for partitioned bus architecture (1999) (8)
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages (2000) (7)
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages (1999) (7)
Isomorphism-Aware Identification of Custom Instructions With I/O Serialization (2013) (7)
Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation (2007) (7)
An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth (2012) (7)
Thread-based software synthesis for embedded system design (1996) (7)
Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation (2018) (7)
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding (2018) (7)
AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy (2016) (6)
Efficient prototyping system based on incremental design and module-by-module verification (1995) (6)
VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks (2019) (6)
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study (2014) (6)
Efficient VLSI architecture for lossless data compression (1995) (6)
A self-timed divider using RSD number system (1994) (6)
Proceedings of the 28th Asia and South Pacific Design Automation Conference (2008) (6)
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology (2014) (6)
Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators (2019) (6)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors (2018) (6)
Performance-driven scheduling with bit-level chaining (1999) (6)
FPGA implementation of convolutional neural network based on stochastic computing (2017) (6)
Acceleration of DNN Backward Propagation by Selective Computation of Gradients (2019) (6)
Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture (2014) (5)
Memory-aware mapping and scheduling of tasks and communications on many-core SoC (2012) (5)
Automatic Instruction Set Design Through Efficient Instruction Encoding for Application-Specific Processors (2003) (5)
Deflection routing in 3D network-on-chip with limited vertical bandwidth (2013) (5)
Self-timed statistical carry lookahead adder using multiple-output DCVSL (1999) (5)
Temporal Mapping for Loop Pipelining on a MIMD-style Coarse-Grained Reconfigurable Architecture (2006) (5)
Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes (2007) (5)
Compilation Approach for Coarse-Grained Reconfigurable (2003) (5)
Self-timed divider based on RSD number system (1996) (5)
SoC Architecture for Automobile Vision System (2014) (5)
Partitioned-bus architecture synthesis based on data transfer model (5)
A design guideline for volatile STT-RAM with ECC and scrubbing (2015) (5)
Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution (2010) (5)
CRM: Configurable Range Memory for Fast Reconfigurable Computing (2011) (5)
Hardware-software codesign of resource-constrained real-time systems (1996) (5)
Fast Generation of Multiple Custom Instructions under Area Constraints (2011) (5)
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model (2000) (4)
Entry control in network-on-chip for memory power reduction (2008) (4)
A polynomial-time custom instruction identification algorithm based on dynamic programming (2011) (4)
Latency minimisation by system clock optimisation (1998) (4)
A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem (2012) (4)
Java-Based Programmable Networked Embedded System Architecture with Multiple Application Support (4)
A new approach to binarizing neural networks (2016) (3)
VHDL simulation acceleration using specialized functions (1997) (3)
Modified half rail differential logic for reduced internal logic swing (1998) (3)
Fast hardware-software coverification by optimistic execution of real processor (2000) (3)
High-level synthesis with distributed controller for fast timing closure (2011) (3)
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration (2007) (3)
DOMAIN-SPECIFIC OPTIMIZATION OF RECONFIGURABLE ARRAY ARCHITECTURE (2006) (3)
Low power self-timed floating-point divider in 0.25um technology (2000) (3)
Aging Gracefully with Approximation (2019) (3)
Power-conscious Scheduling for Real-time Embedded Systems Design (2001) (3)
Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares (2017) (3)
Communication architecture design for reconfigurable multimedia SoC platform (2010) (3)
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors (2011) (3)
Training Neural Networks with Low Precision Dynamic Fixed-Point (2018) (3)
VHDL Developer's Toolkit 2.6 User's Guide & Reference (1997) (3)
Simulated annealing-based diffusive load balancing on many-core SoC (2011) (2)
Reconfigurable Architectures (2017) (2)
Multi-codec variable length decoder design with configurable processor (2008) (2)
SAT-based state encoding for peak current Minimization (2009) (2)
An Efficient Self-Timed Divider (1993) (2)
Low Voltage and High Speed 1Xnm 1T1C FE-RAM with Ultra-Thin 5nm HZO (2021) (2)
Worst case execution time analysis for synthesized hardware (2006) (2)
Buffer Size Reduction through Control-Flow Decomposition (2007) (2)
Leveraging parallelism in the presence of control flow on CGRAs (2014) (2)
Thor user''s manual: library functions (1988) (2)
Exploiting early partial reconfiguration of run-time reconfigurable FPGAs in embedded systems design (abstract only) (1999) (2)
How Much Computation Power do you need for Near-Data Processing in Cloud ? (2018) (2)
Fast custom instruction generation under area constraint (2010) (2)
Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch (2017) (2)
Area-efficient buffer binding based on a novel two-port FIFO structure (2001) (1)
Tapered-Ratio Compression for Residual Network (2018) (1)
Coarse-grained reconfigurable architecture for multiple application domains: a case study (2009) (1)
Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing (2013) (1)
VLSI-SoC: Design for Reliability, Security, and Low Power (2015) (1)
Synthesis of Instruction Sets for High-Performance and Energy-Efficient ASIP (2007) (1)
Techniques for improving coarse-grained reconfigurable architectures (2011) (1)
Low power self-timed radix-2 division (2000) (1)
Adaptive delay monitoring for wide voltage-range operation (2016) (1)
Resource-shared custom instruction generation under performance/area constraints (2012) (1)
Hardware synthesis for stack type partitioned-bus architecture (1999) (1)
Generalized Parameter Extraction Model for High-Speed Interconnects with Arbitrary Boundary Conditions (2011) (1)
GUEST EDITORS' INTRODUCTION - Special Section on Hardware Description Languages (1998) (1)
A formal approach toward developing an equivalent circuit for high-speed coupled interconnects with intermediate ground insertion (2010) (1)
Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks (2018) (1)
Code decomposition and recomposition for enhancing embedded software performance (2009) (1)
Concept-aware ensemble system for pedestrian detection (2014) (1)
Leakage power reduction of functional units in processors having zero-overhead loop counter (2009) (1)
Rate assignment for embedded reactive real-time systems (1998) (1)
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems (2004) (1)
Compression of Simulation Results by Sampling (1996) (1)
An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design (2003) (1)
GPU-Based Acceleration of Quantum-Inspired Evolutionary Algorithm (2012) (1)
Network Recasting: A Universal Method for Network Architecture Transformation (2018) (1)
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines (2008) (1)
Optimal mapping of program overlays onto many-core platforms with limited memory capacity (2017) (1)
Dynamic clock synchronization scheme between voltage domains in multi-core architecture (2016) (1)
Library-based Mapping of Application to Reconfigurable Array Architecture (2009) (1)
ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator (2022) (1)
Accelerator for Parallel Graph Processing (2015) (0)
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006 (2006) (0)
Comparison of Two 3D-stacked Inductive Coupling Communication Interfaces (2011) (0)
Optimal mapping of program overlays onto many-core platforms with limited memory capacity (2017) (0)
6 Applications of Reconfigurable Computing (2017) (0)
Application-specific configuration of multithreaded processor architecture for embedded applications (2004) (0)
Guest Editorial New Interconnect Technologies in On-Chip Communication (2012) (0)
11.6 Applications of Reconfigurable Computing (2019) (0)
Low power self-timed Radix-2 division (poster session) (2000) (0)
Dynamic error tracking and supply voltage adjustment for low power (2015) (0)
Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture (2013) (0)
Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands (2018) (0)
Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators (2018) (0)
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 (2004) (0)
Hybrid Simulation for IP-Based Design (1999) (0)
Hybrid spiking-stochastic Deep Neural Network (2017) (0)
Design verification by concurrent simulation and automatic comparison (1997) (0)
Pipelining with common operands for power-efficient linear systems (2005) (0)
Emerging Interconnect Technologies for 3D Networks-on-Chip (2018) (0)
Synthesis of multi-variate stochastic computing circuits (2017) (0)
Application-specific Microprocessors Compilation Techniques (2009) (0)
ESL Design Methodology (2012) (0)
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing (2015) (0)
Incremental training of CNNs for user customization: work-in-progress (2017) (0)
A new stochastic mutiplier for deep neural networks (2017) (0)
Enhancing schedulability of hard real-time systems through codesign (1997) (0)
QoS-aware dynamic power management for coarse-grained reconfigurable architecture (2009) (0)
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 (2007) (0)
Work-in-progress: incremental training of CNNs for user customization (2017) (0)
Introduction to embedded systems week 2006 special issue (2008) (0)
Editorial ESL DesignMethodology (2015) (0)
An Approach to Combining Emulation and Simulation for Efficient Debugging of System-on-Chip Design (2001) (0)
An Efficient Computer-Aided Prototyping System Based on FPGAs (1994) (0)
Modeling functional unit delays for bit-level chaining (2008) (0)
A Transformation Technique for power-conscious High Level Synthesis (1996) (0)
A new cost model for high-level power optimization and its application (2000) (0)
An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network (2019) (0)
Design of a Synthesizable RISC Processor (2004) (0)
Configurable range memory for effective data reuse on programmable accelerators (2014) (0)
Area-efficient buffer binding based on a novel two-part FIFO structure (2001) (0)
Fast Simulation Method for Analog Deep Binarized Neural Networks (2019) (0)
Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth (2013) (0)
Automatic Generation of Transaction Level Code for Fast SoC Design Space Exploration (2006) (0)
Scheduling and iming analysis of HW/SW on-chip communication in MP SoC design (2003) (0)
REDELF (2015) (0)
Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12) (2014) (0)
A Novel Self-Timed Ring Structure for SRT Division (1996) (0)
AN EFFICIENT VLSI ARCHITECTURE FOR LEMPEL-ZIV-BASED DATA COMPRESSION (1995) (0)
MPSoC Design Space Exploration Based on Static Analysis of Process Network Model (2007) (0)

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