Chung-kuan Cheng

Chung-kuan Cheng's AcademicInfluence.com Rankings

Chung-kuan Cheng

Engineering

#7423

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#8795

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Electrical Engineering

#2322

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#2430

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engineering Degrees

Chung-kuan Cheng

Computer Science

#10122

World Rank

#10617

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Information Systems

#33

World Rank

#36

Historical Rank

Computer Architecture

#66

World Rank

#68

Historical Rank

Database

#7078

World Rank

#7323

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computer-science Degrees

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Engineering
Computer Science

Chung-kuan Cheng's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering National Taiwan University

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Chung-kuan Cheng's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

An O-tree representation of non-slicing floorplan and its applications (1999) (388)
Corner block list: an effective and efficient topological representation of non-slicing floorplan (2000) (321)
Optimal wire sizing and buffer insertion for low power and a generalized delay model (1995) (313)
Ratio cut partitioning for hierarchical designs (1991) (280)
Towards efficient hierarchical designs by ratio cut partitioning (1989) (221)
Module Placement Based on Resistive Network Optimization (1984) (192)
An improved two-way partitioning algorithm with stable performance [VLSI] (1991) (164)
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing (1996) (105)
Floorplanning using a tree representation (2001) (101)
Floorplan representations: Complexity and connections (2003) (86)
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement (2019) (84)
A general purpose multiple way partitioning algorithm (1991) (83)
Area minimization of power distribution network using efficient nonlinear programming techniques (2001) (82)
An enhanced perturbing algorithm for floorplan design using the O-tree representation (2000) (75)
Block placement with symmetry constraints based on the O-tree non-slicing representation (2000) (74)
Simultaneous routing and buffer insertion for high performance interconnect (1996) (65)
Performance-Driven Steiner Tree Algorithms for Global Routing (1993) (65)
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method (2015) (64)
A global router with a theoretical bound on the optimal solution (1996) (64)
A global router using an efficient approximate multicommodity multiterminal flow algorithm (1991) (64)
The Y architecture for on-chip interconnect: analysis and methodology (2003) (63)
Circuit Partitioning for Huge Logic Emulation Systems (1994) (62)
Integrating dynamic thermal via planning with 3D floorplanning algorithm (2006) (59)
A probabilistic multicommodity-flow solution to circuit clustering problems (1992) (58)
An algorithmic approach for generic parallel adders (2003) (57)
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits (2015) (56)
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization (2006) (53)
Corner block list representation and its application to floorplan optimization (2004) (51)
A replication cut for two-way partitioning (1995) (51)
Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach (1993) (50)
Rectilinear block placement using sequence-pair (1998) (50)
An Efficient Timing-Driven Global Routing Algorithm (1993) (49)
An Online Brain-Computer Interface Based on SSVEPs Measured From Non-Hair-Bearing Areas (2017) (48)
A two-level two-way partitioning algorithm (1990) (47)
Power network analysis using an adaptive algebraic multigrid approach (2003) (47)
A wire length estimation technique utilizing neighborhood density equations (1992) (47)
Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards (2009) (45)
The Y-architecture: yet another on-chip interconnect solution (2003) (45)
Communication latency aware low power NoC synthesis (2006) (44)
Efficient and accurate eye diagram prediction for high speed signaling (2008) (40)
ePlace: Electrostatics based placement using Nesterov's method (2014) (39)
Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization (2005) (38)
TIGER: an efficient timing-driven global router for gate array and standard cell layout design (1997) (37)
Developing an EEG-based on-line closed-loop lapse detection and mitigation system (2014) (37)
Measuring Steady-State Visual Evoked Potentials from non-hair-bearing areas (2012) (37)
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm (1995) (37)
VLSI floorplanning with boundary constraints based on corner block list (2001) (36)
Optimal planning for mesh-based power distribution (2004) (36)
Linear decomposition algorithm for VLSI design applications (1995) (35)
Revisiting floorplan representations (2001) (35)
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning (2007) (35)
Ancestor tree for arbitrary multi-terminal cut functions (1990) (35)
Wire Length And Delay Minimization In General Clock Net Routing (1993) (35)
Optimal and efficient buffer insertion and wire sizing (1995) (34)
Realizable parasitic reduction using generalized Y-Δ transformation (2003) (34)
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction (2002) (34)
Skew Sensitivity Minimization Of Buffered Clock Tree (1994) (33)
Linear placement algorithms and applications to VLSI design (1987) (33)
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control (2012) (32)
Improved channel routing by via minimization and shifting (1988) (31)
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals (2007) (31)
ECBL: an extended corner block list with solution space including optimum placement (2001) (31)
Fast post-placement rewiring using easily detectable functional symmetries (2000) (31)
Layer Minimization of Escape Routing in Area Array Packaging (2006) (31)
A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation (2012) (31)
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space (2007) (30)
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing (2003) (29)
Rectilinear block packing using O-tree representation (2001) (29)
Surfliner: a distortionless electrical signaling scheme for speed of light on-chip communications (2005) (28)
A mulitple level network approach for clock skew minimization with process variations (2004) (28)
ePlace-3D: Electrostatics based Placement for 3D-ICs (2015) (27)
MATEX: A distributed framework for transient simulation of power distribution networks (2014) (27)
Optimization by iterative improvement: an experimental evaluation on two-way partitioning (1995) (26)
Parallel transistor level circuit simulation using domain decomposition methods (2009) (26)
Performance-Driven Partitioning Using a Replication Graph Approach (1995) (25)
Efficient escape routing for hexagonal array of high density I/Os (2006) (25)
Hurwitz stable reduced order modeling for RLC interconnect trees (2000) (25)
Unified quadratic programming approach for mixed mode placement (2005) (25)
An algebraic multigrid solver for analytical placement with layout based clustering (2003) (25)
Reliability aware through silicon via planning for 3D stacked ICs (2009) (25)
Timing Optimization For Multi-source Nets: Characterization And Optimal Repeater Insertion (1997) (24)
A multi-probe approach for MCM substrate testing (1994) (24)
A novel fixed-outline floorplanner with zero deadspace for hierarchical design (2008) (23)
An efficient multilevel placement technique using hierarchical partitioning (1992) (23)
Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG (2015) (23)
Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI (2013) (23)
Analyzing High-Density ECG Signals Using ICA (2008) (22)
Constructing zero-deficiency parallel prefix adder of minimum depth (2005) (22)
Performance-driven partitioning using retiming and replication (1993) (22)
Circuit clustering using a stochastic flow injection method (1995) (22)
Cluster Refinement For Block Placement (1997) (21)
Marked Increases in Resting-State MEG Gamma-Band Activity in Combat-Related Mild Traumatic Brain Injury. (2020) (21)
Routability improvement using dynamic interconnect architecture (1995) (21)
Dynamic global buffer planning optimization based on detail block locating and congestion analysis (2003) (20)
3-D floorplanning using labeled tree and dual sequences (2008) (20)
The optimal partitioning of networks (1992) (20)
The Orientation of Modules Based on Graph Decomposition (1991) (20)
Sequence-pair approach for rectilinear module placement (1999) (20)
On the construction of zero-deficiency parallel prefix circuits with minimum depth (2006) (20)
3D power distribution network co-design for nanoscale stacked silicon ICs (2008) (20)
Buffer planning as an Integral part of floorplanning with consideration of routing congestion (2005) (20)
Circuit simulation via matrix exponential method for stiffness handling and parallel processing (2012) (20)
New spectral linear placement and clustering approach (1996) (20)
Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list (2001) (19)
Fast postplacement optimization using functional symmetries (2004) (19)
3D stacked power distribution considering substrate coupling (2009) (19)
A block-diagonal structured model reduction scheme for power grid networks (2011) (19)
Power grid simulation using matrix exponential method with rational Krylov subspaces (2013) (19)
Prediction and Comparison of High-Performance On-Chip Global Interconnection (2011) (19)
Tutorial on VLSI Partitioning (2000) (19)
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect (2007) (18)
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints (2012) (17)
MEG Working Memory N-Back Task Reveals Functional Deficits in Combat-Related Mild Traumatic Brain Injury. (2019) (17)
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks (2015) (17)
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP (1993) (16)
FARM: an efficient feed-through pin assignment algorithm (1992) (16)
Worst-case noise prediction with non-zero current transition times for early power distribution system verification (2010) (16)
Symbolic analysis and reduction of VLSI circuits (2004) (16)
On general zero-skew clock net construction (1995) (15)
Novel Differential-Mode Equalizer With Broadband Common-Mode Filtering for Gb/s Differential-Signal Transmission (2013) (15)
Character design and stamp algorithms for Character Projection Electron-Beam Lithography (2012) (15)
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration (2007) (15)
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing (2003) (15)
High performance on-chip differential signaling using passive compensation for global communication (2009) (15)
Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design (2009) (15)
Toward better wireload models in the presence of obstacles (2001) (15)
Design methodology of high performance on-chip global interconnect using terminated transmission-line (2009) (14)
RCLK-VJ network reduction with Hurwitz polynomial approximation (2003) (14)
Cell-phone based Drowsiness Monitoring and Management system (2012) (14)
Parallel transistor level full-chip circuit simulation (2009) (14)
Digital design and programmable logic boards: Do students actually learn more? (2008) (14)
Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list (2001) (14)
A performance-driven I/O pin routing algorithm (1999) (14)
Algorithms for optimal introduction of redundant logic for timing and area optimization (1996) (14)
Multiple-level partitioning: an application to the very large-scale hardware simulator (1991) (14)
Local ratio cut and set covering partitioning for huge logic emulation systems (1995) (13)
Constructing Zero-deficiency Parallel Prefix Circuits of Minimum Depth (2005) (13)
Fast power network analysis with multiple clock domains (2007) (13)
An iterative division algorithm for FPGAs (2006) (13)
Timing Model Reduction for Hierarchical Timing Analysis (2006) (13)
Modeling and Analysis of Power Distribution Networks in 3-D ICs (2013) (13)
Symbolic layout compaction under conditional design rules (1992) (13)
A buffer planning algorithm based on dead space redistribution (2003) (13)
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits (2016) (13)
An integrated floorplanning with an efficient buffer planning algorithm (2003) (12)
Estimation of Wirelength Reduction for λ-Geometry vs . Manhattan Placement and Routing (2003) (12)
Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response (2007) (12)
Two-Stage Newton-Raphson Method for Transistor-Level Simulation (2007) (12)
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects (2014) (12)
CMOS Power Amplifiers for Wireless Communications (2003) (12)
More realistic power grid verification based on hierarchical current and power constraints (2011) (12)
Fast and Precise Routability Analysis with Conditional Design Rules (2018) (12)
Efficient Power Network Analysis Considering Multidomain Clock Gating (2009) (11)
Exploring the rogue wave phenomenon in 3D power distribution networks (2010) (11)
Realizable parasitic reduction using generalized Y-/spl Delta/ transformation (2003) (11)
Empirical mode decomposition improves detection of SSVEP (2013) (11)
Optimal buffered clock tree synthesis (1994) (11)
From Circuit Theory, Simulation to SPICEDiego<\/sup>: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits (2016) (11)
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness (2010) (11)
Representing topological structures for 3-D floorplanning (2009) (10)
A non-slicing floorplanning algorithm using corner block list topological representation (2000) (10)
Design and implementation of a global router based on a new layout-driven timing model with three poles (1997) (10)
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential (2012) (10)
A building block placement tool (1997) (10)
Circuit simulation using matrix exponential method (2011) (10)
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform (2010) (10)
Design considerations and algorithms for partitioning optoelectronic multichip modules. (1995) (9)
Noninvasive Study of the Human Heart using Independent Component Analysis (2006) (9)
Eye prediction of digital driver with power distribution network noise (2012) (9)
Prediction of high-performance on-chip global interconnection (2009) (9)
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators (2015) (9)
Low power passive equalizer optimization using tritonic step response (2008) (9)
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications (2011) (9)
Low Power Passive Equalizer Design for Computer Memory Links (2008) (9)
Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing (2020) (8)
Performance driven bus buffer insertion (1996) (8)
Finite state machine decomposition for I/O minimization (1995) (8)
Improving the efficiency of static timing analysis with false paths (2005) (8)
Cuff-Less Blood Pressure Monitoring with a 3-Axis Accelerometer (2019) (8)
A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation (2011) (8)
Floorplanning with abutment constraints based on corner block list (2001) (8)
Arbitrary convex and concave rectilinear block packing based on corner block list (2003) (8)
Algorithms for performance-driven design of integrated circuits (1996) (7)
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT (2021) (7)
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals (2011) (7)
Distortion Minimization for Packaging Level Interconnects (2006) (7)
Physical planning of on-chip interconnect architectures (2002) (7)
A Network Flow Approach For Hierarchical Tree Partitioning (1997) (7)
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules (2020) (7)
On-chip global clock distribution using directional rotary traveling-wave oscillator (2009) (7)
Module placement with boundary constraints using O-tree representation (2002) (7)
Dynamic analysis of power delivery network with nonlinear components using matrix exponential method (2015) (7)
High-speed and low-power on-chip global link using continuous-time linear equalizer (2010) (7)
Dynamic probe scheduling optimization for MCM substrate test (1994) (7)
Stairway compaction using corner block list and its applications with rectilinear blocks (2002) (7)
On the bound of time-domain power supply noise based on frequency-domain target impedance (2009) (7)
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm (2020) (7)
An optimal probe testing algorithm for the connectivity verification of MCM substrates (1992) (7)
Optimization of power dissipation and skew sensitivity in clock buffer synthesis (1995) (7)
An unconditional stable general operator splitting method for transistor level transient analysis (2006) (7)
Enabling power distribution network analysis flows for 3D ICs (2010) (7)
Epidermal Graphene Sensors and Machine Learning for Estimating Swallowed Volume (2021) (6)
Energy and switch area optimizations for FPGA global routing architectures (2009) (6)
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization (2013) (6)
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures (2009) (6)
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (2009) (6)
Bus via reduction based on floorplan revising (2010) (6)
Timing-power optimization for mixed-radix Ling adders by integer linear programming (2008) (6)
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era (2012) (6)
Optimal Test Size and Efficient Probe Scheduling for Substrate Verification Using Two-Probe Testers (1993) (6)
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization (2007) (6)
Network partitioning into tree hierarchies (1996) (6)
Clock Skew Analysis via Vector Fitting in Frequency Domain (2008) (6)
A buffer planning algorithm with congestion optimization (2004) (6)
Data Flow Partitioning for Clock Period and Latency Minimization (1994) (6)
Layer minimization in escape routing for staggered-pin-array PCBs (2013) (6)
A hierarchical three-way interconnect architecture for hexagonal processors (2003) (6)
ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques (2019) (5)
Maximum concurrent flows and minimum cuts (1992) (5)
The Y-architecture for on-chip interconnect: analysis and methodology (2003) (5)
Floorplanning using a tree representation: a summary (2003) (5)
On-chip power network optimization with decoupling capacitors and controlled-ESRs (2010) (5)
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation (2017) (5)
RLC interconnect delay estimation via moments of amplitude and phase response (1999) (5)
Transient Circuit Simulation for Differential Algebraic Systems using Matrix Exponential (2018) (5)
GRA-LPO: Graph Convolution Based Leakage Power Optimization (2021) (5)
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network (2009) (5)
Predicting the worst-case voltage violation in a 3D power network (2009) (5)
Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs (2013) (5)
Circuit partitioning and its applications to vlsi designs (1990) (5)
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs (2021) (5)
Passive compensation for high performance inter-chip communication (2007) (5)
Noise minimization during power-up stage for a multi-domain power network (2009) (5)
Timing optimization for multisource nets: characterization andoptimal repeater insertion (1999) (5)
Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links (2011) (5)
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths (2006) (5)
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT (2020) (5)
Worst-case noise prediction using power network impedance profile (2013) (5)
Simple tree-construction heuristics for the fanout problem (1995) (4)
VLSI Block Placement With Alignment Constraints (2006) (4)
VLSI block placement with alignment constraints based on corner block list (2005) (4)
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes (2021) (4)
Efficient timing analysis with known false paths using biclique covering (2007) (4)
Geometric compaction on channel routing (1992) (4)
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC (2021) (4)
Circuit partitioning for pipelined pseudo-exhaustive testing using simulated annealing (1994) (4)
Block placement with symmetry constraints based on the O-tree non-silicing representation (2000) (4)
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation (2020) (4)
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (2008) (4)
Evaluating a bounded slice-line grid assignment in O(nlogn) time (2003) (4)
An optimum placement search algorithm based on extended Corner Block List (2002) (4)
On-chip bus signaling using passive compensation (2008) (4)
Data flow partitioning with clock period and latency constraints (1997) (4)
An efficient algorithm for the net matching problem (1993) (4)
Worst-Case Noise Area Prediction of On-Chip Power Distribution Network (2014) (3)
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning (2021) (3)
Efficient frequency-dependent reluctance extraction for large-scale Power/Ground grid (2008) (3)
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility (2020) (3)
Advancing supercomputer performance through interconnection topology synthesis (2008) (3)
R-peak Detection Using a Hybrid of Gaussian and Threshold Sensitivity (2020) (3)
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial (2002) (3)
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints" (2012) (3)
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes (2022) (3)
High performance current-mode differential logic (2008) (3)
Incremental Power Impedance Optimization Using Vector Fitting Modeling (2007) (3)
On-chip high performance signaling using passive compensation (2008) (3)
Distortion Mapping for Cofired Ceramic Substrate Testing (1993) (3)
Efficient transient simulation for transistor-level analysis (2005) (3)
An interdigitated non-contact ECG electrode for impedance compensation and signal restoration (2015) (3)
Octilinear redistributive routing in bump arrays (2009) (3)
A new layout-driven timing model for incremental layout optimization (1997) (3)
Interconnect implications of growth-based structural models for VLSI circuits (2001) (3)
Physical synthesis of bus matrix for high bandwidth low power on-chip communications (2010) (3)
Physical models and algorithms for optoelectronic MCM layout (1995) (3)
Balancing the interconnect topology for arrays of processors between cost and power (2002) (2)
Buffer allocation algorithm with consideration of routing congestion (2004) (2)
A buffer planning algorithm for chip-level floorplanning (2004) (2)
Tree Structures and Algorithms for Physical Design (2018) (2)
Impulse response generation from S-parameters for power delivery network simulation (2015) (2)
Fast Transient Simulation of Lossy Transmission Lines (2007) (2)
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations (2009) (2)
Pin Redistribution for Multichip Module Designs (1993) (2)
Worst-case performance prediction under supply voltage and temperature variation (2010) (2)
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design (2009) (2)
Study of visual stimulus waveforms via forced van der Pol oscillator model for SSVEP-based brain-computer interfaces (2013) (2)
Efficient Power Network Analysis with Modeling of Inductive Effects (2010) (2)
Floorplan Representation in VLSI (2004) (2)
Interconnect analysis and synthesis. [Book Review] (2001) (2)
Corner block list representation and its application with boundary constraints (2004) (2)
Fast evaluation of Bounded Slice-line Grid (2004) (2)
FPGA global routing architecture optimization using a multicommodity flow approach (2007) (2)
Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs) (2021) (2)
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling (2010) (2)
Exploring Cardioneural Signals from Noninvasive ECG Measurement (2007) (2)
General Floorplans with L/T-Shaped Blocks Using Corner Block List (2006) (2)
Floorplanning with consideration of white space resource distribution for repeater planning (2005) (2)
Arnoldi algorithms with structured orthogonalization (2020) (1)
Area efficient pipelined pseudo-exhaustive testing with retiming (1996) (1)
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph (2012) (1)
Solving the net matching problem in high-performance chip design (1996) (1)
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing (2021) (1)
Placement initialization via a projected eigenvector algorithm: late breaking results (2022) (1)
Interconnect and output driver modeling of high speed designs (1993) (1)
Power line communication for hybrid power/signal pin SOC design (2015) (1)
3D floorplan representations: Corner links and partial order (2016) (1)
Static timing analysis in vlsi design (2006) (1)
Buffer planning algorithm based on partial clustered floorplanning (2005) (1)
Boosting off-chip interconnects through power line communication (2016) (1)
A study of pipelined pseudo-exhaustive testing on VLSI circuits with feedback (1994) (1)
Tiger: a timing-driven gate array and standard cell layout system (1995) (1)
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order (2018) (1)
Exploring 3D power distribution network physics (2011) (1)
Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes (2021) (1)
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond (2017) (1)
Ultra-low power on-chip differential interconnects using high-resolution comparator (2012) (1)
Extending moment computation to 2-port circuit representations (1998) (1)
A non-contact biopotential sensing system with motion artifact suppression (2013) (1)
Performance constrained floorplanning based on partial clustering [IC layout] (2005) (1)
PAS: A stand alone placement annotation system for high speed designs (1993) (1)
Ratio of the Worst Case Noise and the Impedance of Power Distribution Network (2014) (1)
Proceedings of the 11th international workshop on System level interconnect prediction (2009) (1)
Linear Dropout Regulator based power distribution design under worst loading (2011) (1)
Assessment of Reinforcement Learning for Macro Placement (2023) (1)
EARLY FEASIBILITY AND COST ASSESSMENT FOR MULTICHIP MODULE TECHNOLOGIES (1995) (1)
VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation (2001) (1)
Parallel full-chip transient simulation at transistor level (2008) (1)
Power grid sizing via convex programming (2011) (1)
A Parallel-in-Time Circuit Simulator for Power Delivery Networks with Nonlinear Load Models (2020) (1)
Efficient power network analysis with complete inductive modeling (2009) (1)
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation (2021) (1)
Resting‐state magnetoencephalography source magnitude imaging with deep‐learning neural network for classification of symptomatic combat‐related mild traumatic brain injury (2021) (1)
Power distribution network design optimization with on-die voltage-dependent leakage path (2013) (1)
Worst-case noise area prediciton of on-chip power distribution network (2014) (1)
Session details: Multicore and embedded SoC design (2011) (0)
Title A block-diagonal structured model reduction scheme for powergrid networks (2011) (0)
An O(nloglogn) algorithm for evaluation of Bounded Slice-line Grid (2003) (0)
Minimizing the worst-case voltage noise for power distribution network using time-varying equivalent serial resistance (2013) (0)
Contemporary data path design optimization (2006) (0)
Hurwitz Interconnect Delay Evaluation - HIDE: Programmer''s Manual (2000) (0)
Hurwitz Interconnect Delay Evaluation - HIDE: User''s Manual (2000) (0)
Globally stable, highly parallelizable fast transient circuit simulation via faber series (2012) (0)
Theory and Algorithms of Physical Design (2018) (0)
Empirical Study of Block Placement by Cluster Refinement (1999) (0)
An algebraic multigrid solver for analytical placement without layout based clustering (2003) (0)
Timing optimization for multi-source nets (1997) (0)
Electrical Engineering (Computer Engineering) (2008) (0)
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning (2014) (0)
The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings (2009) (0)
2006IEEEElectrical Performance ofElectronic Packaging Distortion Minimization for PackagingLevel Interconnects (2006) (0)
Integrated algorithmic logical and physical design of integer multiplier (2005) (0)
A higher-order moment model for multiport circuits (1999) (0)
A cell-based hierarchical pitchmatching compaction using minimal LP (1995) (0)
On-chip interconnect architectures: perspectives of layout, circuits, and systems (2006) (0)
Monolithic 3D Semiconductor Footprint Scaling Exploration based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform (2022) (0)
Author/Panelist Index (1995) (0)
Placement and beyond in honor of Ernest S. Kuh (2011) (0)
Cost Effectiveness Index (2014) (0)
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs (2022) (0)
Generalized volterra series model for highly nonlinear optical interconnects, circuits and devices (2007) (0)
An Algebraic Multigrid Solver for Analytical with Layout Based Clustering Placement (2003) (0)
Eecient Boolean Division and Substitution (1998) (0)
Boosting off-chip interconnects through chip-to-chip capacitive coupled communication (2017) (0)
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints (2023) (0)
A multi-level transmission line network approach for multi-giga hertz clock distribution (2005) (0)
Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders (2009) (0)
Floorplan Representations : Corner Links and Partial Order (2016) (0)
Session details: New approaches to physical design problems (2005) (0)
Solving the Net Matching Pro erforrnance Chip Desi (1996) (0)
Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs (2020) (0)
Title Circuit simulation via matrix exponential method for stiffnesshandling and parallel processing (2012) (0)
Physical planning of vlsi layout (2005) (0)
Desig nMethodolog yo fHig hPerformanc eOn-Chi pGloba lInterconnect Using Terminated Transmission-Line (2009) (0)
A fast time‐domain EM–TCAD coupled simulation framework via matrix exponential with stiffness reduction (2016) (0)
Block-oriented programmable design with switching network interconnect (1994) (0)
Topological circuit reduction: theory and applications (2003) (0)
A compact algorithm for placement design using corner block list representation (2001) (0)
Finite state machine partitioning for I/O-limited design (1995) (0)
PAPER Special Section on VLSI Design and CAD Algorithms Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration (2008) (0)
CAD transactions best paper award "Floorplanning using a tree representation" (2002) (0)
Title A fast time-domain EM-TCAD coupled simulation framework viamatrix exponential (2012) (0)
An unconditional stable general operator splitting method for transistor level (2006) (0)
A a Theoretical al Solutio (1996) (0)
Session details: Low power design for FPGAs (2005) (0)
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation (2000) (0)
Floorplanning algorithms for vlsi physical design automation (2000) (0)
Session details: Session 1C: Interconnect planning (2001) (0)
Fast adders in modern FPGAs (2004) (0)
Performance driven multiple-source bus synthesis using buffer insertion (1995) (0)
Reconfigurable Computing (2017) (0)
AD-A 275 896 Annual Progress Report 1 i 1 i 1 hu 10 for Design and Packaging of Fault Tolerant Optoelectronic Multiprocessor Computing System (0)
Application Multiple-Level Partitioning: An the Very Large-scale Hardware Simulator (1991) (0)
Two-stage newton–raphson method for transistor-level simulation (2007) (0)
An All-Digital Built-in Self-Test Circuit for ADPLLs in 65nm CMOS Technology (2018) (0)
Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation (2022) (0)
Adaptive Sensitivity Analysis with Nonlinear Power Load Modeling (2018) (0)
Module Placement Based on Resistive Net- Work Optimization. Ieee Transactions on 4.2 Normalizing the Weight Values (1997) (0)
Floorplan and placement approaches for vlsi physical design (1998) (0)
Session details: Floorplanning (2004) (0)
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization (2022) (0)
Research on floorplanning (2001) (0)
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? (2005) (0)
ROAD (2019) (0)
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis (2022) (0)
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation (2022) (0)
SAT-Based On-Track Bus Routing (2021) (0)

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