Chung Laung Liu
#12,315
Most Influential Person Now
Taiwanese computer scientist
Chung Laung Liu's AcademicInfluence.com Rankings
Chung Laung Liuengineering Degrees
Engineering
#504
World Rank
#851
Historical Rank
Electrical Engineering
#251
World Rank
#288
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Chung Laung Liucomputer-science Degrees
Computer Science
#1589
World Rank
#1644
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Parallel Computing
#28
World Rank
#28
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Computer Architecture
#38
World Rank
#39
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Database
#729
World Rank
#764
Historical Rank
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Engineering Computer Science
Chung Laung Liu's Degrees
- Bachelors Electrical Engineering National Taiwan University
Why Is Chung Laung Liu Influential?
(Suggest an Edit or Addition)According to Wikipedia, Chung Laung Liu , also known as David Liu or C. L. Liu, was a Taiwanese computer scientist. Born in Guangzhou, he spent his childhood in Macau. He received his B.Sc. degree in Taiwan, master's degree and doctorate in United States.
Chung Laung Liu's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment (1989) (10009)
- On a Real-Time Scheduling Problem (1978) (652)
- A New Algorithm for Floorplan Design (1986) (538)
- Simulated Annealing for VLSI Design (1988) (231)
- Coupling-driven signal encoding scheme for low-power interface design (2000) (185)
- Minimum crosstalk channel routing (1993) (170)
- Novel bioseparations using two-phase aqueous micellar systems. (2000) (147)
- Separation of proteins and viruses using two-phase aqueous micellar systems. (1998) (126)
- Protein partitioning in two-phase aqueous nonionic micellar solutions (1992) (93)
- A scheduling algorithm for conditional resource sharing (1991) (92)
- Low power realization of finite state machines—a decomposition approach (1996) (86)
- On a Periodic Maintenance Problem (1983) (85)
- Over-the-cell channel routing (1988) (84)
- Minimum fault coverage in reconfigurable arrays (1988) (79)
- Phase separation in aqueous solutions of lens gamma-crystallins: special role of gamma s. (1996) (74)
- Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems (1974) (74)
- A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach (1994) (73)
- Minimum Crosstalk Switchbox Routing (1994) (66)
- Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines (1991) (63)
- General models and algorithms for over-the-cell routing in standard cell design (1990) (54)
- Computer-aided development of a high-performance liquid chromatographic method for the determination of hydroxyanthraquinone derivatives in Chinese herb medicine rhubarb. (1999) (52)
- A new performance driven placement algorithm (1991) (52)
- A performance driven macro-cell placement algorithm (1992) (49)
- Optimal clock period clustering for sequential circuits with retiming (1997) (49)
- Linear systems analysis (1974) (49)
- A new approach to three- or four-layer channel routing (1988) (48)
- Area minimization for floorplans (1995) (46)
- Utilization of Multiport Memories in Data Path Synthesis (1993) (46)
- A new approach to the pin assignment problem (1988) (41)
- On a Class of Scheduling Algorithms for Multiprocessors Computing Systems (1974) (41)
- Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks (1989) (40)
- SIMULATED-ANNEALING CHANNEL ROUTER. (1985) (39)
- A reversible optode membrane for picric acid based on the fluorescence quenching of pyrene. (1993) (39)
- A Personnel Assignment Problem (1984) (38)
- Determination of gastrodin,p-hydroxybenzyl alcohol, vanillyl alcohol,p-hydroxylbenzaldehyde and vanillin in tall gastrodia tuber by high-performance liquid chromatography (2002) (37)
- On the k-layer planar subset and topological via minimization problems (1991) (34)
- Crosstalk minimization using wire perturbations (1999) (33)
- Low power logic synthesis for XOR based circuits (1997) (32)
- A postprocessing algorithm for crosstalk-driven wire perturbation (2000) (31)
- NEW APPROACH TO THE THREE LAYER CHANNEL ROUTING PROBLEM. (1987) (30)
- Floorplan design of VLSI circuits (1989) (29)
- Optimal clock period FPGA technology mapping for sequential circuits (1996) (29)
- Compacted channel routing with via placement restrictions (1986) (29)
- Area minimization for hierarchical floorplans (1994) (28)
- Routing for symmetric FPGAs and FPICs (1993) (26)
- Binary decision diagram with minimum expected path length (2001) (26)
- A technology mapping algorithm for CPLD architectures (2002) (25)
- Permutation Channel Routing (1988) (25)
- Aggregation in aqueous solutions of bovine lens gamma-crystallins: special role of gamma(s). (1998) (25)
- Optimal allocation of carry-save-adders in arithmetic optimization (1999) (23)
- FLOORPLAN DESIGN FOR RECTANGULAR AND L-SHAPED MODULES. (1987) (23)
- A Branch and Bound Algorithm for Optimal PLA Folding (1984) (22)
- A generalization of Ramsey theory for graphs (1978) (22)
- Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs (1996) (22)
- An algorithm for synthesis of system-level interface circuits (1996) (20)
- Optimization of the maximum delay of global interconnects duringlayer assignment (2001) (18)
- Low power logic synthesis under a general delay model (1998) (17)
- On the k-layer planar subset and via minimization problems (1990) (16)
- Compression-relaxation: A New Approach To Performance Driven Placement For Regular Architectures (1994) (16)
- A new approach to the multiport memory allocation problem in data path synthesis (1995) (16)
- Physical models and efficient algorithms for over-the-cell routing in standard cell design (1993) (15)
- Low power FPGA design—a re-engineering approach (1997) (15)
- Solid-phase microextraction from small volumes of sample in a glass capillary. (2003) (15)
- Routing for Symmetric FPGA's and FPIC's (1997) (14)
- Recent Results in Real-Time Scheduling (1991) (14)
- Implication graph based domino logic synthesis (1999) (14)
- Improvement in trimerization of acetylene to benzene for radiocarbon dating with a commercially available vanadium oxide catalyst (1972) (14)
- Optimal clock period FPGA technology mapping for sequential circuits (1998) (13)
- Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction (1998) (13)
- Area minimization for general floorplans (1992) (13)
- Fault covers in reconfigurable PLAs (1990) (12)
- A construction scheme for linear and non-linear codes (1973) (12)
- Constrained floorplan design for flexible blocks (1989) (11)
- An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem (1986) (11)
- Re-engineering of timing constrained placements for regular architectures (1995) (11)
- Optimal Scheduling on Multi-Processor Computing Systems (1972) (11)
- SS/TDMA satellite communications with k -permutation switching modes (1987) (10)
- Noise-aware power optimization for on-chip interconnect (2000) (10)
- Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance (1996) (10)
- Discretionary channel routing (1988) (10)
- An enhanced bottom-up algorithm for floorplan design (1989) (9)
- Solution of a module orientation and rotation problem (1990) (9)
- MULTIPLE PLA FOLDING BY THE METHOD OF SIMULATED ANNEALING. (1986) (9)
- Placement and placement driven technology mapping for FPGA synthesis (1993) (9)
- LC Determination of Podophyllum Lignans and Flavonoids in Podophyllum emodi Wall.var.chinesis Sprague (2006) (9)
- Coupling delay optimization by temporal decorrelation using dual threshold voltage technique (2001) (8)
- A timing-constrained incremental routing algorithm for symmetrical FPGAs (1996) (8)
- Register allocation for data flow graphs with conditional branches and loops (1993) (7)
- A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs (1996) (7)
- Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays (1995) (7)
- Timing-driven placement for regular architectures (1997) (7)
- Deterministic Job Scheduling in Computing Systems (1976) (7)
- Power invariant vector sequence compaction (1998) (7)
- Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture (1994) (7)
- A rapid method for the measurement of cholesterol thermodynamic activity in bile salt-lecithin-cholesterol solutions. (1993) (7)
- Noise-aware interconnect power optimization in domino logic synthesis (2003) (7)
- Optimal Graph Constraint Reduction for Symbolic Layout Compaction (1993) (7)
- A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (2000) (6)
- Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs (1995) (6)
- Two-dimensional layout compaction by simulated annealing (1988) (6)
- A performance driven hierarchical partitioning placement algorithm (1993) (6)
- A new formulation of yield enhancement problems for reconfigurable chips (1988) (5)
- Permutation Representation of k-Ary Trees (1985) (5)
- Performance analysis of multiprocessor systems containing functionally dedicated processors (1978) (5)
- Fault covering problems in reconfigurable VLSI systems (1992) (5)
- G-vector: A New Model for Glitch Analysis in Logic Circuits (2001) (5)
- Array Optimization for VLSI Synthesis (1987) (5)
- Domino logic synthesis based on implication graph (2002) (5)
- Generalized latin squares I (1989) (5)
- Equilibrium dialysis studies on aqueous taurocholate-lecithin solutions: further validation of the method. (1990) (5)
- A stepwise refinement synthesis of digital systems for testability enhancement (1999) (5)
- Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation (1996) (4)
- An efficient data path synthesis algorithm for behavioral-level power optimization (1999) (4)
- An area minimizer for floorplans with L-shaped regions (1992) (4)
- Disjoint Covers in Replicated Heterogeneous Arrays (1991) (4)
- Synthesis and Optimization of Combinational Interface Circuits (2002) (4)
- Analysis of sorting algorithms (1971) (3)
- Timing-based placement for an FPGA design environment (1994) (3)
- (g 0, g 1, ... g k)-Trees and Unary OL Systems (1983) (3)
- A drum scheduling algorithm (1973) (3)
- A complete model for glitch analysis in logic circuits (2000) (3)
- A delay driven FPGA placement algorithm (1994) (3)
- PLA logic minimization by simulated annealing (1990) (3)
- An Integer Linear Programming Approach to General Fault Covering Problems (1990) (3)
- Generation of trees (1980) (3)
- Desensitization for power reduction in sequential circuits (1996) (3)
- Analysis and Synthesis of Sorting Algorithms (1972) (3)
- Fundamentals of Real-Time Scheduling (Extended Abstract) (1992) (3)
- Partial Scan with Pre-selected Scan Signals (1995) (3)
- A General Model for Fault Covering Problems in Reconfigurable Arrays (1989) (2)
- Sperner's theorem on maximal-sized antichains and its generalization (1975) (2)
- A channel router for single layer customization technology (1991) (2)
- Logic transformation for low-power synthesis (2002) (2)
- Algorithms for permutation channel routing (1987) (2)
- Scheduling with slack time (1982) (2)
- Register Allocation—A Hierarchical Reduction Approach (1998) (2)
- Partial Scan with Preselected Scan Signals (1999) (2)
- The retiming of single-phase clocked circuits containing level-sensitive latches (1999) (2)
- Sequence Compaction to Preserve Transition Frequencies (2002) (1)
- Compacting sequences with invariant transition frequencies (2003) (1)
- Issues in the Imprecise Computation Approach to Fault Tolerance (1991) (1)
- Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits (1997) (1)
- Symbolic Techniques for Optimal Scheduling 1 (1)
- An integrated algorithm for incremental data path synthesis (1996) (1)
- A New Approach to Three- or (1988) (0)
- From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years (1999) (0)
- An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization (2000) (0)
- Research in Complexity Theory and Combinatorial Algorithms (1980) (0)
- Power optimization of multi-level logic circuits utilizing circuit symmetries (2000) (0)
- Fault Covers in Heterogeneous and General Arrays (1992) (0)
- Minimum fault covering in reconfigurable arrays (1991) (0)
- General Formulation of Fault Covering Problems (1992) (0)
- Prototyping Environ-Chapter 7 : PERTS : A Prototyping Environment for Real-Time Systems (2012) (0)
- Making: Detecting Land Mines with Neural Networks Using Separated Aperture Sensor Data Collected at 4 Annealing Schedules for a Real- World Perceptron Network 3 Cooling Reconsidered (1993) (0)
- 12. VLSI layout synthesis (2003) (0)
- Fault Covers in Rectangular Arrays (1992) (0)
- Modeling and synthesis of combinational logic circuits: a power dissipation perspective (1998) (0)
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