Daniel Gajski

Q: What Schools Are Affiliated With Daniel Gajski

Daniel Gajski is affiliated with the following schools: University of California, Berkeley, University of California, Irvine, University of Illinois Urbana-Champaign, University of Zagreb, University of Pennsylvania

Daniel Gajski's AcademicInfluence.com Rankings

Daniel Gajski

Computer Science

#2372

World Rank

#2477

Historical Rank

#1052

USA Rank

Computer Architecture

#34

World Rank

#35

Historical Rank

#22

USA Rank

Database

#2241

World Rank

#2356

Historical Rank

#511

USA Rank

computer-science Degrees

Daniel Gajski

Engineering

#2001

World Rank

#2816

Historical Rank

#697

USA Rank

Electrical Engineering

#674

World Rank

#737

Historical Rank

#191

USA Rank

engineering Degrees

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Computer Science
Engineering

Daniel Gajski's Degrees

PhD Electrical Engineering University of California, Berkeley
Masters Electrical Engineering University of California, Berkeley
Bachelors Electrical Engineering University of California, Berkeley

Why Is Daniel Gajski Influential?

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According to Wikipedia, Daniel Gajski is a Professor of the School of Information and Computer Science and the School of Engineering at University of California, Irvine, United States. He was previously the Director for the Center for Embedded Computer Systems , now known as the Center for Embedded and Cyber-physical Systems.

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Daniel Gajski's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

High ― Level Synthesis: Introduction to Chip and System Design (1992) (1173)
Hypertool: A Programming Aid for Message-Passing Systems (1990) (724)
Specification and Design of Embedded Systems (1998) (647)
Transaction level modeling: an overview (2003) (632)
SPECC: Specification Language and Methodology (2000) (491)
Introduction to high-level synthesis (1994) (309)
An Introduction to High-Level Synthesis (2009) (232)
Principles of Digital Design (1996) (218)
CEDAR: a large scale multiprocessor (1983) (209)
A Second Opinion on Data Flow Machines and Languages (1982) (197)
RTOS modeling for system level design (2003) (193)
Specification and Design of Embedded Hardware-Software Systems (1995) (192)
Embedded System Design: Modeling, Synthesis and Verification (2013) (192)
Electronic System-Level Synthesis Methodologies (2009) (181)
Design Tools for Intelligent Silicon Compilation (1987) (166)
System Design - A Practical Guide with SpecC (2001) (143)
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning (1994) (142)
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design (2008) (141)
Percolation based synthesis (1990) (138)
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design (1998) (133)
Specification partitioning for system design (1992) (123)
Cycle-approximate Retargetable Performance Estimation at the Transaction Level (2008) (110)
An American National Standard- IEEE Standard for Binary Floating-Point Arithmetic (1985) (102)
Essential Issues in Multiprocessor Systems (1985) (99)
Synthesis from VHDL (1988) (97)
Flow Graph Representation (1986) (94)
Chippe: a system for constraint driven behavioral synthesis (1990) (93)
Interfacing Incompatible Protocols Using Interface Process Generation (1995) (93)
An algorithm for array variable clustering (1994) (92)
A system-design methodology: executable-specification refinement (1994) (89)
High-Level Transformations for Minimizing Syntactic Variances (1993) (88)
A retargetable, ultra-fast instruction set simulator (1999) (81)
Transaction Level Modeling in System Level Design (2003) (80)
Essential issues for IP reuse (2000) (80)
Synthesis of system-level bus interfaces (1994) (79)
Incremental hardware estimation during hardware/software functional partitioning (1995) (77)
System specification and synthesis with the SpecCharts language (1991) (69)
SpecCharts: a VHDL front-end for embedded systems (1995) (68)
Clustering for improved system-level functional partitioning (1995) (68)
System-level abstraction semantics (2002) (61)
Retargetable profiling for rapid, early system-level design space exploration (2004) (61)
LES: A Layout Expert System (1987) (60)
SpecCharts : A Language for System Level Synthesis (1991) (59)
A cycle-accurate compilation algorithm for custom pipelined datapaths (2005) (56)
An algorithm for component selection in performance optimized scheduling (1991) (56)
An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines (1981) (54)
An effective methodology for functional pipelining (1992) (53)
A Programming Aid for Message-passing Systems (1987) (52)
Partitioning and pipelining for performance-constrained hardware/software systems (1999) (52)
A transformation-based method for loop folding (1994) (50)
Layout-area models for high-level synthesis (1991) (50)
System specification with the SpecCharts language (1992) (49)
Embedded software generation from system level design languages (2004) (48)
Software estimation from executable specifications (1994) (47)
Essential Issues in Codesign (1997) (47)
Syntax and Semantics of the SpecC Language (1997) (47)
An Expert-System Paradigm for Design (1986) (46)
Knowledge Based Control in Micro-Architecture Design (1987) (46)
System clock estimation based on clock slack minimization (1992) (45)
RTOS scheduling in transaction level models (2003) (45)
Design of a GSM Vocoder using SpecC Methodology (1999) (44)
Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths (2005) (44)
Closeness metrics for system-level functional partitioning (1995) (43)
Accurate layout area and delay modeling for system level design (1992) (43)
The SpecC Language Reference Manual (1998) (42)
System-level communication modeling for network-on-chip synthesis (2005) (41)
New VLSI Tools - Guest Editors' Introduction (1983) (41)
Automatic communication refinement for system level design (2003) (41)
Embedded tutorial: essential issues for IP reuse (2000) (40)
An ultra-fast instruction set simulator (2002) (39)
Translating system specifications to VHDL (1991) (38)
IP-Centric Methodology and Design with the SpecC Language (1999) (35)
SpecC Technology Open Consortium (2001) (33)
Protocol Generation for Communication Channels (1994) (33)
System-level exploration with SpecSyn (1998) (33)
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models (2007) (33)
Timing models for high-level synthesis (1992) (33)
Comparison of SpecC and SystemC Languages for System Design (2003) (32)
A memory selection algorithm for high-performance pipelines (1995) (32)
Implementing flexible hybrid instruction in an electrical engineering course: The best of three worlds? (2015) (32)
A parallel pipelined relational query processor (1984) (32)
An intermediate representation for behavioral synthesis (1990) (32)
DEPENDENCE DRIVEN COMPUTATION. (1981) (31)
Condition Graphs For High-quality Behavioral Synthesis (1994) (31)
Automatic Model Refinement for Fast Architecture Exploration (2002) (31)
The Specc Methodology (2000) (30)
Area and performance estimation from system-level specifications (1992) (30)
Component selection for high-performance pipelines (1996) (29)
Model Refinement for Hardware-Software Codesign (1996) (29)
Design of Testable Structures Defined by Simple Loops (1981) (28)
Hardware/software Partitioning And Pipelining (1997) (28)
Automatic generation of transaction level models for rapid design space exploration (2006) (28)
Automatic architecture refinement techniques for customizing processing elements (2008) (28)
FPGA-friendly code compression for horizontal microcoded custom IPs (2007) (27)
System design methodologies: aiming at the 100 h design cycle (1996) (26)
SLIF: a specification-level intermediate format for system design (1995) (26)
Soft scheduling in high level synthesis (1999) (26)
A Heuristic for Suffix Solutions (1986) (26)
MILO: a microarchitecture and logic optimizer (1988) (25)
VHDL Synthesis Using Structured Modeling (1989) (25)
SpecC Methodology for High-Level Modeling (2002) (24)
Features supporting system-level specification in HDLs (1993) (24)
A scheduling and pipelining algorithm for hardware/software systems (1997) (24)
Design of a JPEG Encoding System (1999) (23)
Design Methodology for High-Level Synthesis (1992) (23)
A programming aid for hypercube architectures (1988) (22)
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors (2007) (22)
Software estimation using a generic-processor model (1995) (21)
Parallel Compressors (1980) (21)
Specify-Explore-Refine (SER): From specification to implementation (2008) (21)
Assignment Decision Diagram for High-Level Synthesis (1992) (20)
Custom processor design using NISC: a case-study on DCT algorithm (2005) (20)
Performance evaluation for application-specific architectures (1995) (20)
What input-language is the best choice for high level synthesis (HLS)? (2010) (20)
Interface Synthesis from Protocol Specification (2002) (19)
NISC: The Ultimate Reconfigurable Component (2003) (19)
An intelligent component database for behavioral synthesis (1990) (19)
Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs (2006) (19)
Designer Controlled Behavioral Synthesis (1989) (18)
Automatic generation of bus functional models fromtransaction level models (2004) (18)
100-hour design cycle: a test case (1994) (17)
Architectural exploration for datapaths with memory hierarchy (1995) (17)
System Design Methodology and Tools (2003) (17)
Linking Register-Transfer and Physical Levels of Design (Special Issue on Synthesis and Verification of Hardware Design) (1993) (17)
A formalism for functionality preserving system level transformations (2005) (17)
Custom Processor Core Construction from C Code (2008) (16)
SpecC System-Level Design Methodology Applied to the Design of a GSM Vocoder (2000) (16)
Top-down system level design methodology using SpecC, VCC and SystemC (2002) (16)
Minimizing Syntactic Variance with Assignment Decision Diagrams (1992) (16)
Automatic TLM Generation for Early Validation of Multicore Systems (2011) (16)
Component synthesis from functional descriptions (1993) (16)
Specification and Design of Embedded Software/Hardware Systems (1995) (16)
IP-based design methodology (1999) (16)
Verification of System Level Model Transformations (2006) (16)
Component selection in resource shared and pipelined DSP applications (1996) (15)
Fast Execution of Loops with IF Statements (1984) (15)
A unified formal model of ISA and FSMD (1999) (15)
Design synthesis and silicon compilation (1990) (14)
Functional synthesis using area and delay optimization (1992) (13)
The component synthesis algorithm: technology mapping for register transfer descriptions (1990) (13)
Interface synthesis for heterogeneous multi-core systems from transaction level models (2007) (13)
A component selection algorithm for high-performance pipelines (1994) (13)
Model refinement for hardware-software codesign (1996) (13)
CAMP: A Programming Aide for Multiprocessors (1986) (13)
Youn-Long Steve Lin (1992) (13)
Performance-constrained hierarchical pipelining for behaviors, loops, and operations (2001) (13)
Automatic network generation for system-on-chip communication design (2005) (13)
Embedded system environment: A framework for TLM-based design and prototyping (2010) (13)
No-instruction-set-computer (nisc) technology modeling and compilation (2007) (12)
System-On-Chip Component Models (2003) (12)
Reuse and protection of intellectual property in the SpecC system (2000) (12)
An efficient multi-view design model for real-time interactive synthesis (1992) (12)
Exel: A language for interactive behavioral synthesis (1988) (12)
Accurate timed RTOS model for transaction level modeling (2010) (12)
Functional Unit (1996) (11)
Top-down modeling of RISC processors in VHDL (1993) (11)
Automatic generation of equivalent architecture model from functional specification (2004) (11)
A performance evaluator for parameterized ASIC architectures (1994) (11)
OpenJ: an extensible system level design language (1999) (11)
Layout placement for sliced architecture (1992) (11)
Multi-metric and multi-entity characterization of applications for early system design exploration (2005) (11)
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs (2008) (11)
Partitioning algorithms for layout synthesis from register-transfer netlists (1990) (11)
Clock-driven performance optimization in interactive behavioral synthesis (1996) (11)
Synthesis of functions and procedures in behavioral VHDL (1993) (11)
An optimal clock period selection method based on slack minimization criteria (1996) (11)
A design process model (1992) (10)
A case study to develop a graduate-level degree program in embedded & cyber-physical systems (2017) (10)
Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontal-Microcoded Architectures in Embedded Systems (2007) (10)
Transaction based design: another buzzword or the solution to a design problem? (2003) (10)
C-based design flow: A case study on G.729A for Voice over internet protocol (VoIP) (2008) (10)
Towards Intelligent Silicon Compilation (1987) (10)
Silicon compilation from register-transfer schematics (1990) (10)
Automatic Data Path Generation from C code for Custom Processors (2007) (10)
Estimation and exploration automation of system level design (2004) (9)
A transformation for integrating VHDL behavioral specification with synthesis and software generation (1994) (9)
Generic netlist representation for system and PE level design exploration (2006) (9)
A novel memory size model for variable-mapping in system level design (2004) (9)
A parallel pipelined relational query processor: An architectural overview (1989) (9)
Introduction of system level architecture exploration using the SpecC methodology (2001) (9)
RTL semantics and methodology (2001) (9)
An approach to component generation and technology adaptation (1991) (8)
Automatic model refinement for fast architecture exploration [SoC design] (2002) (8)
NISC Technology and Preliminary Results (2005) (8)
Semantics and synthesis of signals in behavioral VHDL (1992) (8)
Compiling SpecC for simulation (2001) (8)
Designing a custom architecture for DCT using NISC technology (2006) (8)
Cell Compilation with Constraints (1984) (8)
GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors (2008) (8)
Functional validation of system level static scheduling (2005) (8)
Structured modeling for VHDL synthesis (1989) (8)
Introduction of Design-Oriented Profiler of SpecC Language (2002) (8)
Clock optimization for high-performance pipelined design (1996) (8)
Programming environments for multiprocessors (1987) (8)
Modeling flow for automated system design and exploration (2004) (8)
Automatic Design with Dependence Graphs (1980) (8)
Computer-aided programming for message-passing systems: problems and solutions (1989) (8)
Decomposition of Logic Networks into Silicon (1985) (8)
Co-design of emulators for power electric processes using SpecC methodology (2002) (7)
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications (2010) (7)
Improving parallel program performance using critical path analysis (1990) (7)
Bringing in-class online - A hybrid solution (2014) (7)
Embedded Systems Education: How to Teach the Required Skills? (2004) (7)
Hardware-dependent Software synthesis for many-core embedded systems (2009) (7)
SpecCharts : a language for system level specification and synthesis (1990) (7)
A new algorithm for transistor sizing in CMOS circuits (1990) (7)
Automatic Generation of Communication Architectures (2005) (7)
A Graph Based Algorithm for Data Path Optimization in Custom Processors (2006) (7)
Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor (1982) (6)
Designing a Custom Architecture for DCT Using NISC Design Flow (2005) (6)
BIF : a behavioral intermediate format for high level synthesis (1989) (6)
C/C++ Based System Design Flow using SpecC, VCC and SystemC (2003) (6)
RT level power analysis (1997) (6)
RTOS Modeling in System Level Synthesis (2002) (6)
Codesign Methodology of Real-time Embedded Controllers for Electromechanical Systems (2005) (6)
Architectural tradeoffs in synthesis of pipelined controls (1993) (6)
The role of learning in logic synthesis (1989) (6)
A Hardware-Software Partitioning Algorithm for Minimizing Hardware (1993) (6)
System design extreme makeover (2005) (6)
Embedded systems education: how to teach the required skills? (2004) (6)
Automated Generation of Custom Processor Core from C Code (2012) (5)
Essential Issues and Possible Solutions in High-Level Synthesis (1991) (5)
System Level Verification with Model Algebra (2004) (5)
Queue Generation Algorithm for Interface Synthesis (2002) (5)
Optimal message-passing for data coherency in distributed architecture (2002) (5)
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms (2007) (5)
Obtaining functionally equivalent simulations using VHDL and a time-shift transformation (1991) (5)
Software synthesis for system-on-chip (2005) (5)
Automatic Generation of Cells for Recurrence Structures (1981) (5)
Design and implementation of transducer for ARM-TMS communication (2006) (5)
Generation of Custom Co-processor Structure from C-Code (2008) (4)
Low-Power Design with NISC Technology (2007) (4)
Automatic Software Generation for System Level Design (2003) (4)
A Design Methodology and Environment for Interactive Behavioral Synthesis (1996) (4)
Synthesis from VHDL : Rockwell-counter case study (1990) (4)
Automating technology adaptation in design synthesis (1989) (4)
Defining an enhanced RTL semantics (2005) (4)
System-on-Chip Communication Modeling Style Guide (2004) (4)
Constant-time cost evaluation for behavioral partitioning (1992) (4)
Comparison of the Scenic Design Environment and the SpecC System (1998) (4)
SLAM : an automated structure to layout synthesis system (1989) (4)
Communication Link Synthesis for SoC (2004) (4)
Functional verification of system level model refinements (2005) (4)
The Specification Language SpecC within the PARADISE Design Environment (2000) (4)
Channel Mapping in System Level Design (2003) (4)
Silicon Compilers and Expert Systems for VLSI (1984) (4)
Formal Verification of Specification Partitioning (2003) (4)
A technique for pull-up transistor folding (1988) (4)
Synthesis from specifications : basic concepts (1990) (4)
A decision support environment for behavioral synthesis (1991) (4)
The SpecSyn Design Process and Human Interface (1993) (4)
Design Space Exploration for The Beamformer System (1993) (4)
Rapid prototyping with HW/SW codesign tool (1999) (4)
Accessing sparse arrays in parallel memories (1983) (3)
Silicon compilation of switched-capacitor networks (1990) (3)
Variable Mapping of System Level Design (2002) (3)
Model Based Synthesis of Embedded Software (2008) (3)
System-On-Chip Network Modeling Style Guide (2004) (3)
High-speed modulo-3 generator (1977) (3)
Glue-logic partitioning for floorplans with a rectilinear datapath (1991) (3)
On deriving equivalent architecture model from system specification (2004) (3)
An algorithm for generation of behavioral shape functions (1994) (3)
Specification and validation of new control algorithms for electric drives using SpecC language (2002) (3)
ent Selection in R rce Shared and elined t (1996) (3)
Synthesis and optimization of low-power custom nisc processors (2007) (3)
Recurrence semigroups and their relation to data storage in fast recurrence solvers on parallel machines (1981) (3)
A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs (2007) (3)
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis (2000) (3)
Co-design of embedded controllers for power electronics and electric systems (2002) (3)
New Strategies for System Level Design (2006) (3)
Computer architecture, tutorial (1987) (3)
IP-Centric Methodology and Specification Language (1998) (3)
System-On-Chip Architecture Modeling Style Guide (2004) (3)
System-level synthesis: From specification to transaction level models (2009) (3)
Provably Correct Architecture Refinement (2003) (3)
Design of arithmetic elements for Burroughs Scientific Processor (1978) (3)
Design process beyond ASICs (1993) (3)
Software and Driver Synthesis from Transaction Level Models (2005) (3)
Modeling a new RTL semantics in C++ (2002) (2)
Performance optimization in layout driven synthesis (1989) (2)
C-based Interactive RTL Design Methodology (2004) (2)
NISC Application and Advantages (2004) (2)
TLM: Crossing Over From Buzz To Adoption (2007) (2)
SpecC design environment (2001) (2)
NISC Modeling and Simulation (2004) (2)
Hypertool: A Programming Aid for Multicomputers (1989) (2)
System-level automatic model refinement (2004) (2)
CHASSIS : a combined hardware selection and scheduling technique for performance driven synthesis (1991) (2)
Methodology is the future (1996) (2)
System Level Specification and Synthesis (1992) (2)
VHDL Synthesis System (VSS) User's Manual Version 5.0 (1992) (2)
Comparison of five multiprocessor systems (1985) (2)
Toward computer-aided programming for multiprocessors (1986) (2)
Hierarchical pipelining for behaviors, loops, and operations (1998) (2)
Design of a MP 3 Decoder using the System-On-Chip Environment ( SCE ) (2007) (2)
Arrays for generating arbitrary mask vectors (1975) (2)
Switched-capacitor silicon compiler (1988) (2)
Technology mapping for register transfer descriptions (1989) (2)
The next HDL (panel session): if C++ is ;the answer, what was the question? (2001) (2)
A clustering technique to optimize hardware/software synchronization (2005) (1)
Algorithmic Layout of Gate Macros (1981) (1)
Grouping-Based Architecture Exploration of System-Level Design (2003) (1)
Gajski Principles Of Digital Design (2015) (1)
Improving a PLA Area by Pull-Up Transistor Folding (1987) (1)
Computer-Aided Synthesis of Data-Path by using a Simulated-Annealing-based approach (1991) (1)
Behavioral modeling of the Intel 8255A/8255A-5 programmable peripheral interface (1991) (1)
Design Exploration For High-performance Pipelines (1994) (1)
System Design Methodologies (2009) (1)
Clock Optimization for High-performance Pipelined Design Clock Optimization for High-performance Pipelined Design (1996) (1)
Specc lan-guage reference manual (2002) (1)
IP-Centric Methodology (1)
Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . (2006) (1)
System design based on C/C++: what is needed and what is not (2003) (1)
Seamless approach for the design of control systems for power electronics and electric drives (2002) (1)
VSS : a VHDL synthesis system (1988) (1)
Automatic synthesis of CMOS operational amplifiers for a switched capacitor compiler (1990) (1)
Structural operational semantics for supporting multi-cycle operations in RTL HDLs (2005) (1)
AN INTERMEDIATE REPRESENTATLON FOR BEHAVIORAL SYNTHESIS (1990) (1)
Design Representation and Transformations (1992) (1)
VHDL design representation in the VHDL synthesis system (VSS) (1989) (1)
Layout-driven allocation for high level synthesis (1991) (1)
Partitioning Algorithms for Layout Synthesis (1990) (1)
Model validation for mapping specification behaviors to processing elements (2004) (1)
Power routing in channelless floorplan layouts (1989) (1)
A Connection-oriented Binding Model for Binding Algorithms (1996) (1)
The design process of behavioral synthesis from VHDL (1994) (1)
Scheduling in RTL Design Methodology (2000) (1)
Automatic design and optimization of processor data path and memory hierarchy (2009) (1)
Back-annotation for interactive data path synthesis (1991) (1)
Transaction level model based performance estimation and system generation (2010) (1)
The Guidelines and JPEG Encoder Study Case of System Level Architecture Exploration Using the SpecC Methodology (2002) (1)
Interactive Behavioral Synthesis from VHDL (1993) (1)
Computer-aided programming for multiprocessing systems (1988) (1)
EXTEND-L : an input language for extensible register transfer compilation (1988) (1)
Automatic synthesis of analog and sampled-data circuits in CMOS technology (1990) (1)
NISC Modeling and Compilation (2004) (1)
Architectural Models in Synthesis (1992) (1)
Network Synthesis for SoC (2004) (1)
Hardware/software co-design for pipelined systems (1996) (1)
Symbolic Techniques for Optimal Scheduling 1 (1)
Microprocessor Synthesis (1984) (1)
Practical Design Verification: Transaction-level system modeling (2009) (1)
Panel: Opportunities and pitfalls in HDL-based system design (1996) (1)
Effects of mixing design styles on the synthesis of RTL components (1991) (1)
System Debugging and Verification : A New Challenge (2003) (1)
Specification Tuning of System-Level Design (2002) (1)
BDEF : the behavioral design data exchange format (1991) (1)
System Level Design: Past, Present, and Future (2008) (1)
Rapid performance estimation for system design (1996) (0)
VLSI Design and ASPDAC Technical Program Committee (2002) (0)
One-week prototyping of embedded systems (2005) (0)
FOREWORD (Special Issue on Synthesis and Verification of Hardware Design) (1996) (0)
Microarchitecture optimization for timing and layout (1991) (0)
FINITE-STATE MACHINE, ALGEBRAIC, AND TESSELLATION SEMIAUTOMATA CHARACTERIZATION OF STRICTLY K-TESTABLE LANGUAGES. (1975) (0)
A System-level Modelling, Analysis and Synthesis of Embedded Multi-core Designs Organiser (2009) (0)
C01\1PUTER-AIDED PROGRA.l\1l\11NG FOR MULTIPROCESSING SYSTE1\1S (2015) (0)
System-Level Design: Designers' Wish List vs. Reality (1999) (0)
The rtl++ language, semantics, and program verification (2005) (0)
A new partitioning approach for layout synthesis from register-transfer netlists (1990) (0)
SpecC Methodology applied to the Design of Control systems for Power Electronics and Electric Drives (2001) (0)
Design Space Exploration of C Programs Using NISC: A Case-Study on DCT algorithm (2006) (0)
Were the good old days all that good?: EDA then and now (2004) (0)
A VHDL-based system-design methodology (1994) (0)
Pipelining of register transfer netlists (1991) (0)
Compact variability modeling to the rescue (2010) (0)
Algorithms for system synthesis (clock selection) (2000) (0)
Incorporating VHDL signal/wait semantics into synthesis (1992) (0)
Workshop: Silicon Compilers and Expert Systems for VLSI (1984) (0)
Transaction Routing and its Verification by Correct Model Transformations (2006) (0)
SpecC System-Level Design Methodology Applied to the Design of aGSM (2000) (0)
_Layout Placement for Sliced Architectur~ (2015) (0)
Essential Issues in System Level Design (2000) (0)
Parallelization Optimization of System-Level Specification (2002) (0)
Notice : This Material may be protected by Copyright Law ( Title 17 U . S . C . ) Back-Annotation for Interactive Data Path (2015) (0)
What will system level design be when it grows up? (2005) (0)
A quantitative analysis for optimizing memory allocation (1997) (0)
Technology and Preliminary Results (2005) (0)
What will system level design be when it grows up? (2005) (0)
One language or more?: how can we design an SoC at a system level? (2000) (0)
Design Synthesis and Tools for DSP (1993) (0)
Rapid Performa ation For System (1996) (0)
Classification of parallel processor architectures (invited tutorial session) (1985) (0)
New strategies for system design (2007) (0)
Design Description Languages (1992) (0)
Tutorial: Computer architecture (1986) (0)
System Design thodologies : iming at the 10 Design Cycle (1996) (0)
System Level Specificat ion and Synthesis (1991) (0)
Design of real-time emulators of electromechanical systems (2002) (0)
Interconnection Binding in RTL Design Methodology (2001) (0)
Introduction: System Level Design: Past, Present and Future (2008) (0)
Trace-Driven Performance Estimation of multi-core platforms (2014) (0)
Hierarchy-Aware mapping of pipelined applications (2014) (0)
Strategies for microarchitecture and logic optimization (1988) (0)
Session details: Panel (2010) (0)
Hardware-software exploration for system design (1995) (0)
SoC design for the new millennium (2003) (0)
Future Of ICCAD Teenage Years (1994) (0)
An~cient Multi-View Design Model for Real-Time Interactive Synthesi§__ (2015) (0)
Partitioning-based algorithm for pipelined scheduling and module assignment (1991) (0)
Embedded Design Practice (2009) (0)
1 ESSENTIAL ISSUES IN CODESIGN (0)
Session details: Embedded multiprocessor software synthesis (2011) (0)
Component reuse: characterization and interface generation (2000) (0)
IP-centric methodology and specification language: system level design of embedded systems (1998) (0)
Synthesis for Reuse (1998) (0)
CAD Profession Facts, Trends And Illusions (1994) (0)
HuffEnc AliasRed AliasRed IMDCT IMDCT ARM Mem PCM FilterCore HW 1 FilterCore HW 2 pcmBus HAL mainBus OS Drivers PCM . HuffEnc AliasRed AliasRed IMDCT IMDCT ARM Mem PCM FilterCore (0)
^SENTIAL ISSUES ^ AND POSSIBLE SOLUTIONS IN HIGH-LEVEL SYNTHESIS (2015) (0)
Benchmarking for high-level synthesis (1992) (0)
Technology mapping with layout constraints (1989) (0)
System Level Design With Specc (2000) (0)
Layout Area Models for ~~ High-Level Synthesi~ (2015) (0)
Driven Allocation < for High Level (2015) (0)
Session details: Memory-aware compiler techniques (2009) (0)
Methodologies and tools for system-level synthesis (1999) (0)
Function Binding in RTL Design Methodology (2001) (0)
A Tool for Functional Verification of System Level Model Refinements (2005) (0)
An exper-system paradigm for design (1988) (0)
A VLSI implementation of the collision avoidance switch protocol for CAMB tree LANs (1991) (0)
Communication synthesis for system-on-chip (2004) (0)
Title 17 U . S . C . ) VHDL Synthesis System ( VSS ) User ' s Manual Version 5 . 0 (2015) (0)
Transducer synthesis for heterogeneous multi-processor systems (2009) (0)
System-level Timing-constrained Scheduling (1998) (0)
The Specc Methodology the Specc Methodology (1999) (0)
Session details: TLM: crossing over from buzz to adoption (2007) (0)
Specify-explore-refine paradigm for system design (1996) (0)
Evaluation driven layout synthesis (1991) (0)
Benchmarking and the Art of Syntesis Tool Comparison (1992) (0)
Chairs and Committee Members (1997) (0)
Topic : Network and communication system Automatic Generation of Communication Architectures (0)
-12 - Unidraw: a Framework for Building Domain-specific Graphical (1994) (0)
Session details: System-level power management (2011) (0)
C/C ++: progress or deadlock in system-level specification (2001) (0)
The Beamformer System (2015) (0)
DESIGNER CONTR0LLED BEHAVIOFUL SMVTI-IESIS (1989) (0)
SW Generation from TL to PCA Level for MPSoC (0)
Fast shifting network with mask generator and rotating device (1977) (0)
Early performance-cost estimation of application-specific data path pipelining (2010) (0)
Software Performance Estimation for Toshiba TLCS-R3900 (1996) (0)
Sysiem Specification with he (1992) (0)

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