David J. Allstot

Q: What Schools Are Affiliated With David J. Allstot

David J. Allstot is affiliated with the following schools: University of California, Berkeley, Oregon State University, University of Portland, Stanford University, University of Texas at Dallas, University of Washington

David J. Allstot's AcademicInfluence.com Rankings

David J. Allstot

Engineering

#4389

World Rank

#5582

Historical Rank

#1102

USA Rank

Electrical Engineering

#2126

World Rank

#2231

Historical Rank

#286

USA Rank

engineering Degrees

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Engineering

David J. Allstot's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering University of California, Berkeley

Why Is David J. Allstot Influential?

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According to Wikipedia, David J. Allstot , is a professor of electrical and computer engineering at Oregon State University. His research includes work on analog, mixed-signal, and radio frequency integrated circuits. He was formerly a professor at UC Berkeley and the University of Washington.

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David J. Allstot's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A capacitor cross-coupled common-gate low-noise amplifier (2005) (339)
Bandwidth Extension Techniques for CMOS Amplifiers (2006) (304)
Compressed Sensing System Considerations for ECG and EMG Wireless Biosensors (2012) (298)
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis (1994) (247)
G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS (2005) (246)
A fully integrated 0.5-5.5 GHz CMOS distributed amplifier (2000) (232)
Design techniques for MOS switched capacitor ladder filters (1978) (201)
A precision variable-supply CMOS comparator (1982) (185)
A Switched-Capacitor RF Power Amplifier (2011) (166)
Design considerations for CMOS low-noise amplifiers (2004) (164)
Simulation techniques and solutions for mixed-signal coupling in integrated circuits (1994) (163)
Compressed Sensing Analog Front-End for Bio-Sensor Applications (2014) (150)
A 0.5-8.5 GHz fully differential CMOS distributed amplifier (2002) (147)
CMOS continuous-time current-mode filters for high-frequency applications (1993) (146)
Considerations for fast settling operational amplifiers (1990) (144)
Monolithic transformers and their application in a differential CMOS RF low-noise amplifier (1998) (142)
Switched-current circuit design issues (1991) (140)
Technological design considerations for monolithic MOS switched-capacitor filtering systems (1983) (119)
A Class-G Supply Modulator and Class-E PA in 130 nm CMOS (2009) (118)
MOS switched capacitor ladder filters (1978) (118)
Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation (2006) (118)
A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS (2009) (117)
Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs (1993) (116)
A high performance low power CMOS channel filter (1980) (114)
Low-power CMOS continuous-time filters (1996) (111)
An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC (1995) (108)
CMOS switched-current ladder filters (1990) (104)
A multistage amplifier technique with embedded frequency compensation (1999) (103)
Verification techniques for substrate coupling and their application to mixed-signal IC design (1996) (101)
A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity (2005) (99)
Rapid simulation of substrate coupling effects in mixed-mode ICs (1993) (97)
A Class-G Switched-Capacitor RF Power Amplifier (2013) (96)
Computer-aided design considerations for mixed-signal coupling in RF integrated circuits (1998) (93)
Electrothermal simulation of integrated circuits (1993) (92)
Design and optimization of CMOS RF power amplifiers (2001) (86)
Modeling of frequency and temperature effects in GaAs MESFETs (1990) (85)
A continuous-time current-mode integrator (1991) (83)
CMOS current steering logic for low-voltage mixed-signal integrated circuits (1997) (83)
CMOS folding A/D converters with current-mode interpolation (1996) (81)
A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers (2004) (78)
Fully balanced CMOS current-mode circuits (1993) (77)
A Parallel, Multi-Resolution Sensing Technique for Multiple Antenna Cognitive Radios (2007) (75)
A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications (2000) (66)
Sizing of cell-level analog circuits using constrained optimization techniques (1993) (65)
Synthesis techniques for CMOS folded source-coupled logic circuits (1992) (63)
A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$m CMOS (2010) (63)
An active-feedback cascode current source (1990) (60)
-Boosted Common-Gate LNA and Differential (2005) (60)
A switched-capacitor power amplifier for EER/polar transmitters (2011) (59)
A methodology for rapid estimation of substrate-coupled switching noise (1995) (58)
A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs (2006) (58)
A two-stage sensing technique for dynamic spectrum access (2009) (56)
Parasitic-Aware Optimization of CMOS RF Circuits (2003) (55)
Reflective-Type Phase Shifters for Multiple-Antenna Transceivers (2007) (55)
Substrate-aware mixed-signal macro-cell placement in WRIGHT (1994) (52)
Differential VCO and passive frequency doubler in 0.18 /spl mu/m CMOS for 24 GHz applications (2006) (51)
A family of high-swing CMOS operational amplifiers (1989) (51)
Strong Injection Locking in Low- $Q$ LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver (2009) (50)
Elitist nondominated sorting genetic algorithm based RF IC optimizer (2005) (49)
An electrically-programmable switched capacitor filter (1979) (49)
Parasitic-aware RF circuit design and optimization (2004) (48)
Substrate-aware mixed-signal macrocell placement in WRIGHT (1995) (47)
A quad-band GSM-GPRS transmitter with digital auto-calibration (2004) (45)
Compressive sampling of ECG bio-signals: Quantization noise and sparsity considerations (2010) (44)
A CMOS 3.1-10.6 GHz UWB LNA employing stagger-compensated series peaking (2006) (43)
CMOS folding ADCs with current-mode interpolation (1995) (43)
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier (2003) (42)
A 1.4V 5GHz four-antenna Cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications (2005) (39)
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS (2008) (39)
An image-rejection down-converter for low-IF receivers (2005) (39)
Current-mode logic techniques for CMOS mixed-mode ASICs (1991) (38)
CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits (2008) (35)
A g/sub m/-Boosted Current-Reuse LNA in 0.18/spl mu/m CMOS (2007) (35)
Compressed sensing reconstruction: Comparative study with applications to ECG bio-signals (2011) (35)
Analog logic techniques steer around the noise (1993) (34)
A 2 GHz CMOS even harmonic mixer for direct conversion receivers (2002) (33)
Wideband CMOS Amplifier Design: Time-Domain Considerations (2008) (31)
Parasitic-aware design and optimization of a CMOS RF power amplifier (2006) (31)
Twisted inductors for low coupling mixed-signal and RF applications (2008) (31)
Parasitic-aware design and optimization of CMOS RF integrated circuits (1998) (29)
Pulse-Width Modulated CMOS Power Amplifiers (2011) (29)
A gate-modulated CMOS LC quadrature VCO (2009) (29)
Integrated Quadrature Couplers and Their Application in Image-Reject Receivers (2009) (28)
A 7.2mW quadrature GPS receiver in 0.13µm CMOS (2009) (28)
Fast parasitic extraction for substrate coupling in mixed-signal ICs (1995) (28)
A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass $\Sigma \Delta$ ADC in 0.13 $\mu$m CMOS (2012) (27)
Low-noise logic for mixed-mode VLSI circuits (1992) (26)
Compressive sampling of EMG bio-signals (2011) (26)
Fully-integrated CMOS RF amplifiers (1999) (25)
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO (2004) (24)
Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem (2006) (24)
A Design Example (1995) (24)
A CMOS switched-current filter technique (1990) (23)
Simplified MOS switched capacitor ladder filter structures (1981) (23)
A 1.5V 28mA fully-integrated fast-locking quad-band GSM-GPRS transmitter with digital auto-calibration in 130nm CMOS (2004) (23)
A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ADC in 0.13 m CMOS (2012) (21)
A 5 GHz wide-range CMOS active phase shifter for wireless beamforming applications (2006) (21)
A 3V-125 MHz CMOS continuous-time filter (1993) (21)
Compressed sensing of ECG bio-signals using one-bit measurement matrices (2011) (20)
A 2.4-GHz Extended-Range Type-I $\Sigma\Delta$ Fractional-$N$ Synthesizer With 1.8-MHz Loop Bandwidth and $-$110-dBc/Hz Phase Noise (2011) (20)
A Calibrated Phase and Amplitude Control System for a 1.9 GHz Phased-Array Transmitter Element (2009) (19)
Fully monolithic CMOS RF power amplifiers: recent advances (1999) (18)
Analysis and design of lumped-element quadrature couplers with lossy passive elements (2006) (17)
A power-combined switched-capacitor power amplifier in 90nm CMOS (2011) (17)
Desensitized CMOS Low-Noise Amplifiers (2008) (16)
Noise considerations for mixed‐signal RF IC transceivers (1998) (16)
A 6 GHz low-noise quadrature Colpitts VCO (2004) (15)
SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits (1995) (15)
Linearizing CMOS Switching Power Amplifiers Using Supply Regulators (2010) (15)
A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation (2008) (14)
Parasitic-aware synthesis of RF CMOS switching power amplifiers (2002) (14)
A buffered charge pump with zero charge sharing (2008) (14)
FIR filtering using CMOS switched-current techniques (1990) (14)
Compact model generation for on-chip transmission lines (2004) (14)
System considerations for the compressive sampling of EEG and ECoG bio-signals (2011) (13)
Rapid Redesign Of Analog Standard Cells Using Constrained Optimization Techniques (1992) (13)
A matrix amplifier in 0.18-/spl mu/m SOI CMOS (2006) (13)
Low-power g/sub m/-boosted LNA and VCO circuits in 0.18 /spl mu/m CMOS (2005) (13)
A unified approach to simulating electrical and thermal substrate coupling interactions in ICs (1993) (12)
Impact of Switching Glitches in Class-G Power Amplifiers (2012) (12)
Digital calibration for monotonic pipelined A/D converters (2004) (12)
A new high-voltage analog-compatible I/sup 2/L process (1978) (11)
Parasitic-aware design and optimization of CMOS RF integrated circuits (1998) (11)
Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A (2017) (11)
A p-well GaAs MESFET technology for mixed-mode applications (1990) (11)
Small-signal analysis and minimum settling time design of a one-stage folded-cascode CMOS operational amplifier (1991) (11)
Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch (2008) (11)
A substrate-referenced data-conversion architecture (1991) (11)
A Matrix Amplifier in 0.18- m SOI CMOS (2006) (11)
An 11-Bit 330MHz 8X OSR /spl Sigma/-spl Delta/ Modulator for Next-Generation WLAN (2006) (11)
Digital power amplifier: A new way to exploit the switched-capacitor circuit (2012) (11)
A symmetric miniature 3D inductor (2003) (11)
An 11-bit 330MHz 8X OSR Σ−∆ Modulator for Next-Generation WLAN (2006) (11)
Design considerations for supply modulated EER power amplifiers (2013) (10)
An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$m CMOS (2010) (10)
A QPLL-timed direct-RF sampling band-pass ΣΔ ADC with a 1.2 GHz tuning range in 0.13 µm CMOS (2011) (10)
A 1.6 mW 5.4 GHz transformer-feedback gm-boosted current-reuse LNA in 0.18/μm CMOS (2010) (10)
Analysis and design of a fast-settling folded-cascode CMOS operational amplifier for switched-capacitor applications (1989) (10)
A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS (2005) (9)
An elitist distributed particle swarm algorithm for RFIC optimization (2005) (9)
A class-C power amplifier/antenna interface for wireless sensor applications (2011) (9)
Design considerations for CMOS switched-current filters (1990) (9)
A CMOS 5 GHz phase-compensated quadrature coupler (2006) (9)
A 2-GHz CMOS variable gain amplifier optimized for low noise (2006) (9)
Substrate coupling in mixed-mode and RF integrated circuits (1997) (9)
A p-well GaAs MESFET technology (1990) (8)
Monolithic transformers in a five metal CMOS process (2002) (8)
Design considerations for a 10 GHz CMOS transmit-receive switch (2005) (8)
A lateral-BJT-biased CMOS voltage-controlled oscillator (2004) (8)
A fully-differential CMOS Clapp VCO for IEEE 802.11a applications (2006) (8)
A PLL-based BFSK transmitter with reconfigurable and PVT-tolerant class-C PA for medradio & ISM (433MHz) standards (2013) (8)
A 2-GHz integrated CMOS reflective-type phase shifter with 675/spl deg/ control range (2006) (7)
Measurement and modeling errors in noise parameters of scaled-CMOS devices (2006) (7)
A multistage amplifier topology with embedded tracking compensation (1998) (7)
A Digital-Summing Feedforward Σ-Δ Modulator and its Application to a Cascade ADC (2007) (7)
A class-G dual-supply switched-capacitor power amplifier in 65nm CMOS (2012) (7)
Analytical model of GaAs MESFET output conductance (1988) (6)
A CMOS 5GHz Image-Reject Receiver Front-End Architecture (2007) (6)
Charge-pump assisted low-power/low-voltage CMOS op amp design (1997) (6)
Trap effects in p-channel GaAs MESFET's (1992) (6)
Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems (2011) (6)
DAC mismatch shaping for quadrature sigma-delta data converters (2015) (6)
Post-optimization design centering for RF integrated circuits (2004) (6)
Fully-differential CMOS current-mode circuits and applications (1991) (6)
MOlC-1 Design Considerations for CMOS Low-Noise Amplifiers ' (2004) (6)
A low-power backward equalizer for DFE read-channel applications (1997) (6)
Design considerations for anti-phase injected quadrature voltage controlled oscillators (2004) (6)
A full-range all-pass variable phase shifter for multiple antenna receivers (2005) (6)
A 900 MHz GSM PA in 250 nm CMOS with breakdown voltage protection and programmable conduction angle (2004) (5)
Current-Mode Continuous-Time Filters (1995) (5)
Low-voltage fully differential switched-current filters (1994) (5)
Low-power high-speed continuous-time /spl Sigma/-/spl Delta/ modulators (1995) (5)
Low-Power High-Speed Continuous-Time Sigma-Delta Modulators. (1995) (5)
Transmitters for body sensor networks: A comparative study (2011) (5)
Monolithic Spiral Transformers: A Design Methodology (2007) (5)
Measurement and modeling of noise parameters for desensitized low noise amplifiers (2004) (4)
An 8-bit, 1.8 V, 20 MSample/s analog-to-digital converter using low gain opamps (2003) (4)
An image rejection down-converter for low-IF receivers in 130 nm CMOS (2004) (4)
CMOS integrated transformers: coming of age (2006) (4)
A monotonic digital calibration technique for pipelined data converters (2003) (4)
A mixed-signal calibration technique for low-voltage CMOS 1.5-bit/stage pipeline data converters (2003) (4)
CMOS phase-shifting circuits for wireless beamforming transmitters (2008) (4)
Desensitized design of MOS low noise amplifiers by R/sub n/ minimization (2004) (4)
Parasitic-aware RF IC design (2003) (4)
Improved self-boot-strapped gain enhancement technique for GaAs amplifiers (1988) (4)
10.7 A 0.26mm2 DPD-Less Quadrature Digital Transmitter With <−40dB EVM Over >30dB Pout Range in 65nm CMOS (2020) (4)
A 1.1µW 2.1µVRMS input noise chopper-stabilized amplifier for bio-medical applications (2012) (4)
A resonant pad for ESD protected narrowband CMOS RF applications (2003) (4)
High Speed Quarter Micron Buried-channel MESFETs With Improved Output Characteristics For Analog Applications (1987) (3)
A 40 Mhz Cmos Continuous-time Current-mode Filter (1992) (3)
Parasitic-aware synthesis of CMOS RF power amplifiers via simultaneous topology selection and device sizing (2002) (3)
Design considerations for integrated CMOS reflective-type phase shifters (2007) (3)
Addition to "Monolithic transformers and their application in a differential CMOS RF low-noise amplifier" (1999) (3)
RF circuit synthesis using particle swarm optimization (2004) (3)
A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC. (2007) (3)
A tunable transmission line phase shifter (TTPS) (2004) (3)
A Tuned-Input Tuned-Output VCO in 0.18/spl mu/m CMOS (2007) (3)
A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing (2011) (3)
Multiple supply (class-G) linear modulator and PA for non-CE modulation (2009) (3)
Dear CAS Member's [President's Message] (2009) (3)
High-speed CMOS current-mode equalizers (1995) (3)
SWITCHED-CAPACITOR APPLICATIONS IN SPEECH PROCESSING. (1979) (3)
Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs (2012) (3)
Substrate Modeling in Heavily-Doped Bulk Processes (1995) (3)
Twisted transformers for low coupling RF and mixed signal applications (2009) (3)
Modeling Chip/Package Power Distribution (1995) (3)
Amplitude-locked loop analysis for calibration applications (2006) (3)
Towards greener wireless transmission: Efficient power amplifier design (2011) (3)
Class AB-D-G line driver for central office asymmetric digital subscriber line systems (2002) (2)
A 360/spl deg/ extended range phase detector for type-I PLLs (2005) (2)
Parasitic-aware design and optimisation of RF power amplifiers (2002) (2)
A 1.4 V/5 GHz, 90-nm system-in-a-package LNA (2006) (2)
A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS (2004) (2)
Controlling Substrate Coupling in Heavily-Doped Bulk Processes (1995) (2)
A Switched-Capacitor Closed-Loop Integration Sampling Front-End for Peripheral Nerve Recording (2021) (2)
A high-voltage analog-compatible I2L process (1977) (2)
Circuit techniques for CMOS multiple-antenna transceivers (2005) (2)
Analog Chirp Fourier Transform for high-resolution real-time wideband RF spectrum Analysis (2011) (2)
Linearity Improvement Techniques for CMOS Switched-Capacitor Power Amplifiers (2021) (2)
One-transistor GaAs voltage reference circuit (1989) (1)
The potential of p-well GaAs MESFET technology for precision integrated circuits (1990) (1)
Low phase noise CMOS voltage-controlled oscillators (2007) (1)
An elitist distributed particle swarm algorithm for RF IC optimization (2005) (1)
Bridging circuits and electromagnetics in a curriculum aimed at microelectronic analog and microwave simulation and design (2005) (1)
Matching considerations in I/Q A/D converter pairs (2002) (1)
Low-Voltage Tracking RC Frequency Compensation in Two-Stage Operational Amplifiers* (2019) (1)
Elimination of sidegating in n-channel GaAs MESFETs using a p-type well (1992) (1)
Sources of Noise and Methods of Coupling (1995) (1)
Digital calibration methods for high-accuracy pipeline A/D converters (2003) (1)
Prof. Temes and Switched-Capacitor Circuits?Thirty-Five Years and Counting (2013) (1)
Design of a One-Stage Folded-Cascode CMOS Operational Amplifier (1991) (1)
From 100 milliwatts/MIPS to 10 microwatts/MIPS [low-power VLSI] (1994) (1)
Simplified Substrate Modeling and Rapid Simulation (1995) (1)
Compressed Sensing Σ-Δ Modulators and Recovery Algorithm for Multi-Channel Bio-Signal Acquisition (2021) (1)
CMOS Powers Toward System-on-Chip Integration [From the Guest Editors' Desk] (2011) (1)
Architectural issues in base-station frequency synthesizers (2005) (1)
Hybrid modeling techniques for low OSR cascade continuous-time ΣΔ modulators (2008) (1)
Design Considerations for Wideband CMOS Amplifiers (2006) (0)
On-chip inductor structures: a comparative study (2003) (0)
AN ABSTRACT OF THE THESIS OF Yihai Xiang for the degree of Master of Science in Electrical and Computer (2012) (0)
Design of GaAs Monolithically integrated Optical Receiver Amplifier (2013) (0)
SOC vs. SIP; Are we putting too much on one chip? (2004) (0)
Title : A CAD Noise Model for Chopper-Stabilized Switched-Capacitor Filters Redacted for Privacy (2013) (0)
RF power amplification: Can CMOS deliver? (2010) (0)
Guillemin-Cauer Award (2004) (0)
A 360∞ Extended Range Phase Detector for Type-I PLLs 1 (2005) (0)
Switched-Capacitor Circuits [Education] (2021) (0)
IEEE CAS Society Transactions on Circuits and Systems Darlington Best Paper Award (2010) (0)
Semiconductor Device Simulation (1995) (0)
Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization (2005) (0)
An Eight-core Class-G Switched-capacitor Power Amplifier with Eight Power Backoff Efficiency Peaks (2022) (0)
a Pulse Width Modulator with Pulse (1997) (0)
Chip/Package Shielding and Good Circuit Design Practice (1995) (0)
A cmos direct-rf sampling band-pass sigmadelta receiver with integrated qpll for software-defined radio applications (2011) (0)
E6 SoC: DOA? RIP? (2003) (0)
Rapid Redesign of Analog Standard Cells Using C on s t r a in e d 0 p t im iz a t i on Tee h n i que s1 (1992) (0)
Gordon M. Jacobs, David J. Allstot, and Robert W. Brodersen win W.R.G. Baker prize award (1980) (0)
Society & Achievement Awards (2011) (0)
A CMOS continuous-time current-mode filter technique (1992) (0)
Parasitic-aware RF IC design and optimisation (2004) (0)
AN ABSTRACT OF THE THESIS OF SPEED READER INTERFACE FOR PDP-8/L COMPUTER SYSTEM Redacted for privacy (2010) (0)
Associate Editors :N. S COTT BARKER ,G EORG BOECK ,K WOK-KEUNG M. CHENG ,J AE-SUNG RIEH ,C OSTAS D. SARRIS, AND LEI ZHU The following members of the Review Board reviewed papers during 2009. (2010) (0)
SE5 Noise Coupling in Mixed-Signal/RF SoCs (2004) (0)
Design of Wideband Amplifiers in CMOS (2008) (0)
Engineering in Medicine and Biology B. HE, President TECHNICAL CO-SPONSORING SOCIETIES Computational Intelligence (2009) (0)
Electrical and T (1993) (0)
Controlling Substrate Coupling in Bulk P- Wafers (1995) (0)
Switched-Capacitor Circuits (2022) (0)
A delay generation technique for fast-locking frequency synthesizers (2006) (0)
A High Performance Low Power Filter 929 CMOS Channel (1999) (0)
I/Q-Sharing Switched-Capacitor Power Amplifier with Baseband Harmonic-Rejection and Wilkinson Combiner (2021) (0)
IEEE COUNCIL ON ELECTRONIC DESIGN AUTOMATION Officers (2008) (0)
2009 IEEE Dallas Circuits And Systems Workshop (2009) (0)
Introduction to the Special Issue on Analog, Sensor, and Communications Circuits of the 1996 ISSCC [ (1996) (0)
A Context for Assisted Cognition (2002) (0)
A variable-offset phase detector for phased-array applications (2006) (0)
gm/ID Design Considerations for Subthreshold-Based CMOS Two-Stage Operational Amplifiers (2020) (0)
A 4-antenna transmitter in 0.18µm CMOS using space-time block codes (2009) (0)
A macromodel compaction scheme for the fast simulation of large linear mesh circuits (1995) (0)
Competing CMOS circuit techniques (1993) (0)
Ring-Amplification Technique for Bio-Signal LNA Designs (2015) (0)
Transformer-Combining Digital PA with Efficiency Peaking at 0, −6, and −12 dB Backoff in 32nm CMOS (2020) (0)
Electromagnetic modeling and electromagnetic-circuit co-simulation of mixed-signal systems-on-chip (2004) (0)
SESSION VIII: MONOLITHIC FILTERS (1979) (0)
Call for nominations (2016) (0)
Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition (2023) (0)
gm/ID-Based Frequency Compensation of CMOS Two-Stage Operational Amplifiers (2020) (0)
Substrate Resistance Extraction for Large Circuits (1995) (0)
2008 IEEE CIRCUITS AND SYSTEMS SOCIETY (2008) (0)
AN ABSTRACT OF THE THESIS OF Vivek Subramanian for the degree of Master of Science in Electrical and Computer (2013) (0)
AN ABSTRACT OF THE THESIS OF Vivek Subramanian for the degree of Master of Science in Electrical and Computer (2013) (0)
Accurate compact model extraction for on-chip coplanar waveguides (2003) (0)
AN ABSTRACT OF THE THESIS OF Paul A . Lao for the degree of Master of Science in Electrical and Computer (2013) (0)
U-shaped slow-wave transmission lines in 0.18μm CMOS (2010) (0)
Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators. (2008) (0)
RECENT ADVANCES AND DESIGN TRENDS IN CMOS RADIO FREQUENCY INTEGRATED CIRCUITS (2005) (0)
Dear CAS Members [Past President's Message] (2010) (0)
A digital RF power amplification technique based on the switched-capacitor circuit (2016) (0)
A Mode-I/Mode-III UWB LNA with programmable gain and 20 dB WLAN blocker rejection in 130nm CMOS (2010) (0)
Windowed Integration Sampling in Bio-Signal Front-End Design (2020) (0)
Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs (2012) (0)
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS (1994) (0)
A Two-Stage CMOS OTA with Load-Pole Cancellation (2019) (0)

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