David M. Brooks

David M. Brooks's AcademicInfluence.com Rankings

David M. Brooks

Engineering

#6093

World Rank

#7397

Historical Rank

Electrical Engineering

#1770

World Rank

#1869

Historical Rank

engineering Degrees

David M. Brooks

Computer Science

#7931

World Rank

#8347

Historical Rank

Computer Architecture

#51

World Rank

#53

Historical Rank

Database

#4989

World Rank

#5183

Historical Rank

computer-science Degrees

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Engineering
Computer Science

David M. Brooks's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Stanford University

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David M. Brooks's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Wattch: a framework for architectural-level power analysis and optimizations (2000) (3008)
Dynamic thermal management for high-performance microprocessors (2001) (874)
System level analysis of fast, per-core DVFS using on-chip switching regulators (2008) (747)
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors (2000) (515)
Accurate and efficient regression modeling for microarchitectural performance and power prediction (2006) (503)
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators (2016) (502)
Applied Machine Learning at Facebook: A Datacenter Infrastructure Perspective (2018) (444)
Process Variation Tolerant 3T1D-Based Cache Architectures (2007) (322)
Machine Learning at Facebook: Understanding Inference at the Edge (2019) (312)
Dynamically exploiting narrow width operands to improve processor power and performance (1999) (311)
Profiling a warehouse-scale computer (2015) (300)
Thread motion: fine-grained power management for multi-core systems (2009) (263)
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures (2014) (263)
Methods of inference and learning for performance modeling of parallel applications (2007) (225)
A dynamic compilation framework for controlling microprocessor energy and performance (2005) (224)
A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS (2012) (214)
Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network (2007) (211)
MachSuite: Benchmarks for accelerator design and customized architectures (2014) (207)
Ares: A framework for quantifying the resilience of deep neural networks (2018) (197)
MLPerf Training Benchmark (2019) (189)
The Architectural Implications of Facebook's DNN-Based Personalized Recommendation (2019) (186)
Performance, energy, and thermal considerations for SMT and CMP architectures (2005) (178)
CMP design space exploration subject to physical constraints (2006) (176)
An ultra low power system architecture for sensor network applications (2005) (174)
Fathom: reference workloads for modern deep learning methods (2016) (165)
Benchmarking TPU, GPU, and CPU Platforms for Deep Learning (2019) (162)
Optimizing pipelines for power and performance (2002) (154)
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications (2017) (150)
Control techniques to eliminate voltage emergencies in high performance processors (2003) (144)
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors (2007) (141)
Illustrative Design Space Studies with Microarchitectural Regression Models (2007) (134)
Survey of Hardware Systems for Wireless Sensor Networks (2008) (131)
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units (2006) (126)
An Adaptive Issue Queue for Reduced Power at High Performance (2000) (121)
Energy characterization and instruction-level energy model of Intel's Xeon Phi processor (2013) (121)
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors (2003) (119)
Co-designing accelerators and SoC interfaces using gem5-Aladdin (2016) (116)
DeepRecSys: A System for Optimizing End-To-End At-Scale Neural Recommendation Inference (2020) (110)
Voltage emergency prediction: Using signatures to reduce operating margins (2009) (105)
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency (2008) (105)
A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation (2011) (101)
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019) (99)
Quantifying sources of error in McPAT and potential impacts on architectural studies (2015) (99)
CPR: Composable performance regression for scalable multiprocessor models (2008) (98)
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling (2010) (95)
A circuit level implementation of an adaptive issue queue for power-aware microprocessors (2001) (92)
HELIX: automatic parallelization of irregular programs for chip multiprocessing (2012) (85)
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance (2000) (83)
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (2008) (80)
Integrated analysis of power and performance for pipelined microprocessors (2004) (74)
The accelerator store: A shared memory framework for accelerator-based systems (2012) (72)
Tribeca: Design for PVT variations with local recovery and fine-grained adaptation (2009) (70)
ISA-independent workload characterization and its implications for specialized architectures (2013) (70)
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications (2018) (66)
Tradeoffs between power management and tail latency in warehouse-scale applications (2014) (64)
Efficiency trends and limits from comprehensive microarchitectural adaptivity (2008) (63)
Cheetah: Optimizing and Accelerating Homomorphic Encryption for Private Inference (2020) (62)
A case for efficient accelerator design space exploration via Bayesian optimization (2017) (61)
Chasing Carbon: The Elusive Environmental Footprint of Computing (2020) (60)
Understanding the energy efficiency of simultaneous multithreading (2004) (54)
Profiling a Warehouse-Scale Computer (2016) (51)
Towards a software approach to mitigate voltage emergencies (2007) (50)
An event-guided approach to reducing voltage noise in processors (2009) (50)
RecSSD: near data processing for solid state drive based recommendation inference (2021) (49)
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference (2020) (49)
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs (2014) (47)
An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS (2009) (46)
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability (2008) (45)
Dimetrodon: Processor-level preventive thermal management via idle cycle injection (2011) (45)
Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance (2006) (45)
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization (2004) (43)
Architectural power models for sram and cam structures based on hybrid analytical/empirical techniques (2007) (42)
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor (2000) (41)
HELIX-UP: Relaxing program semantics to unleash parallelization (2015) (39)
Achieving uniform performance and maximizing throughput in the presence of heterogeneity (2011) (39)
TinyBench: the case for a standardized benchmark suite for TinyOS based wireless sensor network devices (2004) (38)
Enabling On-Chip Switching Regulators for Multi-Core Processors using Current Staggering (2007) (37)
Characterizing and evaluating voltage noise in multi-core near-threshold processors (2013) (37)
Live, Runtime Power Measurements as a Foundation for Evaluating Power/Performance Tradeoffs (2001) (36)
MASR: A Modular Accelerator for Sparse RNNs (2019) (35)
The Aladdin Approach to Accelerator Design and Modeling (2015) (34)
Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference (2020) (33)
Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation (2006) (33)
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor (2002) (32)
A Systematic Methodology for Analysis of Deep Learning Hardware and Software Platforms (2020) (31)
SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads (2019) (30)
Weightless: Lossy Weight Encoding For Deep Neural Network Compression (2017) (30)
Applications of Deep Neural Networks for Ultra Low Power IoT (2017) (29)
A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications (2016) (29)
Can Subthreshold and Near-Threshold Circuits Go Mainstream? (2010) (29)
Effects of pipeline complexity on SMT/CMP power-performance efficiency (2005) (28)
The Accelerator Store framework for high-performance, low-power accelerator-based systems (2010) (28)
Empirical performance models for 3T1D memories (2009) (27)
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation (2019) (26)
Deep Learning for Computer Architects (2017) (26)
Software-assisted hardware reliability: Abstracting circuit-level challenges to the software stack (2009) (26)
A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators (2019) (25)
Quantifying acceleration: Power/performance trade-offs of application kernels in hardware (2013) (24)
Mallacc: Accelerating Memory Allocation (2017) (24)
The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines (2020) (24)
The design of a bloom filter hardware accelerator for ultra low power systems (2009) (23)
Research Infrastructures for Hardware Accelerators (2015) (23)
A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter (2015) (23)
Voltage Noise in Production Processors (2011) (22)
Gradient Disaggregation: Breaking Privacy in Federated Learning by Reconstructing the User Participant Matrix (2021) (22)
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations (2006) (22)
Roughness of microarchitectural design topologies and its implications for optimization (2008) (22)
Cross-Stack Workload Characterization of Deep Recommendation Systems (2020) (22)
On-Chip Deep Neural Network Storage with Multi-Level eNVM (2018) (22)
Toward Cache-Friendly Hardware Accelerators (2015) (21)
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity (2010) (21)
Eliminating voltage emergencies via software-guided code transformations (2010) (21)
Evaluation of voltage stacking for near-threshold multicore computing (2012) (21)
Helix: Making the Extraction of Thread-Level Parallelism Mainstream (2012) (21)
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency (2008) (21)
A fully integrated battery-connected switched-capacitor 4:1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling (2013) (20)
Ivory: Early-stage design space exploration tool for integrated voltage regulators (2017) (19)
A power electronics unit to drive piezoelectric actuators for flying microrobots (2015) (19)
AdaptivFloat: A Floating-point based Data Type for Resilient Deep Learning Inference (2019) (19)
A Low Mass Power Electronics Unit to Drive Piezoelectric Actuators for Flying Microrobots (2018) (18)
Applied inference: Case studies in microarchitectural design (2010) (18)
CARB: A C-State Power Management Arbiter for Latency-Critical Workloads (2017) (18)
Exploiting Parallelism Opportunities with Deep Learning Frameworks (2019) (18)
Efficient architectures through application clustering and architectural heterogeneity (2006) (16)
Power-performance simulation: design and validation strategies (2004) (15)
A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC–DC Converter (2017) (15)
Microarchitecture-Level Power-Performance Simulators: Modeling, Validation, and Impact on Design (2003) (15)
A multi-chip system optimized for insect-scale flapping-wing robots (2015) (14)
Navigo: An Early-Stage Model to Study Power-Constrained Architectures and Specialization (2015) (14)
Implementing a hybrid SRAM / eDRAM NUCA architecture (2011) (14)
Power and thermal effects of SRAM vs. latch-mux design styles and clock gating choices (2005) (13)
9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET (2021) (13)
Statistically Rigorous Regression Modeling for the Microprocessor Design Space (2006) (13)
A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs (2019) (12)
Cheetah: Optimizations and Methods for PrivacyPreserving Inference via Homomorphic Encryption (2020) (12)
Predicting New Workload or CPU Performance by Analyzing Public Datasets (2019) (12)
Design and analysis of an integrated driver for piezoelectric actuators (2013) (12)
XIOSim: power-performance modeling of mobile x86 cores (2012) (12)
A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle (2017) (11)
The HELIX project: Overview and directions (2012) (11)
Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip (2014) (11)
Power-efficient issue queue design (2002) (11)
Impact of thermal constraints on multi-core architectures (2006) (11)
Hardware in the loop for optical flow sensing in a robotic bee (2011) (10)
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs (2019) (10)
RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance (2021) (10)
Machine Learning-Based Automated Design Space Exploration for Autonomous Aerial Robots (2021) (10)
Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations (2011) (10)
Evaluating the Thermal Efficiency of SMT and CMP Architectures (2004) (9)
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles (2021) (9)
Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS (2013) (9)
Spatial Sampling and Regression Strategies (2007) (8)
Evaluation of voltage interpolation to address process variations (2008) (8)
Regression Modeling Strategies for Microarchitectural Performance and Power Prediction (2006) (8)
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators (2020) (8)
EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP (2020) (8)
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization (2019) (8)
Very Low Voltage (VLV) Design (2017) (8)
Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development (2020) (7)
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling (2019) (7)
LATENCY ADAPTATION FOR MULTIPORTED REGISTER FILES TO MITIGATE THE IMPACT OF PROCESS VARIATIONS (2006) (7)
An Area-Efficient 8-Bit Single-Ended ADC With Extended Input Voltage Range (2018) (7)
Cognitive Computing Safety: The New Horizon for Reliability / The Design and Evolution of Deep Learning Workloads (2017) (7)
MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge (2019) (7)
A 20μW 10MHz relaxation oscillator with adaptive bias and fast self-calibration in 40nm CMOS for micro-aerial robotics application (2013) (7)
NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories (2021) (6)
A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm (2020) (6)
Analytical Latency-Throughput Model of Future Power Constrained Multicore Processors (2012) (6)
Measuring Code Optimization Impact on Voltage Noise (2013) (6)
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators (2022) (6)
Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis (2018) (6)
Using dynamic dependence analysis to improve the quality of high-level synthesis designs (2017) (5)
Multi-accelerator system development with the ShrinkFit acceleration framework (2014) (5)
CPUs, GPUs, and Hybrid Computing (2011) (5)
Energy- and area-efficient architectures through application clustering and architectural heterogeneity (2009) (5)
A Tutorial in Spatial Sampling and Regression Strategies for Microarchitectural Analysis (2007) (5)
Bridging Python to Silicon: The SODA Toolchain (2022) (4)
Shrink-Fit: A Framework for Flexible Accelerator Sizing (2013) (4)
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories (2021) (4)
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware (1999) (4)
Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights (2019) (4)
Cloud No Longer a Silver Bullet, Edge to the Rescue (2018) (4)
A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET (2018) (4)
Evaluating techniques for exploiting instruction slack (2004) (3)
Variation-aware processor architectures with aggressive operating margins (2009) (3)
Demystifying Bayesian Inference Workloads (2019) (3)
A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs (2020) (3)
OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge (2022) (3)
Process Variation Tolerant Register Files Based On Dynamic Memories (2007) (3)
Design and test strategies for microarchitectural post-fabrication tuning (2009) (3)
Application of Approximate Matrix Multiplication to Neural Networks and Distributed SLAM (2019) (3)
Accelerator-based architectures for wireless sensor network applications (2009) (3)
Reducing power loss, cost and complexity of soc power delivery using integrated 3-level voltage regulators (2013) (2)
Automatically accelerating non-numerical programs by architecture-compiler co-design (2017) (2)
Instruction-driven clock scheduling with glitch mitigation (2008) (2)
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration (2022) (2)
Invited: Software Defined Accelerators From Learning Tools Environment (2020) (2)
A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs (2023) (2)
Design and modeling of power-efficient computer architectures (2001) (2)
Tabula: Efficiently Computing Nonlinear Activation Functions for Secure Neural Network Inference (2022) (2)
A Scalable Bayesian Inference Accelerator for Unsupervised Learning (2020) (2)
Ares (2018) (2)
A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM (2019) (2)
Quantifying Latency and Throughput Compromises in CMP Design (2012) (2)
Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis (2021) (2)
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC (2022) (2)
Co-designed systems for deep learning hardware accelerators (2018) (2)
System-on-Chip Architecture Design for Intelligent Sensor Networks (2006) (2)
ASAP: automatic synthesis of area-efficient and precision-aware CGRAs (2022) (1)
Automating Design of Voltage Interpolation to Address Process Variations (2011) (1)
System design considerations for sensor network applications (2008) (1)
Emerging Neural Workloads and Their Impact on Hardware (2020) (1)
Circuit and system design for robotic flying vehicles (2015) (1)
Early DSE and Automatic Generation of Coarse-grained Merged Accelerators (2021) (1)
CoopMC: Algorithm-Architecture Co-Optimization for Markov Chain Monte Carlo Accelerators (2022) (1)
Power , Performance and Portability : System Design Considerations for Micro Air Vehicle Applications (2010) (1)
End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators (2022) (1)
Software-assisted hardware reliability: enabling aggressive timing speculation using run-time feedback from hardware and software (2010) (1)
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators (2020) (1)
A Binary-activation, Multi-level Weight RNN and Training Algorithm for ADC-/DAC-free and Noise-resilient Processing-in-memory Inference with eNVM (2020) (1)
Place and route considerations for voltage interpolated designs (2009) (1)
GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators (2022) (1)
Ultra-Low-Power Processors (2017) (1)
AutoPilot: Automating SoC Design Space Exploration for SWaP Constrained Autonomous UAVs (2021) (1)
Methods and infrastructure in the era of accelerator-centric architectures (2017) (1)
CHAMPVis: Comparative Hierarchical Analysis of Microarchitectural Performance (2019) (1)
MaxNVM (2019) (1)
Impala: Low-Latency, Communication-Efficient Private Deep Learning Inference (2022) (1)
Toward a hardware accelerated future (2013) (1)
The MachSuite Benchmark (2015) (1)
Sub-uJ deep neural networks for embedded applications (2017) (1)
Unified Cache : A Case for Low-Latency Communication (2015) (0)
Cross-Layer Modeling Framework for Energy-Efficient Resilience (2014) (0)
Design and Test Strategies for Microarchitectural PostFabrication (2008) (0)
SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33rd Hot Chips Symposium – August 22-24, 2021 (2021) (0)
Keynote I: Workload Characterization in the Era of Specialization by David Brooks (2015) (0)
The alarms project: A hardware/software approach to addressing parameter variations (2011) (0)
A System-Level View of Voltage Noise in Production Processors (2011) (0)
Integrated Architectural Level Power-Performance Modeling Toolkit (2004) (0)
Hardware-based thread scheduling for power-efficient and variation-resilient chip multiprocessors (2011) (0)
Guest Editors’ Introduction Ultra-Low-Power Processors (2017) (0)
Automatic Domain-Specific SoC Design for Autonomous Unmanned Aerial Vehicles (2022) (0)
Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design (2020) (0)
Analytically Modeling NVM Design Trade-Offs (2020) (0)
Complexity − Effective Design Workshop on (2005) (0)
An SoC Platform Architecture for Mini Autonomous Drones (2017) (0)
Mallacc (2017) (0)
Mallacc (2017) (0)
A Circuit Level Implementation of an Adaptive Issue for Power-Aware Microprocessors Queue (2001) (0)
Early-Stage Definition of LPX : aLow Power (0)
Session details: Hot chips running cool - energy efficient near-threshold computing and its barriers (2012) (0)
Session details: High level power modeling and analysis (2004) (0)
Tribeca (2018) (0)
Operand-Value-Based Optimizations To Reduce Processor Power Consumption (2011) (0)
Breaking Cyclic-Multithreading Parallelization with XML Parsing (2014) (0)
From High-Level Frameworks to custom Silicon with SODA (2022) (0)
Research Narrative (2008) (0)
22.9 A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management (2023) (0)
2017 International Symposium on Computer Architecture Influential Paper Award (2017) (0)
FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference (2021) (0)
21.5 A 3-to-5V input 100Vpp output 57.7mW 0.42% THD+N highly integrated piezoelectric actuator driver (2017) (0)
SMAUG (2020) (0)
Architectural Implications of Embedding Dimension during GCN on CPU and GPU (2022) (0)
Trireme: Exploration of Hierarchical Multi-Level Parallelism for Hardware Acceleration (2023) (0)
PerfSAGE: Generalized Inference Performance Predictor for Arbitrary Deep Learning Models on Edge Devices (2023) (0)
Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007 (2008) (0)
Addressing the computing technology-capability gap: The coming Golden Age of design (2015) (0)

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What Schools Are Affiliated With David M. Brooks?

David M. Brooks is affiliated with the following schools:

Harvard University

David M. Brooks's Academic­Influence.com Rankings

David M. Brooks's Degrees

Why Is David M. Brooks Influential?

David M. Brooks's Published Works

Published Works

What Schools Are Affiliated With David M. Brooks?

David M. Brooks's AcademicInfluence.com Rankings