Dean M. Tullsen
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Dean M. Tullsencomputer-science Degrees
Computer Science
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Computer Architecture
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Computer Science
Dean M. Tullsen's Degrees
- PhD Computer Science University of Washington
- Masters Computer Science University of Washington
- Bachelors Computer Science University of California, Berkeley
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Why Is Dean M. Tullsen Influential?
(Suggest an Edit or Addition)Dean M. Tullsen's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures (2009) (2453)
- Simultaneous multithreading: Maximizing on-chip parallelism (1995) (1770)
- Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction (2003) (854)
- Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor (1996) (850)
- Single-ISA heterogeneous multi-core architectures for multithreaded workload performance (2004) (668)
- Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling (2005) (482)
- Simultaneous multithreading: a platform for next-generation processors (1997) (447)
- Symbiotic jobscheduling for a simultaneous mutlithreading processor (2000) (438)
- Heterogeneous chip multiprocessors (2005) (383)
- Speculative precomputation: long-range prefetching of delinquent loads (2001) (359)
- Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading (1997) (285)
- Symbiotic jobscheduling for a simultaneous multithreaded processor (2000) (271)
- Core architecture optimization for heterogeneous chip multiprocessors (2006) (252)
- Handling long-latency loads in a simultaneous multithreading processor (2001) (242)
- Dynamic speculative precomputation (2001) (219)
- Selective value prediction (1999) (218)
- The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing (2013) (195)
- Symbiotic jobscheduling with priorities for a simultaneous multithreading processor (2002) (194)
- Managing distributed UPS energy for effective power capping in data centers (2012) (193)
- Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices (2005) (192)
- Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor (1996) (161)
- Threaded multiple path execution (1998) (157)
- Dynamic prediction of critical path instructions (2001) (147)
- Initial observations of the simultaneous multithreading Pentium 4 processor (2003) (139)
- Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors (2009) (126)
- Pointer cache assisted prefetching (2002) (125)
- Supporting fine-grained synchronization on a simultaneous multithreading processor (1999) (119)
- Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX (2017) (118)
- Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor (2014) (114)
- Conjoined-Core Chip Multiprocessing (2004) (111)
- Execution migration in a heterogeneous-ISA chip multiprocessor (2012) (105)
- Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures (2003) (98)
- Reducing power with dynamic critical path information (2001) (92)
- Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors (2006) (90)
- Inter-core prefetching for multicore processors using migrating helper threads (2011) (88)
- Storageless value prediction using prior register values (1999) (82)
- A tree based router search engine architecture with single port memories (2005) (81)
- Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization (2019) (80)
- Limitations Of Cache Prefetching On A Bus-based Multiprocessor (1993) (79)
- Accelerating and Adapting Precomputation Threads for Effcient Prefetching (2007) (73)
- An event-driven multithreaded dynamic optimization framework (2005) (70)
- Proximity-aware directory-based coherence for multi-core processor architectures (2007) (68)
- Software-Directed Register Deallocation for Simultaneous Multithreaded Processors (1999) (63)
- Application-Specific Customization of Parameterized FPGA Soft-Core Processors (2006) (62)
- The effect of compiler optimizations on Pentium 4 power consumption (2003) (62)
- Quantifying instruction criticality (2002) (59)
- Redefining the Role of the CPU in the Era of CPU-GPU Integration (2012) (54)
- Reducing peak power with a table-driven adaptive processor core (2009) (54)
- Tuning Compiler Optimizations for Simultaneous Multithreading (1997) (53)
- Effective cache prefetching on bus-based multiprocessors (1995) (52)
- Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices (2008) (50)
- Root causes (1997) (49)
- Control Flow Optimization Via Dynamic Reconvergence Prediction (2004) (49)
- Shredder: Learning Noise Distributions to Protect Inference Privacy (2019) (48)
- Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy (2004) (45)
- Dynamically heterogeneous cores through 3D resource pooling (2012) (45)
- Fast thread migration via cache working set prediction (2011) (44)
- Hardware identification of cache conflict misses (1999) (43)
- Clustered multithreaded architectures - pursuing both IPC and cycle time (2004) (39)
- Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing (2016) (39)
- Thermal time shifting: Leveraging phase change materials to reduce cooling costs in warehouse-scale computers (2015) (38)
- Fast switching of threads between cores (2009) (37)
- A self-repairing prefetcher in an event-driven dynamic optimization framework (2006) (36)
- A Multi-Core Approach to Addressing the Energy-Complexity Problem in Microprocessors (2003) (35)
- Data-triggered threads: Eliminating redundant computation (2011) (34)
- MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories (2017) (34)
- Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading (2009) (33)
- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture (2008) (32)
- The shared-thread multiprocessor (2008) (32)
- Runtime parallelization of legacy code on a transactional memory system (2011) (31)
- Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems (2015) (30)
- Multithreaded value prediction (2005) (30)
- The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU (2015) (28)
- HIPStR: Heterogeneous-ISA Program State Relocation (2016) (27)
- Automatically eliminating speculative leaks from cryptographic code with blade (2020) (27)
- ILP versus TLP on SMT (1999) (27)
- Compiling for instruction cache performance on a multithreaded architecture (2002) (25)
- Reliability-Aware Data Placement for Heterogeneous Memory Architecture (2018) (25)
- I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches (2021) (25)
- Accurate branch prediction for short threads (2008) (24)
- Swivel: Hardening WebAssembly against Spectre (2021) (24)
- Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency (2018) (23)
- Multithreading Architecture (2013) (23)
- Modeling and analysis of Phase Change Materials for efficient thermal management (2014) (22)
- The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best (2005) (22)
- Power-sensitive multithreaded architecture (2000) (21)
- Simultaneous multithreading (1996) (21)
- Conjoining Soft-Core FPGA Processors (2006) (21)
- Software data spreading: leveraging distributed caches to improve single thread performance (2010) (21)
- Compiler techniques to reduce the synchronization overhead of GPU redundant multithreading (2017) (20)
- The case for colocation of high performance computing workloads (2016) (19)
- Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA (2019) (19)
- Runtime identification of cache conflict misses: The adaptive miss buffer (2001) (19)
- REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs (2013) (18)
- Computing Along the Critical Path (2002) (18)
- Enabling dynamic heterogeneity through core-on-core stacking (2014) (16)
- Software data-triggered threads (2012) (16)
- Power-sensitive multithreaded architecture (2000) (16)
- Creating artificial global history to improve branch prediction accuracy (2009) (16)
- Classifying load and store instructions for memory renaming (1999) (16)
- Not All Features Are Equal: Discovering Essential Features for Preserving Prediction Privacy (2021) (15)
- Dynamic workload characterization for power efficient scheduling on CMP systems (2010) (15)
- Processor Power Reduction Via Single-ISA (2003) (15)
- Architecture-Level Power Optimization - What Are the Limits? (2005) (13)
- Design And Vlsi Implementation Of An On-Line Algorithm (1986) (13)
- Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments (2013) (13)
- Instruction recycling on a multiple-path processor (1999) (13)
- Low-current probabilistic writes for power-efficient STT-RAM caches (2013) (13)
- Hot peripheral thermal management to mitigate cache temperature variation (2012) (12)
- A comparison of core power gating strategies implemented in modern hardware (2014) (12)
- Battery Provisioning and Associated Costs for Data Center Power Capping (2012) (12)
- The Case For Colocation of HPC Workloads (2012) (11)
- Profile Guided Load Marking for Memory Renaming (1998) (11)
- Load-balanced pipeline parallelism (2013) (11)
- Packet Chasing: Spying on Network Packets over a Cache Side-Channel (2019) (10)
- ISPASS 2009: IEEE International symposium on Performance Analysis of Systems and Software (2009) (10)
- CDTT: Compiler-generated data-triggered threads (2014) (10)
- Thermal Time Shifting: Decreasing Data Center Cooling Costs with Phase-Change Materials (2017) (10)
- A Principled Approach to Learning Stochastic Representations for Privacy in Deep Neural Inference (2020) (10)
- Resistive Computation: A Critique (2014) (9)
- Proceedings of the 34th annual international symposium on Computer architecture (2007) (9)
- SecSMT: Securing SMT Processors against Contention-Based Covert Channels (2022) (9)
- Co-locating and concurrent fine-tuning MapReduce applications on microservers for energy efficiency (2017) (8)
- Retrospective: simultaneous multithreading: maximizing on-chip parallelism (1998) (8)
- Eliminating Redundant Computation and Exposing Parallelism through Data-Triggered Threads (2012) (7)
- Maximizing TLP with loop-parallelization on SMT (2001) (7)
- Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management (2019) (6)
- Shredder: Learning Noise to Protect Privacy with Partial DNN Inference on the Edge (2019) (6)
- Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures (2019) (6)
- Underclocked Software Prefetching: More Cores, Less Energy (2012) (6)
- Fast and Efficient Deployment of Security Defenses Via Context Sensitive Decoding (2019) (5)
- Compilation issues for a simultaneous multithreading processor (1996) (5)
- Dynamic Code Value Specialization Using the Trace Cache Fill Unit (2006) (5)
- Limits of task-based parallelism in irregular applications (2000) (5)
- Heterogeneous Computing [Guest editors' introduction] (2015) (4)
- Virtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change Materials (2018) (4)
- Reliability and Performance Trade-off Study of Heterogeneous Memories (2016) (4)
- Editorial: Special Section on CMP Architectures (2007) (3)
- Themis: Energy Efficient Management of Workloads in Virtualized Data Centers (2012) (3)
- Data-triggered Multithreading for Near-Data Processing (2013) (3)
- Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences (2009) (3)
- Critical-path aware processor architectures (2004) (2)
- Multithreaded Execution Architecture and Compilation (1999) (2)
- Memory Subsystem Design for Multithreaded Processors (1997) (2)
- Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology (2012) (2)
- Data Layout for Cache Performance on a Multithreaded Architecture (2011) (2)
- Exploring the Potential of Architecture-Level Power Optimizations (2003) (2)
- Optimizing processor architectures for power-efficiency (2003) (1)
- Agon: A Scalable Competitive Scheduler for Large Heterogeneous Systems (2021) (1)
- Shredder (2020) (1)
- Replication package for article: Automatically Eliminating Speculative Leaks from Cryptographic Code with Blade (2020) (1)
- Understanding the Impact of Socket Density in Density Optimized Servers (2019) (1)
- EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security (2022) (1)
- Retrospective on “Power-Sensitive Multithreaded Architecture” (2012) (1)
- Explorations in Symbiosis on two (1999) (1)
- Pitchfork-Angr (2020) (1)
- Inter-socket victim cacheing for platform power reduction (2010) (1)
- Platform-Agnostic Learning-Based Scheduling (2019) (1)
- Mitigating Speculative Execution Attacks via Context-Sensitive Fencing (2022) (1)
- 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA (2007) (1)
- Tuning Compiler Optimizations for Simultaneous (1997) (1)
- Interpretable Privacy for Deep Learning Inference (2020) (1)
- Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08) (2009) (1)
- Temperature-Aware DRAM Cache Management—Relaxing Thermal Constraints in 3-D Systems (2020) (1)
- Data prefetching via speculative precomputation on a simultaneous multithreaded processor (2004) (1)
- Fast cost efficient designs by building upon the plackett and burman method (2012) (0)
- Session details: Session 7A: Non-traditional Computer Systems (2016) (0)
- Reducing Leakage Power in Cache Peripheral Circuits of Embedded Processors (2011) (0)
- Accurately modeling GPGPU frequency scaling with the CRISP performance model (2017) (0)
- Session details: Memory subsystems (2010) (0)
- Introduction (2005) (0)
- Introduction (2004) (0)
- Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06) (2007) (0)
- The architecture of Efficient Multi-Core Processors: A Holistic Approach (2007) (0)
- Segue & ColorGuard: Optimizing SFI Performance and Scalability on Modern x86 (2022) (0)
- HCW Keynote Address Holistic Design of Multi-Core Architectures (2007) (0)
- Introduction (2006) (0)
- Editorial (2008) (0)
- UNLIKE THREADS IN PARALLEL PROGRAMS CREATED BY CONVENTIONAL PROGRAMMING, DATA-TRIGGERED THREADS ARE INITIATED WHEN A MEMORY VALUE IS CHANGED (2012) (0)
- Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05) (2005) (0)
- Coalition Threading: Combining traditional and non-traditional parallelism to maximize scalability (2012) (0)
- 2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar (2014) (0)
- Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07) (2008) (0)
- ASAR : Application-Specific Approximate Recovery to Mitigate Hardware Variability (2017) (0)
- Speculative Code Value Specialization Using the Trace Cache Fill Unit. (2006) (0)
- Session details: Memory subsystems (2010) (0)
- Introduction (2007) (0)
- Swarm Processor System: hardware process scheduler based energy efficient multi-core system (2014) (0)
- Going beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI (2023) (0)
- Session details: Session 7A: Non-traditional Computer Systems (2016) (0)
- Computer Science (Computer Engineering) (2013) (0)
- Holistic Design of Multiple-Core Architectures (2008) (0)
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