Dennis M. C. Sylvester

Dennis M. C. Sylvester's AcademicInfluence.com Rankings

Engineering

#3810

World Rank

#4937

Historical Rank

Electrical Engineering

#902

World Rank

#975

Historical Rank

engineering Degrees

Download Badge

Engineering

Dennis M. C. Sylvester's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

Why Is Dennis M. C. Sylvester Influential?

(Suggest an Edit or Addition)

(See a Problem?)

Dennis M. C. Sylvester's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits (2010) (825)
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation (2000) (503)
Theoretical and practical limits of dynamic voltage scaling (2004) (433)
Getting to the bottom of deep submicron (1998) (337)
A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V (2012) (290)
Analysis and mitigation of variability in subthreshold design (2005) (284)
Statistical Analysis and Optimization for VLSI: Timing and Power (2005) (279)
A highly resilient routing algorithm for fault-tolerant NoCs (2009) (249)
Ultralow-voltage, minimum-energy CMOS (2006) (237)
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018) (226)
A cubic-millimeter energy-autonomous wireless intraocular pressure monitor (2013) (223)
Vicis: A reliable network for unreliable silicon (2009) (209)
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells (2010) (206)
The Phoenix Processor: A 30pW platform for sensor applications (2008) (191)
A2: Analog Malicious Hardware (2016) (188)
A global wiring paradigm for deep submicron design (2000) (184)
A Modular 1 mm$^{3}$ Die-Stacked Sensing Platform With Low Power I$^{2}$C Inter-Die Communication and Multi-Modal Energy Harvesting (2013) (184)
Modeling and analysis of crosstalk noise in coupled RLC interconnects (2006) (178)
Statistical analysis of subthreshold leakage current for VLSI circuits (2004) (178)
A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode (2009) (175)
Exploring Variability and Performance in a Sub-200-mV Processor (2008) (174)
Pushing ASIC performance in a power envelope (2003) (172)
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM (2008) (169)
A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory (2016) (165)
Analytical modeling and characterization of deep-submicrometer interconnect (2001) (165)
Energy-Efficient Subthreshold Processor Design (2009) (163)
Power gating with multiple sleep modes (2006) (159)
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction (2013) (159)
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating (2007) (154)
Gate oxide leakage current analysis and reduction for VLSI circuits (2004) (154)
Underdesigned and Opportunistic Computing in Presence of Hardware Variability (2013) (152)
Yield-Driven Near-Threshold SRAM Design (2010) (148)
Parametric yield estimation considering leakage variability (2004) (145)
Statistical optimization of leakage power considering process variations using dual-Vth and sizing (2004) (144)
Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor (2011) (144)
A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes (2014) (136)
Impact of small process geometries on microarchitectures in systems on a chip (2001) (134)
Modeling and analysis of leakage power considering within-die process variations (2002) (133)
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring (2015) (129)
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon (2006) (128)
An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler (2014) (128)
Nanometer Device Scaling in Subthreshold Logic and SRAM (2008) (127)
Statistical estimation of leakage current considering inter- and intra-die process variation (2003) (126)
An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique (1996) (126)
IoT design space challenges: Circuits and systems (2014) (125)
Analysis and minimization techniques for total leakage considering gate oxide leakage (2003) (125)
An ultra low power 1V, 220nW temperature sensor for passive wireless applications (2008) (124)
A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems (2017) (118)
A modular 1mm3 die-stacked sensing platform with optical communication and multi-modal energy harvesting (2012) (116)
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling (2005) (116)
Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation (2008) (112)
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors (2007) (109)
Energy efficient near-threshold chip multi-processing (2007) (107)
Getting to the bottom of deep submicron II: a global wiring paradigm (1999) (105)
High performance level conversion for dual V/sub DD/ design (2004) (104)
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (2004) (103)
Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source (2008) (102)
Design sensitivities to variability: extrapolations and assessments in nanometer VLSI (2002) (102)
Gate-length biasing for runtime-leakage control (2006) (101)
A Sub-200mV 6T SRAM in 0.13μm CMOS (2007) (98)
Bubble Razor: An architecture-independent approach to timing-error detection and correction (2012) (96)
Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection (2006) (95)
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (2005) (95)
A Reliable Routing Architecture and Algorithm for NoCs (2012) (93)
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells (2013) (92)
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation (2005) (92)
Variational delay metrics for interconnect timing analysis (2004) (91)
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores (2012) (91)
Reliability modeling and management in dynamic microprocessor-based systems (2006) (90)
A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems (2007) (90)
Selective gate-length biasing for cost-effective runtime leakage control (2004) (88)
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation (1998) (85)
14.2 A physically unclonable function with BER <10−8 for robust chip authentication using oscillator collapse in 40nm CMOS (2015) (82)
Swizzle-Switch Networks for Many-Core Systems (2012) (81)
Variability in nanometer CMOS: Impact, analysis, and minimization (2008) (80)
A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution (2013) (80)
Circuit Design Advances for Wireless Sensing Applications (2010) (80)
A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out (2010) (80)
Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor (2007) (79)
8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic (2015) (79)
16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS (2014) (78)
9.2 A 0.6nJ −0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence (2017) (77)
Minimizing total power by simultaneous Vdd/Vth assignment (2004) (77)
Low power circuit design based on heterojunction tunneling transistors (HETTs) (2009) (77)
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence (2017) (71)
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM (2014) (71)
A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering (2006) (71)
An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations (2016) (71)
A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS (2012) (69)
An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits (2006) (68)
A new algorithm for improved VDD assignment in low power dual VDD systems (2004) (68)
An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution (1997) (68)
System-Level Performance Modeling with BACPAC - Berkeley Advanced Chip Performance Calculator (1999) (68)
24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis (2014) (67)
Process variation and temperature-aware reliability management (2010) (66)
A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System (2014) (64)
27.6 A 0.7pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge (2015) (64)
A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting (2014) (63)
A hybrid DC-DC converter for sub-microwatt sub-1V implantable applications (2009) (62)
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails (2014) (61)
A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining (2011) (61)
Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security (2018) (61)
8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability (2017) (61)
Advanced timing analysis based on post-OPC extraction of critical dimensions (2005) (61)
12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes (2014) (60)
23.3 A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter (2014) (60)
Reconfigurable energy efficient near threshold cache architectures (2008) (58)
Efficient Monte Carlo based incremental statistical timing analysis (2008) (58)
A 150pW program-and-hold timer for ultra-low-power sensor platforms (2009) (58)
14.2 A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration (2019) (57)
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing (2020) (57)
Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS (2013) (56)
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor (2016) (56)
15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR (2014) (56)
High Performance Level Conversion for Dual Design (2004) (56)
Toward a methodology for manufacturability-driven design rule exploration (2004) (56)
A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination (2018) (55)
Active shields: a new approach to shielding global wires (2002) (55)
Ultralow Power Circuit Design for Wireless Sensor Nodes for Structural Health Monitoring (2016) (55)
Rethinking Deep-Submicron Circuit Design (1999) (54)
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation (2005) (53)
Effects of global interconnect optimizations on performance estimation of deep submicron design (2000) (53)
Future performance challenges in nanometer design (2001) (53)
A 5.8 nW CMOS Wake-Up Timer for Ultra-Low-Power Wireless Applications (2015) (53)
Modeling of non-uniform device geometries for post-lithography circuit analysis (2006) (53)
A fully integrated microbattery for an implantable microelectromechanical system (2008) (52)
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs) (2013) (52)
Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC (2017) (52)
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS (2015) (52)
Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey (2017) (52)
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS (2010) (52)
Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design (2003) (51)
GTX: the MARCO GSRC technology extrapolation system (2000) (51)
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems (2008) (51)
Optimal technology selection for minimizing energy and variability in low voltage applications (2008) (50)
CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing (2011) (50)
Energy Optimality and Variability in Subthreshold Design (2006) (50)
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing (2015) (50)
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization (2011) (50)
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias (2008) (49)
On-chip cross talk noise model for deep-submicrometer ULSI interconnect (1998) (49)
A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs (2016) (49)
An Energy Efficient Parallel Architecture Using Near Threshold Operation (2007) (49)
A Successive-Approximation Switched-Capacitor DC–DC Converter With Resolution of $V_{\text{IN}}/{2^N}$ for a Wide Range of Input and Output Voltages (2016) (49)
Power-Driven Challenges in Nanometer Design (2001) (48)
Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion (2002) (48)
Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation (2012) (47)
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS (2013) (47)
A 0.5V 2.2pW 2-transistor voltage reference (2009) (47)
Tradeoffs between gate oxide leakage and delay for dual T/sub ox/ circuits (2004) (47)
A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems (2016) (47)
Assessing the performance limits of parallelized near-threshold computing (2012) (47)
Logic SER reduction through flip flop redesign (2006) (46)
A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes (2013) (45)
Soft-edge flip-flops for improved timing yield: design and optimization (2007) (45)
A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs (2014) (44)
Statistical interconnect metrics for physical-design optimization (2006) (43)
Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design (2007) (43)
A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications (2012) (43)
Centip3De: A 64-Core, 3D Stacked Near-Threshold System (2012) (42)
A 20-pW Discontinuous Switched-Capacitor Energy Harvester for Smart Sensor Applications (2017) (42)
Timing yield enhancement through soft edge flip-flop based design (2008) (42)
A true random number generator using time-dependent dielectric breakdown (2011) (41)
A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme (2011) (41)
8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems (2016) (41)
A 95fJ/b current-mode transceiver for 10mm on-chip interconnect (2013) (41)
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor (2018) (41)
In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter (2010) (39)
SLC: Split-control Level Converter for dense and stable wide-range voltage conversion (2012) (38)
A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes (2016) (38)
Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor (2011) (38)
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools (2003) (38)
Approximate SRAMs With Dynamic Energy-Quality Management (2016) (38)
RF-Echo: A Non-Line-of-Sight Indoor Localization System Using a Low-Power Active RF Reflector ASIC Tag (2017) (38)
Efficient generation of delay change curves for noise-aware static timing analysis (2002) (38)
A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording (2014) (37)
Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid (2015) (37)
A 695 pW standby power optical wake-up receiver for wireless sensor nodes (2012) (37)
A 0.45–0.7V sub-microwatt CMOS image sensor for ultra-low power applications (2009) (36)
Performance optimization of critical nets through active shielding (2004) (36)
RLC signal integrity analysis of high-speed global interconnects [CMOS] (2000) (36)
Nanometer Device Scaling in Subthreshold Circuits (2007) (35)
A 5.42nW/kB retention power logic-compatible embedded DRAM with 2T dual-Vt gain cell for low power sensing applications (2010) (35)
Clock buffer and wire sizing using sequential programming (2006) (34)
Analog in-memory subthreshold deep neural network accelerator (2017) (34)
Design of an implantable power supply for an intraocular sensor, using POWER (power optimization for wireless energy requirements) (2007) (33)
A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis (2006) (33)
OxID: On-chip one-time random ID generation using oxide breakdown (2010) (33)
A statistical approach for full-chip gate-oxide reliability analysis (2008) (33)
A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology (2017) (33)
Single stage static level shifter design for subthreshold to I/O voltage conversion (2008) (33)
A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell (2017) (32)
A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation (2013) (32)
Clock network design for ultra-low power applications (2010) (32)
Stress aware layout optimization (2008) (32)
A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks (2016) (31)
A 99nW 70.4kHz resistive frequency locking on-chip oscillator with 27.4ppm/ºC temperature stability (2015) (31)
1 A 2 . 9 TOPS / W Deep Convolutional Neural Network SoC in FD-SOI 28 nm for Intelligent Embedded Systems (2017) (31)
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS (2014) (31)
21.5 A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems (2016) (31)
An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration (2019) (31)
OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain (2019) (31)
A Resonant Current-Mode Wireless Power Receiver and Battery Charger With −32 dBm Sensitivity for Implantable Systems (2016) (31)
System-On-Mud: Ultra-Low Power Oceanic Sensing Platform Powered by Small-Scale Benthic Microbial Fuel Cells (2015) (30)
12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback (2016) (30)
LC2: Limited contention level converter for robust wide-range voltage conversion (2011) (30)
27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications (2014) (30)
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves (2003) (30)
Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire (2014) (30)
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization (2007) (30)
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design (2011) (29)
Low-power on-chip communication based on transition-aware global signaling (TAGS) (2004) (29)
Timing error correction techniques for voltage-scalable on-chip memories (2005) (29)
Performance-driven OPC for mask cost reduction (2005) (29)
A 0.04MM316NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement (2018) (29)
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (2004) (29)
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance (2008) (29)
Analytical yield prediction considering leakage/performance correlation (2006) (28)
Yield-driven near-threshold SRAM design (2007) (28)
Concurrent sizing, Vdd and V/sub th/ assignment for low-power design (2004) (28)
26.9 A 0.19×0.17mm2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry (2020) (28)
Simultaneous state, Vt and Tox assignment for total standby power minimization (2004) (28)
Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for Unattended Ground Sensor Nodes (2018) (28)
Simple metrics for slew rate of RC circuits based on two circuit moments (2004) (28)
A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$ (2018) (28)
A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS (2017) (28)
A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm (2016) (28)
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold (2012) (28)
Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment (2003) (28)
Robust ultra-low voltage ROM design (2008) (28)
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs (2011) (27)
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination (2019) (27)
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design (2005) (27)
Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques (2011) (27)
21.4 A >78%-efficient light harvester over 100-to-100klux with reconfigurable PV-cell network and MPPT circuit (2016) (27)
17.2 A 142nW Voice and Acoustic Activity Detection Chip for mm-Scale Sensor Nodes Using Time-Interleaved Mixer-Based Frequency Scanning (2019) (27)
Characterization of interconnect coupling noise using in-situ delay-change curve measurements (2000) (27)
Modeling and analysis of parametric yield under power and performance constraints (2005) (27)
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS (2014) (27)
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS (2012) (27)
A black box method for stability analysis of arbitrary SRAM cell structures (2010) (26)
A 2.5nJ duty-cycled bridge-to-digital converter integrated in a 13mm3 pressure-sensing system (2018) (26)
An effective capacitance based driver output model for on-chip RLC interconnects (2003) (26)
Self-compensating design for focus variation (2005) (26)
Leakage-and crosstalk-aware bus encoding for total power reduction (2004) (26)
Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems (2012) (25)
Standby power reduction techniques for ultra-low power processors (2008) (25)
Gate-level mitigation techniques for neutron-induced soft error rate (2005) (25)
Dynamic NBTI management using a 45nm multi-degradation sensor (2010) (25)
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM (2012) (25)
21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification (2017) (24)
Leakage power reduction using stress-enhanced layouts (2008) (24)
A fully integrated switched-capacitor based PMU with adaptive energy harvesting technique for ultra-low power sensing applications (2013) (24)
A simple method for on-chip, sub-femto Farad interconnect capacitance measurement (1997) (24)
A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM (2018) (24)
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies (2007) (24)
Transistor and pin reordering for gate oxide leakage reduction in dual T/sub ox/ circuits (2004) (24)
A 1.07 Tbit/s 128×128 swizzle network for SIMD processors (2010) (24)
Parametric yield analysis and constrained-based supply voltage optimization (2005) (24)
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS (2014) (24)
Recryptor: A reconfigurable in-memory cryptographic Cortex-M0 processor for IoT (2017) (23)
A new analytical delay and noise model for on-chip RLC interconnect (2000) (23)
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS (2014) (23)
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~\mu$ W/Channel in 65-nm CMOS (2019) (23)
Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part I—Analog Circuit Techniques (2017) (23)
A robust −40 to 120°C all-digital true random number generator in 40nm CMOS (2015) (23)
Performance-driven optical proximity correction for mask cost reduction (2007) (22)
An Acoustic Signal Processing Chip With 142-nW Voice Activity Detection Using Mixer-Based Sequential Frequency Scanning and Neural Network Classification (2019) (22)
A simple metric for slew rate of RC circuits based on two circuit moments (2003) (22)
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling (2001) (22)
5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme (2016) (22)
Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment (2005) (21)
Robust Clock Network Design Methodology for Ultra-Low Voltage Operations (2011) (21)
Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS (2007) (21)
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering (2016) (21)
5.2 Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications (2019) (21)
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation (2012) (21)
Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis (2011) (21)
Shortstop: An on-chip fast supply boosting technique (2013) (21)
A 1.02nW PMOS-only, trim-free current reference with 282ppm/°C from −40°C to 120°C and 1.6% within-wafer inaccuracy (2017) (21)
Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering (2014) (21)
Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion (2007) (21)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2018) (21)
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS (2013) (20)
Circuit impact and skew-corner analysis of stochastic process variation in global interconnect (1999) (20)
A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell (2015) (20)
Investigation of diffusion rounding for post-lithography analysis (2008) (20)
A fixed-point neural network for keyword detection on resource constrained hardware (2015) (20)
A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation (2020) (19)
Bus encoding for total power reduction using a leakage-aware buffer configuration (2005) (19)
A robust alternate repeater technique for high performance busses in the multi-core era (2008) (19)
Circuit and system design guidelines for ultra-low power sensor nodes (2012) (19)
Battery Voltage Supervisors for Miniature IoT Systems (2016) (18)
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS (2016) (18)
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures (2008) (18)
Dual-slope capacitance to digital converter integrated in an implantable pressure sensing system (2015) (18)
A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector (2018) (18)
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes (2017) (18)
Process variability-aware transient fault modeling and analysis (2008) (18)
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI (2016) (17)
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength (2005) (17)
Approaches to run-time and standby mode leakage reduction in global buses (2004) (17)
3 A 3 nW Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor DC-DC Converter (2014) (17)
A robust edge encoding technique for energy-efficient multi-cycle interconnect (2007) (17)
Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part II—Data Communication, Energy Harvesting, Power Management, and Digital Circuits (2017) (17)
Modeling crosstalk in statistical static timing analysis (2008) (17)
A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory (2015) (17)
An efficient surface-based low-power buffer insertion algorithm (2005) (17)
Fast and Accurate Waveform Analysis with Current Source Models (2008) (17)
65nW CMOS temperature sensor for ultra-low power microsystems (2013) (16)
A novel buffer circuit for energy efficient signaling in dual-VDD systems (2005) (16)
Overview of a cyber-enabled wireless monitoring system for the protection and management of critical infrastructure systems (2009) (16)
Wide input range 1.7μW 1.2kS/s resistive sensor interface circuit with 1 cycle/sample logarithmic sub-ranging (2015) (16)
Improved a priori interconnect predictions and technology extrapolation in the GTX system (2003) (16)
A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme (2014) (16)
Layout verification and optimization based on flexible design rules (2006) (16)
Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes (2010) (16)
A 1920 $\times$ 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching (2019) (16)
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (2009) (15)
Process-induced skew reduction in nominal zero-skew clock trees (2006) (15)
A 0 . 3 V VDDmin 4 + 2 T SRAM for Searching and In-Memory Computing Using 55 nm DDC Technology (2018) (15)
A simplifiediyansmission-line based crosstalk noise model for on-chip RLC wiring (2004) (15)
Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC (2019) (15)
A Dual-VDD Boosted Pulsed Bus Technique for Low Power and Low Leakage Operation (2006) (15)
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses (2005) (15)
On the decreasing significance of large standard cells in technology mapping (2008) (15)
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices (2017) (14)
Self-Timed Regenerators for High-Speed and Low-Power Interconnect (2007) (14)
FFT Core with Super-Pipelining (2011) (14)
A 380pW dual mode optical wake-up receiver with ambient noise cancellation (2016) (14)
Impact Ionization Nanowire Transistor with Multiple-Gates, Silicon-Germanium Impact Ionization Region, and Sub-5 mV/decade Subtheshold Swing (2007) (14)
An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC (2016) (14)
All-digital SoC thermal sensor using on-chip high order temperature curvature correction (2015) (14)
DVS for on-chip bus designs based on timing error correction (2005) (14)
Power distribution techniques for dual VDD circuits (2006) (14)
Static Leakage Reduction through Simulteneous VTT/TOX and State Assignment (2004) (14)
Near Threshold Computing : Overcoming Performance Degradation from Aggressive Voltage Scaling (2009) (14)
Variation-aware gate sizing and clustering for post-silicon optimized circuits (2008) (14)
SWIFT: A 2.1Tb/s 32×32 self-arbitrating manycore interconnect fabric (2011) (14)
Near-threshold computing in FinFET technologies: Opportunities for improved voltage scalability (2016) (14)
NSF expedition on variability-aware software: Recent results and contributions (2015) (14)
A 1.7nW PLL-assisted current injected 32KHz crystal oscillator for IoT (2017) (14)
Criticality Aware Latin Hypercube Sampling for Efficient Statistical Timing Analysis (2007) (14)
Accurate in-situ measurement of peak noise and signal delay induced by interconnect coupling (2000) (13)
Statistical modeling of cross-coupling effects in VLSI interconnects (2005) (13)
Advanced timing analysis based on post-OPC patterning process simulations (2005) (13)
Active learning framework for post-silicon variation extraction and test cost reduction (2010) (13)
19.2 A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation (2019) (13)
Gate Oxide Leakage and Delay Tradeoffs for Dual Tox Circuits (2005) (13)
A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications (2015) (13)
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier (2019) (13)
Exploiting the analog properties of digital circuits for malicious hardware (2017) (13)
Near-field communication using phase-locking and pulse signaling for millimeter-scale systems (2009) (13)
Low-voltage circuit design for widespread sensing applications (2008) (13)
Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs (2012) (13)
Compact HSPICE model for IMOS device (2008) (13)
Runtime leakage power estimation technique for combinational circuits (2007) (13)
Spice up your MOSFET modelling (2003) (12)
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware (2018) (12)
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation (2017) (12)
Early detection of oxide breakdown through in situ degradation sensing (2010) (12)
Total leakage optimization strategies for multi-level caches (2005) (12)
Active shielding of RLC global interconnects (2002) (12)
Post-fabrication measurement-driven oxide breakdown reliability prediction and management (2009) (12)
Clock tree synthesis with data-path sensitivity matching (2008) (12)
Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization (2005) (12)
Victim alignment in crosstalk aware timing analysis (2007) (11)
Design for manufacturability: challenges and opportunities (2005) (11)
Low power battery supervisory circuit with adaptive battery health monitor (2014) (11)
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment (2005) (11)
Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits (2005) (11)
2 A Physically Unclonable Function with BER < 10-8 for Robust Chip Authentication Using Oscillator Collapse in 40 nm CMOS (2018) (11)
Limits of Parallelism and Boosting in Dim Silicon (2013) (11)
A general framework for probabilistic low-power design space exploration considering process variation (2004) (11)
A 6×5×4mm3 general purpose audio sensor node with a 4.7μW audio processing IC (2017) (11)
Optimization objectives and models of variation for statistical gate sizing (2005) (11)
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and 3-D simulation (1997) (11)
Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion (2009) (11)
Millimeter-scale computing platform for next generation of Internet of Things (2016) (11)
27.2 An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain (2019) (11)
A 635pW battery voltage supervisory circuit for miniature sensor nodes (2012) (11)
A 4.7nW 13ppm/°C Self-Biased Wakeup Timer Using a Switched-Resistor Scheme. (2016) (10)
Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS (2011) (10)
Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling (2009) (10)
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment (2017) (10)
Mechanical stress aware optimization for leakage power reduction (2010) (10)
Low power interconnects for SIMD computers (2011) (10)
Switch-factor based loop RLC modeling for efficient timing analysis (2003) (10)
A New Technique for Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits (2006) (10)
The Internet of Tiny Things: Recent Advances of Millimeter-Scale Computing (2019) (10)
IoT2 — the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die Stacking (2019) (10)
Transition aware global signaling (TAGS) (2002) (10)
Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization (2010) (10)
Analytical performance models for RLC interconnects and application to clock optimization (2002) (10)
A dense 45nm half-differential SRAM with lower minimum operating voltage (2011) (10)
Impact of FinFET on Near-Threshold Voltage Scalability (2017) (10)
An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages (2003) (10)
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic (2009) (10)
A 260µW infrared gesture recognition system-on-chip for smart devices (2016) (10)
A 10.6mm3 fully-integrated, wireless sensor node with 8GHz UWB transmitter (2015) (9)
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service (2012) (9)
RedCooper: Hardware Sensor Enabled Variability Software Testbed for Lifetime Energy Constrained Application (2014) (9)
Investigation of performance metrics for interconnect stack architectures (2004) (9)
Design and Evaluation of Confidence-Driven Error-Resilient Systems (2014) (9)
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses (2004) (9)
A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency Cancellation (2018) (9)
8 ppm / ° C Self-Biased Wakeup Timer Using a Switched-Resistor Scheme (2017) (9)
Sensor-Driven Reliability and Wearout Management (2009) (9)
Design time body bias selection for parametric yield improvement (2010) (9)
Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems (2017) (9)
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise (2010) (9)
Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry (2012) (9)
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS (2015) (9)
Shaping gate channels for improved devices (2008) (9)
3 A 23 Mb / s 23 pJ / b Fully Synthesized True-Random-Number Generator in 28 nm and 65 nm CMOS (2018) (8)
STEEL: A technique for stress-enhanced standard cell library design (2008) (8)
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing (2013) (8)
An Open-source Framework for Autonomous SoC Design with Analog Block Generation (2020) (8)
A 4.7μW switched-bias MEMS microphone preamplifier for ultra-low-power voice interfaces (2017) (8)
A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms (2013) (8)
A two-tiered self-powered wireless monitoring system architecture for bridge health management (2010) (8)
A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple (2015) (8)
Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform (2015) (8)
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and Data Telemetry (2022) (8)
ISSCC 2017 / SESSION 14 / DEEP-LEARNING PROCESSORS / 14 . 7 14 . 7 A 288 μW Programmable Deep-Learning Processor with 270 KB On-Chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence (2018) (8)
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse (2015) (8)
Fine grained multi-threshold CMOS for enhanced leakage reduction (2006) (8)
Closed-form modeling of layout-dependent mechanical stress (2010) (8)
Circuit techniques for miniaturized biomedical sensors (2014) (8)
Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage (2005) (8)
Energy-optimized high performance FFT processor (2011) (7)
Synchronization of ultra-low power wireless sensor nodes (2011) (7)
Switch-factor based loop RLC modeling for efficient timing analysis (2003) (7)
A confidence-driven model for error-resilient computing (2011) (7)
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design (2002) (7)
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator (2021) (7)
Analyzing electrical effects of RTA-driven local anneal temperature variation (2010) (7)
Runtime Leakage Minimization Through Probability-Aware Optimization (2006) (7)
ISSCC 2016 / SESSION 21 / HARVESTING AND WIRELESS POWER / 21 . 4 21 . 4 A > 78 %-Efficient Light Harvester over 100-to-100 klux with Reconfigurable PV-Cell Network and MPPT Circuit (2017) (7)
An Analytical Crosstalk Model with Application to ULSI Interconnect Scaling (1998) (7)
A ripple voltage sensing MPPT circuit for ultra-low power microsystems (2013) (7)
A Reconfigurable Sense Amplifier with Auto-Zero Calibration and Pre-Amplification in 28 nm CMOS (2018) (7)
A complementary-I-MOS technology featuring SiGe channel and i-region for enhancement of impact-ionization, breakdown voltage, and performance (2007) (7)
Power Optimization using Multiple Supply Voltages (2007) (7)
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems (2012) (7)
A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers (2011) (7)
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect (2008) (7)
24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS (2016) (6)
3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection (2020) (6)
Achieving Ultralow Standby Power With an Efficient SCCMOS Bias Generator (2013) (6)
When Homogeneous becomes Heterogeneous Wearout Aware Task Scheduling for Streaming Applications (2007) (6)
Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect (2015) (6)
Extended dynamic voltage scaling for low power design (2004) (6)
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles (2018) (6)
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation (2007) (6)
Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits (2019) (6)
Analysis and design of level-converting flip-flops for dual-V/sub dd//V/sub th/ integrated circuits (2003) (6)
Crosshairs SRAM — An adaptive memory for mitigating parametric failures (2010) (6)
Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur (2021) (6)
Variability analysis of a digitally trimmable ultra-low power voltage reference (2010) (6)
A Dual-Stage, Ultra-Low-Power Acoustic Event Detection System (2016) (6)
A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric Amplification (2018) (5)
Toward performance-driven reduction of the cost of RET-based lithography control (2003) (5)
Minimizing Total Power by Simultaneous Assignment (2004) (5)
Chip-on-mud: Ultra-low power ARM-based oceanic sensing system powered by small-scale benthic microbial fuel cells (2014) (5)
Measurement techniques and interconnect estimation (2000) (5)
4.4 A sub-nW 80mlx-to-1.26Mlx self-referencing light-to-digital converter with AlGaAs photodiode (2017) (5)
Line-End Shortening is Not Always a Failure (2007) (5)
A 1.74.12 mm3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation (2019) (5)
A Noise-Efficient Neural Recording Amplifier Using Discrete-Time Parametric Amplification (2018) (5)
Chip-Level Assembly ( And Not the Integration of Synthesis and Physical ) Is the Key to DSM Design (1999) (5)
Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC buses (2003) (5)
A Light Tolerant Neural Recording IC for Near-Infrared-Powered Free Floating Motes (2021) (5)
Low power wireless sensor networks for infrastructure monitoring (2012) (5)
Sensor data retrieval using alignment independent capacitive signaling (2008) (5)
Power-aware global signaling strategies (2005) (5)
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems (2012) (5)
A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur (2019) (5)
Clock net optimization using active shielding (2003) (5)
ISSCC 2016 / SESSION 8 / LOW-POWER DIGITAL CIRCUITS / 8 . 5 8 . 5 A 60 %-Efficiency 20 nW-500 μ W Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for IoT Systems (2018) (4)
1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge Processors (2020) (4)
FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node (2015) (4)
A Statistical Framework for Post-Fabrication Oxide Breakdown Reliability Prediction and Management (2013) (4)
Demo: Ultra-constrained sensor platform interfacing (2012) (4)
Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating (2013) (4)
Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI (2014) (4)
Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation (2006) (4)
A dual-passband filter architecture for dual-band systems (2011) (4)
A new threshold voltage assignment scheme for runtime leakage reduction in on-chip repeaters (2004) (4)
A 0.3-V to 1.8–3.3-V Leakage-Biased Synchronous Level Converter for ULP SoCs (2020) (4)
Reconfigurable Multicore Server Processors for Low Power Operation (2009) (4)
A 40-nm Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent IoT Sensors (2021) (4)
45pW ESD clamp circuit for ultra-low power applications (2013) (4)
An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM (2020) (4)
An ultra-wide program, 122pJ/bit flash memory using charge recycling (2017) (3)
Variation-aware analysis: savior of the nanometer era? (2006) (3)
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks (2021) (3)
A 256 pixel, 21.6 μW infrared gesture recognition processor for smart devices (2019) (3)
A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates (2022) (3)
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries (2018) (3)
Interconnect performance corners considering crosstalk noise (2009) (3)
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2019) (3)
From digital processors to analog building blocks: Enabling new applications through ultra-low voltage design (2012) (3)
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries (2019) (3)
AA-ResNet: Energy Efficient All-Analog ResNet Accelerator (2020) (3)
Optimal inductance for on-chip RLC interconnections (2003) (3)
An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration (2018) (3)
Crosstalk-aware PWM-based on-chip global signaling in 65nm CMOS (2009) (3)
A1920 × 1080 25FPS, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation (2018) (3)
Top-k Aggressors Sets in Delay Noise Analysis (2007) (3)
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect (2011) (3)
Millimeter-Scale Ultra-Low-Power Imaging System for Intelligent Edge Monitoring (2022) (3)
1 A 4 . 5 Tb / s 3 . 4 Tb / s / W 64 × 64 Switch Fabric with Self-Updating Least-Recently-Granted Priority and Quality-of-Service Arbitration in 45 nm CMOS (2018) (3)
Runtime leakage minimization through probability-aware dual-V/sub t/ or dual-T/sub ox/ assignment (2005) (3)
A 1.6nJ/bit, 19.9μA peak current fully integrated 2.5mm2 inductive transceiver for volume-constrained microsystems (2014) (3)
8 A 32 kb SRAM for Error-Free and Error-Tolerant Applications with Dynamic Energy-Quality Management in 28 nm CMOS (2018) (3)
A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control (2020) (3)
A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applications (2016) (3)
Energy-Optimal Circuit Design (2007) (3)
Ultra-low power circuit techniques for miniaturized sensor nodes (2015) (3)
A 1920 $\times $ 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles (2018) (3)
An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs (2012) (3)
F1: Intelligent energy-efficient systems at the edge of IoT (2018) (3)
Racetrack converter: A low power and compact data converter using racetrack spintronic devices (2015) (3)
A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge (2020) (2)
Joining the design and mask flows for better and cheaper masks (2004) (2)
XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems (2012) (2)
Rectified-linear and recurrent neural networks built with spin devices (2017) (2)
A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection (2022) (2)
A new asymmetric skewed buffer design for runtime leakage power reduction (2005) (2)
A library compatible driver output model for on-chip RLC transmission lines (2004) (2)
Achieving continuous VT performance in a dual VT process (2005) (2)
A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS Biasing (2022) (2)
ISQED 2004 Proceedings 5th International Symposium on Quality Electronic Design (2004) (2)
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels (2015) (2)
The great interconnect buffering debate: are you a chicken or an ostrich? (2004) (2)
An ultra-low-power biomedical chip for injectable pressure monitor (2015) (2)
Designing robust ultra-low power circuits (2008) (2)
A Physics-based Compact Model for I-MOS Transistors (2007) (2)
Measurement-Based Interconnect Capacitance Characterization for Circuit Simulations (1998) (2)
Cache Automaton: Repurposing Caches for Automata Processing (2017) (2)
A standard cell compatible bidirectional repeater with thyristor assist (2012) (2)
Design-patterning co-optimization of SRAM robustness for double patterning lithography (2012) (2)
Circuit design advances to enable ubiquitous sensing environments (2010) (2)
Bae Systems Mission Specific Processor Technology (2003) (2)
Phoenix: an Ultra-Low Power Processor for Cubic Millimeter Sensor Systems (2009) (2)
A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers (2017) (2)
An Analog-Assisted Digital LDO With Single Subthreshold Output pMOS Achieving 1.44-fs FOM (2021) (2)
Sample and Average Common-Mode Feedback in a 101 nW Acoustic Amplifier (2020) (2)
A low-power VGA full-frame feature extraction processor (2013) (2)
Low-power switched-capacitor converter design techniques for small IoT systems (2017) (2)
A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference (2017) (2)
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices (2010) (2)
Ultra-Low Power 32kHz Crystal Oscillators: Fundamentals and Design Techniques (2021) (1)
A 43nW 32kHz Pulsed Injection TCXO with 4.2ppm Accuracy Using ∆Σ Modulated Load Capacitance (2021) (1)
Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC (2018) (1)
An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration (2022) (1)
A 346μm2 reference-free sensor interface for highly constrained microsystems in 28nm CMOS (2013) (1)
A Double-Gate Tunneling Field-Effect Transistor with Silicon-Germanium Source for High-Performance, Low Standby Power, and Low Power Technology Applications (2007) (1)
Proceedings of the 2003 international workshop on System-level interconnect prediction (2002) (1)
Ultra-constrained sensor platform interfacing (2012) (1)
A lower bound computation method for evaluation of statistical design techniques (2010) (1)
Design Strategies for Ultra-Low Voltage Circuits (2006) (1)
A wire-overhead-free reset propagation scheme for millimeter-scale sensor systems (2017) (1)
Design Techniques of Integrated Power Management Circuits for Low Power Edge Devices (2021) (1)
A 192 nW 0.02 Hz High Pass Corner Acoustic Analog Front-End with Automatic Saturation Detection and Recovery (2021) (1)
A 0 . 5 V 3 . 6 ppm / oC 2 . 2 pW 2-Transistor Voltage Reference (2009) (1)
Circuits for ultra-low power millimeter-scale sensor nodes (2012) (1)
Vlsi Design Curriculum (2004) (1)
Design and Optimization of Hybrid Power Systems for Fully Implantable Medical Devices (2006) (1)
A library compatible driving point model for on-chip RLC interconnects (2002) (1)
A 210×340×50µm Integrated CMOS System f0r Micro-Robots with Energy Harvesting, Sensing, Processing, Communication and Actuation (2022) (1)
14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC (2021) (1)
22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systems (2017) (1)
Supply boosting for high-performance processors in flip-chip packages (2016) (1)
Analysis and optimization of SRAM robustness for double patterning lithography (2010) (1)
Intraocular Pressure Monitor (2011) (1)
Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS (2010) (1)
Design of Hybrid Implantable Power Systems (HIPS): Optimization Based on Fundamentals of Materials and Energetics (2007) (1)
2003 International Workshop on System-Level Interconnect Prediction (SLIP) (2003) (1)
Low voltage circuit design techniques for cubic-millimeter computing (2009) (1)
Achieving continuous V/sub T/ performance in a dual V/sub T/ process (2005) (1)
Analysis and measurement of the stability of dual-resonator oscillators (2012) (1)
Adaptive robustness tuning for high performance domino logic (2011) (1)
Adaptive sensing and design for reliability (2010) (1)
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries (2017) (1)
A$\mu$Processor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C (2020) (1)
45 pW ESD Clamp Circuit for Ultra-Low Power Applications (2018) (1)
OVERCOMING MOORE ’ S CURSE : TECHNIQUES FOR POWERING LARGE TRANSISTOR COUNTS IN SUB-45 NM TECHNOLOGIES (2009) (1)
A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter (2022) (1)
Circuit design advances for ultra-low power sensing platforms (2010) (1)
Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications (2018) (1)
Self-Calibrating GPS Accelerator Implemented Using Analog Calculation in 65 nm LP CMOS (2017) (1)
New Associate Editor (2022) (0)
Statistical Sampling Under Variability (2007) (0)
Chip-to-Chip Proximity Communication (2007) (0)
A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend (2023) (0)
ADualVDD Boosted Pulsed BusTechnique forLowPower andLowLeakage Operation (2006) (0)
System-Level Reliability Factors and Implications on Real-Time Monitoring (2007) (0)
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End (2022) (0)
A Statistical Framework forPost-Silicon Tuning through BodyBiasClustering (2006) (0)
Session details: Special purpose processing (2005) (0)
29.3 An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees (2023) (0)
Low-Power Resistive Bridge Readout Circuit Integrated in Two Millimeter-Scale Pressure-Sensing Systems (2019) (0)
A New Algorithm for Improwed VDQ Assignment in Low Power Qual VDD Systems (2004) (0)
Session details: Interconnect analysis for SoCs and microprocessors (2004) (0)
A Continuous Acoustic Sensing Microsystem for Event Identification (2017) (0)
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware (2016) (0)
A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence (2022) (0)
Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference (2017) (0)
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee (2018) (0)
The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings (2003) (0)
International Solid-State Circuits Conference ISSCC 2016 / SESSION 8 / LOW-POWER DIGITAL CIRCUITS / 8 . 8 8 . 8 iRazor : 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R 4 Processor (2017) (0)
in an Image Sensor with Integrat ed 2D Edge Detectio n and Noise Filterin g (2014) (0)
Genomic DNA Analysis with the Agilent 2200 TapeStation System and Agilent Genomic DNA ScreenTape Application Note Author (2016) (0)
AHighlyResilientRoutingAlgorithmforFaultTolerantNoC s (2009) (0)
Session details: Special session: electrothermal design of nanoscale integrated circuits (2006) (0)
SoftError Reduction inCombinational LogicUsing GateResizing andFlipflop Selection (2006) (0)
Session details: Session 9D: Interconnect analysis and extraction (2001) (0)
C 20-1 Recryptor : A Reconfigurable In-Memory Cryptographic Cortex-M 0 Processor for IoT (2018) (0)
Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating (2022) (0)
F1: Integrated voltage regulators for SoC and emerging IoT systems (2017) (0)
Rethinking bmicron Circuit Design (1999) (0)
Title RedCooper : Hardware Sensor Enabled Variability Software Testbed for Lifetime Energy Constrained Application Permalink (2013) (0)
Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS The problem with designs that minimize power consumption is that they tend to reduce circuit reliability; improved techniques that jointly optimize both power and reliability are needed. (2007) (0)
A $\boldsymbol{210}\times \boldsymbol{340}\times \boldsymbol{50}\boldsymbol{\mu}\mathbf{m}$ Integrated CMOS System f0 $\mathbf{r}$ Micro-Robots with Energy Harvesting, Sensing, Processing, Communication and Actuation (2022) (0)
Chapter 8 8 POWER OPTIMIZATION USING MULTIPLE SUPPLY VOLTAGES (0)
Keynote Lectures (2008) (0)
Charge-Injection SAR ADC (2022) (0)
Gate Oxide Leakage and Delay Tradeoffs for (2005) (0)
Session details: Crosstalk noise avoidance and power/ground network optimization (2005) (0)
2001 International Workshop on System-Level Interconnect Prediction (SLIP 2001): Foreword (2001) (0)
ISSCC 2016 / SESSION 24 / ULTRA-EFFICIENT COMPUTING : APPLICATION-INSPIRED AND ANALOG-ASSISTED DIGITAL / 24 . 3 24 . 3 A 36 . 8 2 b-TOPS / W Self-Calibrating GPS Accelerator Implemented Using Analog Calculation in 65 nm LP (2018) (0)
Session details: Closing the power gap between ASIC and custom (2005) (0)
Session details: Interconnect optimization (2005) (0)
Session details: Dawn of the 22nm design era - yes we can! (2009) (0)
Session details: Life after CMOS: Imminent or Irrelevant? (2002) (0)
Camera-Ready Paper Submission GUIDE (2004) (0)
Session 20 overview: Digital voltage regulators and low-power techniques (2017) (0)
ISSCC 2017 / SESSION 3 / DIGITAL PROCESSORS / 3 . 7 3 . 7 A 1920 × 1080 30 fps 2 . 3 TOPS / W Stereo-Depth Processor for Robust Autonomous (2018) (0)
Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited Papers (2021) (0)
Reshaping EDA for power (2003) (0)
Spatial Encoding Circuit Tec Reduction of On-Chip Hig (2004) (0)
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS (2016) (0)
Introduction to the Special Section on Circuits and Systems for Energy-Autonomous Microsystems (2013) (0)
Fast Statistical Static Timing Analysis Using Smart (2011) (0)
A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems (2017) (0)
Gate Oxide Leakage Current Analysis and Reduction (2004) (0)
2013 Ieee Custom Integrated Circuits Conference (cicc 2013) Educational Sessions Session 1 – Plenary Session Welcome and Opening Remarks Awards Presentations Keynote Speaker Introduction Session 2 --microsystems for Biomedical and Sensing Applications a Broadband Biosensor Interface Ic for Miniaturi (0)
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation (2020) (0)
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance (2022) (0)
28.6 Bubble Razor: An Architecture-Independent Approach to Timing-Error Detection and Correction (2012) (0)
Session details: Noise-tolerant design and analysis techniques (2004) (0)
A High-Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter (2023) (0)
Hardware Acceleration for Third-Generation FHE and PSI Based on It (2022) (0)
Ultra-low power processor design using subthreshold design techniques : the solution to battery life with voltage scaling (2010) (0)
A NewStatistical MaxOperation forPropagating Skewness inStatistical TimingAnalysis (2006) (0)
FPGA Synthesis and CAD for Reconfigurable Systems (2009) (0)
Circuit Design Advances for Wireless Sensing Applications Many recent designs for miniature, millimeter-scale, long-lifetime, ultralow-power wireless sensors are described with applications in areas such as medical diagnosis, infrastructure monitoring, and environmental sensing. (2010) (0)

This paper list is powered by the following services:

What Schools Are Affiliated With Dennis M. C. Sylvester?

Dennis M. C. Sylvester is affiliated with the following schools:

University of Michigan