Dhiraj K. Pradhan
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Dhiraj K. Pradhanengineering Degrees
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Dhiraj K. Pradhancomputer-science Degrees
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Engineering Computer Science
Dhiraj K. Pradhan's Degrees
- PhD Electrical Engineering University of Southern California
- Masters Electrical Engineering University of Southern California
Why Is Dhiraj K. Pradhan Influential?
(Suggest an Edit or Addition)Dhiraj K. Pradhan's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- A cluster-based approach for routing in dynamic networks (1997) (535)
- Fault-tolerant computer system design (1996) (461)
- Fault-tolerant computing : theory and techniques (1986) (292)
- The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI (1989) (278)
- Fault Injection: A Method for Validating Computer-System Dependability (1995) (250)
- A Fault-Tolerant Communication Architecture for Distributed Systems (1982) (197)
- Consensus With Dual Failure Modes (1991) (189)
- Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization (1994) (173)
- Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci (1992) (163)
- Improving performance of TCP over wireless networks (1997) (141)
- NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances (2004) (130)
- A Cluster-based Approach for Routing in Ad-Hoc Networks (1995) (128)
- Matrix Codes for Reliable and Cost Efficient Memory Chips (2011) (124)
- Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture (1994) (121)
- Error-Correcting Codes and Self-Checking Circuits (1980) (120)
- A Routing-Aware ILS Design Technique (2011) (115)
- A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression (1991) (114)
- Recoverable mobile environment: design and trade-off analysis (1996) (111)
- Design Automation and Test in Europe (DATE) (2014) (97)
- A novel pattern generator for near-perfect fault-coverage (1995) (94)
- A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications (2010) (94)
- A fast and efficient strategy for submesh allocation in mesh-connected parallel computers (1993) (92)
- Fault-Tolerant Multiprocessor Link and Bus Network Architectures (1994) (91)
- A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications (1980) (89)
- Optimal Unidirectional Error Detecting/Correcting Codes (1982) (88)
- A single ended 6T SRAM cell design for ultra-low-voltage applications (2008) (84)
- The Hyper-deBruijn Networks: Scalable Versatile Architecture (1993) (83)
- GLFSR-a new test pattern generator for built-in-self-test (1994) (83)
- Processor- and memory-based checkpoint and rollback recovery (1993) (81)
- Modeling Defect Spatial Distribution (1989) (78)
- Aliasing Probability for Multiple Input Signature Analyzer (1990) (73)
- Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems (1987) (73)
- Robust SRAM Designs and Analysis (2012) (72)
- Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems (1986) (70)
- Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment (1995) (70)
- Error-control coding in computers (1990) (68)
- Roll-forward and rollback recovery: performance-reliability trade-off (1994) (64)
- A Theory of Galois Switching Functions (1978) (64)
- Accelerated dynamic learning for test pattern generation in combinational circuits (1993) (62)
- Location management in distributed mobile environments (1994) (61)
- Test scheduling for network-on-chip with BIST and precedence constraints (2004) (60)
- Job Scheduling in Mesh Multicomputers (1994) (58)
- Matrix-Based Codes for Adjacent Error Correction (2010) (58)
- A new algorithm for order statistic and sorting (1993) (57)
- A BIST Pattern Generator Design for Near-Perfect Fault Coverage (2003) (57)
- Dynamically Restructurable Fault-Tolerant Processor Network Architectures (1985) (55)
- A design for testability scheme to reduce test application time in full scan (1992) (55)
- On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography (2007) (54)
- Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays (1978) (53)
- A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability (1988) (50)
- LOT: Logic optimization with testability - new transformations using recursive learning (1995) (48)
- Modified tree structure for location management in mobile environments (1995) (48)
- Flip-Trees: Fault-Tolerant Graphs with Wide Containers (1988) (46)
- Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets (1980) (44)
- A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines (1980) (44)
- Investigating the impact of NBTI on different power saving cache strategies (2010) (44)
- Reuse-based test access and integrated test scheduling for network-on-chip (2006) (43)
- Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication (2016) (42)
- Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories (2007) (42)
- Recovery in distributed mobile environments (1993) (41)
- Static and adaptive location management in mobile wireless networks (1996) (41)
- Improved decoding algorithm for high reliable reed muller coding (2007) (41)
- Fault-Tolerant Computing (1980) (40)
- Modeling Live and Dead Lines in Cache Memory Systems (1993) (39)
- Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability (1996) (39)
- Two economical directory schemes for large-scale cache coherent multiprocessors (1991) (38)
- Thermal-aware testing of network-on-chip using multiple-frequency clocking (2006) (38)
- Fault-Tolerant Design Strategies for High Reliability and Safety (1993) (37)
- Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay (1988) (34)
- A method to derive compact test sets for path delay faults in combinational circuits (1993) (34)
- Dynamic Testing Strategy for Distributed Systems (1989) (33)
- A Defect Tolerance Scheme for Nanotechnology Circuits (2007) (32)
- Recovery in Mobile Wireless Environment: Design and Trade-off Analysis (1996) (32)
- A novel framework for logic verification in a synthesis environment (1996) (32)
- A Technique to Identify and Substitute Faulty Nodes in Wireless Sensor Networks (2009) (30)
- A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies (2008) (30)
- Reliable network-on-chip based on generalized de Bruijn graph (2007) (29)
- Fault-tolerant computing: theory and techniques; vol. 1 (1986) (29)
- Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation (1995) (29)
- Virtual Checkpoints: Architecture and Performance (1992) (29)
- Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction (2011) (28)
- VERILAT: verification using logic augmentation and transformations (1996) (28)
- Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs (2007) (28)
- Integrated Circuit Manufacturability: The Art of Process and Design Integration (1998) (27)
- Can concurrent checkers help BIST? (1992) (27)
- BCH code based multiple bit error correction in finite field multiplier circuits (2011) (26)
- Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph (2011) (26)
- Single element correction in sorting algorithms with minimum delay overhead (2009) (26)
- A Novel Memristor-Based Hardware Security Primitive (2015) (26)
- SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs (2007) (24)
- Store Address Generator with On-Line Fault-Detection Capability (1977) (24)
- RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework (2012) (24)
- Sequential Network Design Using Extra Inputs for Fault Detection (1983) (24)
- Multiple Upsets Tolerance in SRAM Memory (2007) (23)
- TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's (1988) (23)
- IEEE International On-Line Testing Symposium (2008) (23)
- Integrated Circuit Manufacturability (1998) (22)
- Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis (2014) (22)
- Fault-Tolerant VLSI Architectures Based on de Bruijn Graphs (Galileo in the Mid Nineties) (1989) (22)
- Single ended 6T SRAM with isolated read-port for low-power embedded systems (2009) (22)
- Recoverable Mobile Environments : Design andTrade-o Analysis (1996) (21)
- Single Event Upset Detection and Correction (2007) (21)
- Lecture note in Computer Science (2012) (21)
- Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model (1991) (21)
- An O(m 2 )-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2 m ) a (2009) (20)
- Zero aliasing compression (1990) (20)
- Error-Control Techniques for Logic Processors (1972) (20)
- LPRAM: a novel low-power high-performance RAM design with testability and scalability (2004) (20)
- An O(m2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2m)a (2009) (20)
- Safe System Level Diagnosis (1994) (19)
- Soft Error Mitigation in Switch Modules of SRAM-based FPGAs (2007) (19)
- EBIST: a novel test generator with built-in fault detection capability (2005) (19)
- Fault-tolerant multiprocessor and VLSI-based system communication architectures (1986) (19)
- A multiprocessor network suitable for single-chip VLSI implementation (1984) (19)
- Novel Complementary Resistive Switch Crossbar Memory Write and Read Schemes (2015) (19)
- Wormhole routing in de Bruijn networks and hyper-de Bruijn networks (2003) (18)
- A novel memristor based physically unclonable function (2015) (18)
- Performance of TCP over Wireless Networks (1995) (18)
- Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis (2008) (17)
- Gate-level synthesis for low-power using new transformations (1996) (16)
- Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa (1996) (16)
- Synthesis of initializable asynchronous circuits (1994) (16)
- Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) (2007) (16)
- LOT: Logic Optimization with Testability. New transformations for logic synthesis (1998) (16)
- Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM (2012) (16)
- Fault Tolerant Single Error Correction Encoders (2011) (15)
- Single error correctable bit parallel multipliers over GF(2m) (2009) (15)
- Functional learning: a new approach to learning in digital circuits (1994) (15)
- Improving Memory Reliability Against Soft Errors Using Block Parity (2011) (15)
- Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks (2011) (15)
- On the design of different concurrent EDC schemes for S-Box and GF(p) (2010) (15)
- DeSyRe: On-demand system reliability (2013) (14)
- Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications (2016) (14)
- Performance issues in mobile wireless networks (1996) (14)
- Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection (2008) (14)
- Efficient Location Management in Mobile Wireless Networks (1996) (14)
- A placement strategy for reducing the effects of multiple faults in digital circuits (2014) (14)
- A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead (2010) (13)
- A new class of bit- and byte-error control codes (1992) (13)
- Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation (2016) (13)
- Sequential redundancy identification using recursive learning (1996) (13)
- Matching in memristor based auto-associative memory with application to pattern recognition (2014) (13)
- Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms (2008) (13)
- Fault Tolerant Reversible Finite Field Arithmetic Circuits (2008) (12)
- Forwarding Pointers for Efficient Location Management in Distributed Mobile Environments (1994) (12)
- A novel approach for subcube allocation in hypercube multiprocessors (1992) (12)
- Energy-Efficient Fault-Tolerant Systems (2014) (12)
- Fault-Tolerant Asynchronous Networks (1973) (12)
- A Hamming distance based test pattern generator with improved fault coverage (2005) (12)
- ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management (2010) (11)
- Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement (2008) (11)
- Practical Design Verification (2009) (11)
- Comparative study of CA with phase shifters and GLFSRs (2005) (11)
- The Effect of Program Behavior on Fault Observability (1996) (11)
- On a Class of Fault-Tolerant Multiprocessor Network Architectures (1982) (11)
- Step: (2020) (11)
- Mathematical framework for representing discrete functions as word-level polynomials (2003) (11)
- MODD: a new decision diagram and representation for multiple output binary functions (2004) (11)
- Reed-Muller Like Canonic Forms for Multivalued Functions (1975) (11)
- International Conference on Eco-friendly Computing and Communication Systems (ICECCS ) (2012) (11)
- Single-Event Transient Analysis in High Speed Circuits (2011) (11)
- Providing seamless communication in mobile wireless networks (1996) (10)
- Introduction to Energy-Efficient Fault-Tolerant Systems (2014) (10)
- Multiple Bit Error Detection and Correction in GF Arithmetic Circuits (2010) (10)
- GfXpress: A Technique for Synthesis and Optimization of $\hbox{GF}(2^{m})$ Polynomials (2008) (10)
- A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM (2010) (10)
- Complementary resistive switch based stateful logic operations using material implication (2014) (10)
- Fault tolerant bit parallel finite field multipliers using LDPC codes (2008) (10)
- A low power and robust carbon nanotube 6T SRAM design with metallic tolerance (2014) (9)
- A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation (2007) (9)
- Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors (1993) (9)
- An efficient coordinated checkpointing scheme for multicomputers (1994) (9)
- Correction to 'The De Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI' (1991) (9)
- RTRAM: reconfigurable and testable multi-bit RAM design (1988) (9)
- Fault diagnosis in multi layered De Bruijn based architectures for sensor networks (2010) (9)
- The hyper-deBruijn multiprocessor networks (1991) (9)
- SHIFT REGISTERS DESIGNED FOR ON-LINE FAULT DETECTION (1995) (9)
- Buffer Assignment Algorithms on Data Driven ASICs (2000) (8)
- Exploration of Power Optimal Implementation Technique of 128-PT FFT/IFFT for WPAN using Pseudo-Parallel Datapath Structure (2006) (8)
- Design of Two-Level Fault-Tolerant Networks (1974) (8)
- Asia South Pacific Design Automation Conference (ASPDAC) (2004) (8)
- A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields (2007) (8)
- Single Error Correcting Finite Field Multipliers Over GF(2m) (2008) (8)
- Computational analysis and comparison of reversible gates for design and test of logic circuits (2019) (8)
- The de Bruijn multiprocessor network: a versatile sorting network (1985) (8)
- Easily Testable Implementation for Bit Parallel Multipliers in GF (2m) (2006) (8)
- C-testable bit parallel multipliers over GF(2m) (2008) (8)
- Layout-aware Illinois Scan design for high fault coverage coverage (2010) (7)
- De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs (2008) (7)
- Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits (2017) (7)
- A nano-CMOS process variation induced read failure tolerant SRAM cell (2008) (7)
- Degradable agreement in the presence of Byzantine faults (1993) (7)
- Asynchronous State Assignments with Unateness Properties and Fault-Secure Design (1978) (7)
- Optimal broadcasting in binary de Bruijn networks and hyper-deBruijn networks (1993) (7)
- Roll-Forward Checkpointing Schemes (1994) (7)
- Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis (2013) (7)
- Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems (1990) (7)
- A graph-structural approach for the generalization of data management systems (1977) (7)
- Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems (2009) (7)
- Fault-tolerant multiprocessor and distributed systems: principles (1996) (7)
- Eco-friendly Computing and Communication Systems (2012) (7)
- EBIST: a novel test generator with built-in fault detection capability (2003) (7)
- P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP (2010) (7)
- A hierarchical directory scheme for large-scale cache-coherent multiprocessors (1992) (6)
- Fault-Tolerant Carry-Save Adders (1974) (6)
- Degradable Byzantine agreement (1995) (6)
- A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems (2012) (6)
- 2T2M memristor based TCAM cell for low power applications (2015) (6)
- A soft error robust and power aware memory design (2007) (6)
- Statistical analysis of steady state leakage currents in nano-CMOS devices (2007) (6)
- MODD for CF: a representation for fast evaluation of multiple-output functions (2004) (6)
- Organization and analysis of a gracefully-degrading interleaved memory system (1987) (6)
- Yield optimization in large RAM's with hierarchical redundancy (1991) (6)
- Design of Reversible Finite Field Arithmetic Circuits with Error Detection (2008) (6)
- Recovery in Multicomputers with Finite Error Detection Latency (1994) (6)
- Design Metrics of SRAM Bitcell (2013) (6)
- Software Modification Aided Transient Error Tolerance for Embedded Systems (2013) (6)
- A fast error correction technique for matrix multiplication algorithms (2009) (6)
- Program fault tolerance based on memory access behavior (1991) (6)
- Failure analysis for ultra low power nano-CMOS SRAM under process variations (2008) (6)
- A novel fault diagnosis technique in wireless sensor networks (2010) (5)
- Wideband low-distortion sigma-delta ADC for WLAN (2007) (5)
- Bit-serial generalized median filters (1994) (5)
- Initialization issues in the synthesis of asynchronous circuits (1994) (5)
- Completely Self-Checking Checkers in PLAs (1981) (5)
- A novel scheme to reduce test application time in circuits with full scan (1995) (5)
- Lifetime Reliability Analysis of Complementary Resistive Switches Under Threshold and Doping Interface Speed Variations (2015) (5)
- REACT: An Integrated Tool for the Design of Dependable Computing Systems (1994) (5)
- Design of Fault-Tolerant Computers Using ROM as Basic Building Block. (1980) (5)
- Communication structures in fault-tolerant distributed systems (1993) (5)
- Increasing memory yield in future technologies through innovative design (2009) (5)
- Signal transition graph transformations for initializability (1994) (5)
- Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits (2011) (5)
- Fault detection and repair of DSC arrays through memristor sensing (2015) (5)
- On the Hardware Reduction of z-Datapath of Vectoring CORDIC (2007) (5)
- Design and Analysis of a Gracefully Degrading Interleaved Memory System (1990) (5)
- Reversible Logic: An Introduction (2019) (5)
- A New Algorithm For Order Statistic (1992) (5)
- An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m) (2006) (5)
- Yield optimization of redundant multimegabit RAM's using the center-satellite model (1992) (4)
- The effect of memory-management policies on system reliability (1993) (4)
- Great Lakes Symposium on VLSI (GLSVLSI) (2012) (4)
- Secure Testable S-box Architecture for Cryptographic Hardware Implementation (2010) (4)
- Using memristor state change behavior to identify faults in photovoltaic arrays (2014) (4)
- Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model (1993) (4)
- Design for testability of asynchronous sequential circuits (1993) (4)
- VERILAT: verification using logic augmentation and transformations (2003) (4)
- Fault-Tolerant Asynchronous Networks Using Read-Only Memories (1978) (4)
- On the synthesis of attack tolerant cryptographic hardware (2010) (4)
- Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m) (2008) (4)
- A Galois Field Based Logic Synthesis Approach with Testability (2008) (4)
- A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection (2015) (4)
- Pseudo parallel architecture for AES with error correction (2008) (4)
- A fast and effective DFT for test and diagnosis of power switches in SoCs (2013) (4)
- Logic transformation and coding theory-based frameworks for Boolean satisfiability (2003) (4)
- A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications (2007) (4)
- Design of Single-Bit Fault-Tolerant Reversible Circuits (2021) (4)
- Techniques to Construct (1976) (4)
- Buffer assignment for data driven architectures (1993) (4)
- Simultaneous Scheduling and Binding for Low Gate Leakage Nano-CMOS Datapath Circuit Behavioral Synthesis (2006) (4)
- Software fault tolerance in parallel computing systems: new roll-forward checkpointing schemes for modular redundant systems (1992) (3)
- Multinomial Memristor Model for Simulations and Analysis (2013) (3)
- A single cached copy data coherence scheme for multiprocessor systems (1989) (3)
- EBIST: a novel test generator with built-in fault detection capability (2003) (3)
- Low Power and Robust Binary Tree SRAM Design for Embedded Systems (2013) (3)
- Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m) (2007) (3)
- Tabu Search Based Gate Leakage Optimization using DKCMOS Library in Architecture Synthesis (2009) (3)
- Adaptive Checkpoint Interval Algorithm Considering Task Deadline and Lifetime Reliability for Real-Time System☆ (2015) (3)
- A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM (2010) (3)
- Area Reliability Trade-Off in Improved Reed Muller Coding (2008) (3)
- Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm (2007) (3)
- A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields (2011) (3)
- Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs (2008) (3)
- Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}) (2007) (3)
- Introduction to SRAM (2013) (3)
- Recent advances in verification, equivalence checking & SAT-solvers (2003) (3)
- Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays (2015) (3)
- GASIM: a fast Galois field based simulator for functional model (2005) (3)
- Write scheme for multiple Complementary Resistive Switch (CRS) cells (2014) (3)
- 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07) (2007) (3)
- Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System (2014) (3)
- A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF $(2^{m})$ (2015) (3)
- Functional Yield Modeling (1999) (2)
- 2013 International Symposium on Electronic System Design (2013) (2)
- Subcube Level Time-Sharing in Hypercube Multicomputers (1994) (2)
- Boolean satisfiability and EDA applications (2009) (2)
- Application of Galois Fields to Logic Synthesis (2008) (2)
- Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs (2007) (2)
- Non-square Meshes for Improved Yield in Nanotechnology Circuits (2007) (2)
- Multiple SEU tolerance in LUTs of FPGAs using protected schemes (2008) (2)
- Multinomial based memristor modelling methodology for simulations and analysis (2015) (2)
- Soft-error induced system-failure rate analysis in an SoC (2007) (2)
- IEEE High-Level Design Validation and Test Workshop (2006) (2)
- A Novel Soft Error Tolerant Low Power RAM Architecture (2007) (2)
- VERILAT: Verification by Logic Augmentation and Transformation (2000) (2)
- 5th International Congress on Image and Signal Processing (CISP 2012) (2012) (2)
- An Efficient De Bruijn Graph Based Fault Tolerant Sensor Networks Design (2010) (2)
- Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) (2009) (2)
- Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN (2011) (2)
- Fault-Tolerant Multiprocessor and VLSI-Based Systems. (1987) (2)
- CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs (2007) (2)
- A virtual memory translation mechanism to support checkpoint and rollback recovery (1991) (2)
- Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization (2011) (2)
- Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach (2011) (2)
- Critical Area and Fault Probability Prediction (1999) (2)
- Scalability of binary deBruijn networks (1993) (2)
- The DeSyRe Project: On-Demand System Reliability (2012) (2)
- IEEE International Conference on VLSI Design (VLSID) (2010) (2)
- A Low Power 128-pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks (2006) (2)
- A novel error correction technique for adjacent errors (2009) (2)
- Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity (2013) (2)
- De-Bruijn Graph Based Energy Efficient Routing in Multi-layered Architecture for Wireless Sensor Networks (2009) (2)
- Galois Switching Theory: A Uniform Framework for Multi-Level Verification (2005) (1)
- Fault Tolerant Multiprocessor Systems (2001) (1)
- VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases (2012) (1)
- Dagstuhl Seminar Proceedings on Fault-Tolerant Distributed Algorithms on VLSI Chips (2009) (1)
- Reducing the Dynamic Energy Consumption in the Multi-Layer Memory of Embedded Multimedia Processing Systems ∗ (2007) (1)
- BDG-torus union graph-an efficient algorithmically specialized parallel interconnect (1991) (1)
- Single-Ended SRAM Bitcell Design (2013) (1)
- A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization (2010) (1)
- Reliability aware yield improvement technique for nanotechnology based circuits (2009) (1)
- On the synthesis of bit-parallel Galois field multipliers with on-line SEC and DED (2009) (1)
- Test Generation in Systolic Architecture for Multiplication Over $GF(2 ^{m})$ (2010) (1)
- Evaluation of a new low cost software level fault tolerance technique to cope with soft errors (2010) (1)
- ORGANIZATION AND ANALYSIS OF A GRACEFULLY-DEGRADING (1987) (1)
- Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms (2009) (1)
- Highly Reliable Power Aware Memory Design (2007) (1)
- Submitted to MICPRO Special Issue on European projects on Digital System Design DeSyRe : on-Demand System Reliability (2013) (1)
- 20th IEEE International System On Chip Conference (SOCC’ 2007) (2007) (1)
- Introduction to design techniques for energy harvesting (2010) (1)
- IEEE Latin American Test Workshop (LATW 08) (2008) (1)
- Design Techniques for Synthesis of Fault-Tolerant Asynchronous Networks. (1972) (1)
- Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems (2008) (1)
- Logic Verification in a Synthesis Environment (2001) (1)
- CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs (2007) (1)
- Clustered De Bruijn Based Multi Layered Architectures for Sensor Networks (2010) (1)
- A Novel Frame ork for Logic cation in a Synthesis Environment (1996) (1)
- Guest Editorial Special Section on Design Verification and Validation (2008) (1)
- Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs (2007) (1)
- C-testable S-box implementation for secure advanced encryption standard (2009) (1)
- Providing Seamless Communications in Mobile Wireless Networks (1995) (1)
- Parallel algorithms and architectures report of a workshop (1988) (1)
- A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization (2011) (1)
- A METHOD FOR VM-IDATING COMPUTER-SYSTEM DEPENDABILITY (1995) (1)
- Instantaneous Mean-Time-To-Failure (MTTF) estimation for checkpoint interval computation at run time (2019) (1)
- STEP: a unified design methodology for secure test and IP core protection (2012) (1)
- Proceedings of European Test Symposium (ETS) (2007) (1)
- . " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout (1)
- Further results on m-RMC expansions for m-valued functions (1976) (1)
- Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set (2007) (1)
- Fault Tolerant Nanocomputing (2010) (1)
- LPRAM: a low power DRAM with testability (2004) (1)
- A Galois field-based logic synthesis with testability (2010) (1)
- Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability (2010) (1)
- Fault Tolerant Architectures for Multiprocessors and VLSI-Based Systems (1991) (1)
- SRAM Bitcell Design Using Unidirectional Devices (2013) (0)
- 6th International workshop on performance modeling, evaluation, and optimization of parallel and distributed systems (PMEO-PDS'07) (2007) (0)
- Based Checkpoint andd Rollback Recovery (1993) (0)
- Model checking and equivalence checking (2009) (0)
- Defect Monitoring and Characterization (1999) (0)
- Towards on-demand system reliability: software implemented fault tolerance and testing (2013) (0)
- Low Power and Robust Binary Tree SRAM Design for Embedded Systems: 2013 International Symposium on Electronic System Design (2013) (0)
- 2012 JETTA Reviewers (2013) (0)
- A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms (1995) (0)
- A Software Implemented Fault-Tolerance Layer for Reliable Computing on M assively Parallel Computers and Distributed Computing Systems (2001) (0)
- O ct 2 00 7 On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography (2007) (0)
- Fault-tolerant parallel computing systems: communication structures in fault-tolerant distributed systems (1992) (0)
- NBTI and Its Effect on SRAM (2013) (0)
- Verification in a Synthesis Environment (2007) (0)
- 11th IEEE International Symposium on Quality Electronic Design (ISQED) (2010) (0)
- Testing Solutions for MCM Manufacturing (1999) (0)
- DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM (2010) (0)
- Proceedings of Deisgn, Automation & Test in Europe IEEE International Conference, DATE, 2010, Germany (2010) (0)
- Canonical Graph-based Representations for Verification of Logic and Arithmetic Designs (0)
- 8. Recent Advances in Verification, Equivalence Checking (2003) (0)
- 10th European Conference on Radiation Effects on Components and Systems – RADECS 2009 (2008) (0)
- A Novel Approach for Routing in Ad-Hoc Wireless Local Area Networks (2001) (0)
- [18] S.-Y. Huang, K.-C. Chen, and K.-T. Cheng, rror Correction Based on Verification Techniques, Proc. of Design (0)
- 16th Euromicro Conference on Digital System Design (2013) (0)
- Fault-Tolerance in Distributed and Multiprocessor Real-Time Systems (1993) (0)
- Guest Editorial (2017) (0)
- Selected Articles from the IEEE ISED 2016 Conference (2017) (0)
- ATPG-based Transformations for Random-Pattern Testable Logic Synthesis (2001) (0)
- ATPG for Design Errors-Is It Possible? (2001) (0)
- Yield improvement and power aware low cost memory chips (2008) (0)
- Improved Yield in Nanotechnology Circuits Using Non-square Meshes (2010) (0)
- Eco-friendly Computing and Communication Systems: International Conference, ICECCS 2012, Kochi, India, August 9-11, 2012. Proceedings (2012) (0)
- Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory (2007) (0)
- Sharing patterns and the single cachable coherence scheme for shared memory systems (1990) (0)
- Storage Allocation for Streaming-Based Register File (2011) (0)
- EEE International On-Line Testing Symposium 2007 (IOLTS) (2007) (0)
- Area efficient pseudo-parallel Galois field multipliers (2007) (0)
- Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs (2007) (0)
- To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010 (2010) (0)
- Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits (2012) (0)
- Integrated software tools for the memory management of low-energy embedded signal processing systems (2012) (0)
- Application specific VLSI architectures based on De Bruijn graphs (1990) (0)
- Synthesis of directed multicommodity flow networks (1984) (0)
- Implication-Based Gate-level Synthesis for Low Power (2001) (0)
- Low Cost C-Testable Finite Field Multiplier Architectures (2014) (0)
- A hybrid reliability assessment method and its support of sequential logic modelling (2014) (0)
- Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems (2014) (0)
- A Fault-Diagnosis Technique for Closed Flow Networks. (1980) (0)
- 22nd annual symposium on Integrated circuits and system design SBCCI ‘09 (2009) (0)
- Case studies in fault-tolerant multiprocessor and distributed systems (1996) (0)
- Selected Articles from the IEEE ISED 2014 Conference (2015) (0)
- Design for Test and Manufacturability (1999) (0)
- 7th international workshop on Performance Modeling, Evaluation, and Optimization of Ubiquitous Computing and Networked Systems (PMEO-UCNS'08) (2008) (0)
- Proccedings of Latin American Test Workshop (LATW) (2007) (0)
- Transition faults detection in bit parallel multipliers over GF(2 m ) (2008) (0)
- Proccedings of Latin American Test Workshop (2007) (0)
- 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010 (2010) (0)
- Multiple Event Upsets Aware FPGAs Using Protected Schemes (2008) (0)
- Techniques for the Design of Two-Level Fault-Tolerant Logic Networks. (1973) (0)
- Proceedings of Computing Frontiers 2008 (2008) (0)
- Synthesis Techniques and Analysis Tools for On-Chip Fault-Tolerance (1992) (0)
- Power-Efficient Fault-Tolerant Finite Field Multiplier (2014) (0)
- Practical Design Verification: Decision diagrams for verification (2009) (0)
- A low power and robust carbon nanotube 6T SRAM design with metallic tolerance: Design Automation and Test in Europe (DATE) (2014) (0)
- Tutorial: Recent Advances in Verification, Equivalence Checking & SAT-Solvers Speakers (2005) (0)
- Comment on "Nonplanar VLSI arrays with high fault-tolerance capabilities (1989) (0)
- Technologies through Innovative Design (2009) (0)
- Fault Tolerant High Performance Galois Field Arithmetic Processor (2012) (0)
- Digital CMOS Fault Modeling and Inductive Fault Analysis (1999) (0)
- Statistical Methods of Parametric Yield and Quality Enhancement (1999) (0)
- Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks (2011) (0)
- ALowPower128-pt Implementation ofFFT/IFFT for HighPerformance Wireless Personal AreaNetworks (2006) (0)
- The DeSyRe project: on-Demand System Reliability (invited paper) (2012) (0)
- Recent advances in verification, equivalence checking & SAT solvers (2005) (0)
- An application specific processor for implementing stack filters (1993) (0)
- 2-Port SRAM Bitcell Design (2013) (0)
- SystemVerilog and Vera in a verification flow (2009) (0)
- Critical computer applications will growexplosively inthenext decade, demanding systems thatarereliable andavailable. Faulttolerance provides thetools tobuild suchsystems. (1980) (0)
- High defect tolerant low cost memory chips (2007) (0)
- Logic insertion to speed-up logic verification: a recent development (2001) (0)
- Fault-Tolerant Computing Research (1983) (0)
- Recent advances in verification, equivalence checking & SAT solvers (2003) (0)
- Architectural Fault TolerancePortions of this chapter are based on [5]. (1999) (0)
- BIT-based weighted mean filter (1996) (0)
- Multinomial Memristor model for Simulations and Analysis: 2013 International Symposium on Electronic System Design (2013) (0)
- ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI) (2010) (0)
- DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs (2014) (0)
- Don''t Care Based Implications for Faster and Improved Verification (2001) (0)
- Improving reliability for bit parallel finite field multipliers using Decimal Hamming (2010) (0)
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