Diana Marculescu

Q: What Schools Are Affiliated With Diana Marculescu

Diana Marculescu is affiliated with the following schools: University of Texas at Austin, Politehnica University of Bucharest, University of Southern California, Carnegie Mellon University

Diana Marculescu's AcademicInfluence.com Rankings

Diana Marculescu

Computer Science

#4316

World Rank

#4542

Historical Rank

Database

#7212

World Rank

#7460

Historical Rank

computer-science Degrees

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Computer Science

Diana Marculescu's Degrees

PhD Electrical and Computer Engineering University of Southern California
Masters Electrical and Computer Engineering University of Southern California

Why Is Diana Marculescu Influential?

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According to Wikipedia, Diana Marculescu is the Department Chair and Motorola Regents Chair in Electrical and Computer Engineering #2 at the University of Texas at Austin. She was formerly the David Edward Schramm Professor of Electrical and Computer Engineering at Carnegie Mellon University. She is the first female chair in the department's history.

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Diana Marculescu's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Analysis of dynamic voltage/frequency scaling in chip-multiprocessors (2007) (371)
Electronic textiles: a platform for pervasive computing (2003) (324)
Single-Path NAS: Designing Hardware-Efficient ConvNets in less than 4 Hours (2019) (236)
Power and performance evaluation of globally asynchronous locally synchronous processors (2002) (204)
The EDA challenges in the dark silicon era (2014) (191)
MARS-C: modeling and reduction of soft errors in combinational circuits (2006) (160)
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip (2007) (158)
Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip (2009) (135)
Switching Activity Analysis Considering Spatioternporal Correlations (1994) (132)
Variation-aware dynamic voltage/frequency scaling (2009) (122)
Circuit Reliability Analysis Using Symbolic Techniques (2006) (119)
Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach (2010) (116)
Towards Efficient Model Compression via Learned Global Ranking (2019) (112)
Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors (2013) (110)
Information Theoretic Measures for Power Analysis (1996) (108)
Joint logic restructuring and pin reordering against NBTI-induced performance degradation (2009) (108)
Efficient Power Estimation for Highly Correlated Input Streams (1995) (107)
NeuralPower: Predict and Deploy Energy-Efficient Convolutional Neural Networks (2017) (98)
Regularizing Activation Distribution for Training Binarized Deep Networks (2019) (95)
Architectures for silicon nanoelectronics and beyond (2007) (94)
Variability and energy awareness: a microarchitecture-level perspective (2005) (92)
Probabilistic modeling of dependencies during switching activity analysis (1998) (92)
On the Use of Microarchitecture-Driven Dynamic Voltage Scaling (2000) (90)
Ambient intelligence visions and achievements: linking abstract ideas to real-world concepts (2003) (88)
Variation-adaptive feedback control for networks-on-chip with multiple clock domains (2008) (87)
Distributed reinforcement learning for power limited many-core system performance optimization (2015) (84)
Information theoretic measures of energy consumption at register transfer level (1995) (84)
Speed and voltage selection for GALS systems based on voltage/frequency islands (2005) (83)
Power aware microarchitecture resource scaling (2001) (83)
Power efficiency of voltage scaling in multiple clock multiple voltage cores (2002) (82)
Information theoretic measures for power analysis [logic design] (1996) (81)
Aging-aware timing analysis and optimization considering path sensitization (2011) (78)
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits (2008) (72)
Undergraduate embedded system education at Carnegie Mellon (2005) (72)
Soft Error Rate Analysis for Sequential Circuits (2007) (64)
AdaScale: Towards Real-time Video Object Detection Using Adaptive Scaling (2019) (62)
Characterizing chip-multiprocessor variability-tolerance (2008) (61)
HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks (2017) (61)
Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems (2013) (61)
HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors (2013) (59)
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems (2017) (57)
Challenges and opportunities in electronic textiles modeling and optimization (2002) (57)
Toward a multiple clock/voltage island design style for power-aware processors (2005) (57)
Designing Adaptive Neural Networks for Energy-Constrained Image Classification (2018) (54)
Challenges and Promising Results in NoC Prototyping Using FPGAs (2007) (51)
Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling (2013) (50)
Exploiting Process Variability in Voltage/Frequency Control (2012) (48)
Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods (2009) (47)
Ready to ware (2003) (45)
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: A system-level perspective (2009) (44)
Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems (2017) (44)
Hardware based frequency/voltage control of voltage frequency island systems (2006) (43)
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors (2012) (43)
Profile-driven code execution for low power dissipation (2000) (41)
SVR-NoC: A performance analysis tool for Network-on-Chips using learning-based support vector regression model (2013) (41)
Energy awareness and uncertainty in microarchitecture-level design (2005) (41)
Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems (2018) (41)
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks (2017) (40)
3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs (2009) (40)
Improving the efficiency of power simulators by input vector compaction (1996) (39)
Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms (2016) (38)
Layer-compensated Pruning for Resource-constrained Convolutional Neural Networks (2018) (38)
An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface (2007) (38)
Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty (2016) (38)
Stochastic sequential machine synthesis targeting constrained sequence generation (1996) (36)
Modeling, Analysis, and Self-Management of Electronic Textiles (2003) (36)
Quantized deep neural networks for energy efficient hardware-based inference (2018) (35)
Sequence compaction for power estimation: theory and practice (1999) (35)
A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors (2012) (34)
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures (2016) (34)
A systematic approach to modeling and analysis of transient faults in logic circuits (2009) (33)
Beyond Poisson: Modeling Inter-Arrival Time of Requests in a Datacenter (2014) (33)
Hardware-Aware Machine Learning: Modeling and Optimization (2018) (33)
Soft error rate reduction using redundancy addition and removal (2008) (32)
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits (2013) (32)
A comprehensive and accurate latency model for Network-on-Chip performance analysis (2014) (31)
Custom Feedback control: Enabling truly scalable on-chip power management for MPSoCs (2010) (31)
Sunflower : Full-System, Embedded Microarchitecture Evaluation (2007) (30)
Adaptive models for input data compaction for power simulators (1997) (30)
Power-aware soft error hardening via selective voltage scaling (2008) (29)
Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs (2016) (29)
System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems (2006) (27)
Hierarchical Sequence Compaction For Power Estimation (1997) (27)
Single-Path Mobile AutoML: Efficient ConvNet Design and NAS Hyperparameter Optimization (2019) (26)
Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations (2011) (26)
Understanding the Impact of Label Granularity on CNN-Based Image Classification (2018) (25)
Trace-driven steady-state probability estimation in FSMs with application to power estimation (1998) (24)
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits (2007) (24)
Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis (2017) (24)
Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors (2014) (23)
Procrustes1: Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm (2015) (23)
Theoretical bounds for switching activity analysis in finite-state machines (1998) (23)
Process variability-aware transient fault modeling and analysis (2008) (23)
Guest Editors' Introduction: Power and Complexity Aware Design (2003) (23)
System-level throughput analysis for process variation aware multiple voltage-frequency island designs (2008) (23)
Exploring aging deceleration in FinFET-based multi-core systems (2016) (22)
Microarchitecture-level power management (2002) (22)
Run-time Scaling of Microarchitecture Resources in a Processor for Energy Savings (2000) (22)
Open-Vocabulary Semantic Segmentation with Mask-adapted CLIP (2022) (21)
System level power and performance modeling of GALS point-to-point communication interfaces (2005) (21)
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference (2019) (20)
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits (2011) (19)
TEI-Turbo: temperature effect inversion-aware turbo boost for finfet-based multi-core systems (2015) (19)
A Programming Model and Language Implementation for Concurrent Failure-Prone Hardware (2006) (18)
Process-Driven Variability Analysis of Single and Multiple Voltage–Frequency Island Latency-Constrained Systems (2008) (18)
Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling (2016) (18)
LeGR: Filter Pruning via Learned Global Ranking (2019) (17)
Fault-tolerant techniques for Ambient Intelligent distributed systems (2003) (17)
One Weight Bitwidth to Rule Them All (2020) (17)
System-level process variability analysis and mitigation for 3D MPSoCs (2009) (17)
Dynamic Functional Unit Assignment for Low Power (2003) (17)
System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs (2007) (16)
Power reduction through work reuse (2001) (16)
Application-driven processor design exploration for power-performance trade-off analysis (2001) (16)
Pre-characterization free, efficient power/performance analysis of embedded and general purpose software applications (2003) (15)
A critical analysis of application-adaptive multiple clock processors (2003) (15)
Execution cache-based microarchitecture for power-efficient superscalar processors (2005) (15)
Single-Path NAS: Device-Aware Efficient ConvNet Design (2019) (15)
Dynamic fault-tolerance and metrics for battery powered, failure-prone systems (2003) (15)
Profile-driven code execution for low power dissipation (poster session) (2000) (15)
System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands (2012) (15)
Profit: Priority and Power/Performance Optimization for Many-Core Systems (2018) (15)
Emulation of biological networks in reconfigurable hardware (2011) (15)
Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance (2009) (15)
Sequence Compaction For Probabilistic Analysis Of Finite-state Machines (1997) (15)
Regulatory network analysis acceleration with reconfigurable hardware (2011) (15)
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection (2009) (14)
Power Efficient Processors Using Multiple Supply Voltages (2000) (14)
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs (2018) (14)
Can We Guarantee Performance Requirements under Workload and Process Variations? (2016) (14)
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) (2008) (13)
3D NoC-enabled heterogeneous manycore architectures for accelerating CNN training: Performance and thermal trade-offs (2017) (13)
E-textiles: toward computational clothing (2003) (13)
Information theoretic measures for power analysis : Low power design (1996) (12)
Dynamic behavior of cell signaling networks - Model design and analysis automation (2013) (12)
Application adaptive energy efficient clustered architectures (2004) (12)
DeepNVM++: Cross-Layer Modeling and Optimization Framework of Nonvolatile Memories for Deep Learning (2020) (12)
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms (2012) (12)
Energy efficient MapReduce with VFI-enabled multicore platforms (2015) (12)
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs (2009) (11)
DeepNVM: A Framework for Modeling and Analysis of Non-Volatile Memory Technologies for Deep Learning Applications (2020) (11)
Composite sequence compaction for finite-state machines using block entropy and high-order Markov models (1997) (11)
Formal modeling and reasoning for reliability analysis (2010) (11)
The Architectural Implications of Distributed Reinforcement Learning on CPU-GPU Systems (2020) (10)
Energy bounds for fault-tolerant nanoscale designs (2005) (10)
Energy-efficient VFI-partitioned multicore design using wireless NoC architectures (2014) (10)
Logic Level Power Estimation Considering Spatiotemporal Correlations (2014) (10)
Statistical thermal modeling and optimization considering leakage power variations (2012) (10)
Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits (2013) (10)
ViP: Virtual Pooling for Accelerating CNN-based Image Classification and Object Detection (2019) (10)
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs (2011) (9)
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip (2012) (9)
On the impact of manufacturing process variations on the lifetime of sensor networks (2007) (9)
Tractable Learning and Inference for Large-Scale Probabilistic Boolean Networks (2018) (9)
Hybrid On-Chip Communication Architectures for Heterogeneous Manycore Systems (2018) (9)
System-level mitigation of WID leakage power variability using body-bias islands (2008) (9)
Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models (2015) (9)
Toward an integrated design methodology for fault-tolerant, multiple clock/voltage integrated systems (2004) (8)
The (low) power of less wiring: Enabling energy efficiency in many-core platforms through wireless NoC (2015) (8)
Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore Systems (2017) (8)
SupMAE: Supervised Masked Autoencoders Are Efficient Vision Learners (2022) (7)
Deviation-tolerant computation in concurrent failure-prone hardware (2008) (7)
Design and analysis of a low power VLIW DSP core (2006) (6)
Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions (2013) (6)
“Scaling” the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation (2013) (6)
Clock skew scheduling for soft-error-tolerant sequential circuits (2010) (6)
Process variation aware performance modeling and dynamic power management for multi-core systems (2010) (6)
PareCO: Pareto-aware Channel Optimization for Slimmable Neural Networks (2020) (6)
Increased scalability and power efficiency by using multiple speed pipelines (2005) (6)
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment (2014) (6)
Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond (2020) (6)
Stochastic sequential machine synthesis with application to constrained sequence generation (2000) (6)
QAPPA: Quantization-Aware Power, Performance, and Area Modeling of DNN Accelerators (2022) (5)
A two-level approximate model driven framework for characterizing Multi-Cell Upsets impacts on processors (2016) (5)
Does Q = MC/sup 2/? (On the relationship between Quality in electronic design and the Model of Colloidal Computing) (2002) (5)
Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications (2016) (5)
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores (2003) (5)
Variability-Aware Frequency Scaling in Multi-Clock Processors (2008) (5)
Renofeation: A Simple Transfer Learning Method for Improved Adversarial Robustness (2021) (5)
Mixed-clock issue queue design for energy aware, high-performance cores (2004) (5)
Cross-Layer Design Space Exploration of NVM-based Caches for Deep Learning (2020) (5)
Edge AI: Systems Design and ML for IoT Data Analytics (2020) (4)
Guest Editorial Special Section on Low-Power Electronics and Design (2008) (4)
Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems (2012) (4)
Joslim: Joint Widths and Weights Optimization for Slimmable Neural Networks (2020) (4)
“Where Are You Really From?”: Mitigating Unconscious Bias on Campus (2018) (4)
Thread Progress Equalization: Dynamically Adaptive Power and Performance Optimization of Multi-threaded Applications (2016) (4)
Statistical learning in chip (SLIC) (2015) (4)
Local decisions and triggering mechanisms for adaptive fault-tolerance (2004) (3)
On the impact of manufacturing process variations on the lifetime of sensor networks (2012) (3)
Information-theoretic bounds for switching activity analysis in finite-state machines under temporally correlated inputs (1999) (3)
"Power Consumption Modeling of the TI C6201 and Characterization of its Architectural Complexity", IEEE Micro, Special Issue on Power- and Complexity-Aware Design, (2003) (3)
Dynamic Fault-Tolerance Management in Failure-Prone and Battery-Powered Systems (2008) (3)
Vector Compaction Using Dynamic Markov Models (2007) (3)
Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level (2008) (3)
Reclaiming Performance and Energy Efficiency from Variability (2006) (3)
Vector Compaction Using Dynamic Markov Models (Special Section on VLSI Design and CAD Algorithms) (1997) (3)
SLIC: Statistical learning in chip (2014) (2)
Modeling and Analysis of SER in Combinational Circuits (2010) (2)
Impact of technology scaling on energy aware execution cache-based microarchitectures (2004) (2)
Enhancing precipitation models by capturing multivariate and multiscale climate dynamics (2017) (2)
Modeling Computational, Sensing, and Actuation Surfaces (2018) (2)
FLightNNs (2019) (2)
AVE-CLIP: AudioCLIP-based Multi-window Temporal Transformer for Audio Visual Event Localization (2022) (2)
M3A: Model, MetaModel and Anomaly Detection for Inter-arrivals of Web Searches and Postings (2017) (2)
System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing (2002) (2)
Addressing Process Variations at the Microarchitecture and System Level (2013) (2)
M3A: Model, MetaModel, and Anomaly Detection in Web Searches (2016) (2)
QADAM: Quantization-Aware DNN Accelerator Modeling for Pareto-Optimality (2022) (2)
Width transfer: on the (in)variance of width optimization (2021) (2)
Power reduction through work reuse [superscalar processor microarchitecture] (2001) (2)
Profit: <underline>Pr</underline>iority and P<underline>o</underline>wer/Per<underline>f</underline>ormance Opt<underline>i</underline>miza<underline>t</underline>ion for Many-Core Systems (2018) (1)
Hardware-efficient stereo estimation using a residual-based approach (2013) (1)
Non-stationary effects in trace-driven power analysis (1999) (1)
High-Order Temporal Effects in Finite-State Machine Analysis (2007) (1)
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015 (2015) (1)
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007 (2007) (1)
Fast Synthesis of Power and Temperature Profiles for the Development of Data-Driven Resource Managers (2017) (1)
Multi-domain Processors: Challenges, Design Methods, and Recent Developments (2010) (1)
Efficient on-line module-level wake-up scheduling for high performance multi-module designs (2012) (1)
Efficient Deep Learning Using Non-Volatile Memory Technology (2022) (1)
QUIDAM: A Framework for Quantization-aware DNN Accelerator and Model Co-Exploration (2022) (1)
Priority-Aware Near-Optimal Scheduling for Heterogeneous Multi-Core Systems with Specialized Accelerators (2017) (1)
Putting the "Machine" Back in Machine Learning for Engineering Students (2021) (1)
Programming Crystalline Hardware (2003) (1)
The quest for energy aware computing (2015) (1)
Proceedings of the 9th International Symposium on Networks-on-Chip (2015) (1)
Task Scheduling for Heterogeneous Multicore Systems (2017) (1)
Fundamental Limits on Run-Time Power Management Algorithms for MPSoCs (2013) (1)
Improving the Adversarial Robustness of Transfer Learning via Noisy Feature Distillation (2020) (1)
Editorial to special section on networks on chip (2013) (1)
Low Power Microarchitecture Techniques (2006) (1)
ANT: Adapt Network Across Time for Efficient Video Processing (2022) (1)
. " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout (1)
When Climate Meets Machine Learning: Edge to Cloud ML Energy Efficiency (2021) (1)
On the relationship between Q uality in electronic design and the M odel of C olloidal C omputing ) † (0)
Fine-Grained Long-Range Prediction of Resource Usage in Computer Clusters (2017) (0)
Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions (2011) (0)
Session details: Wireless application drivers for low-power systems (2004) (0)
ELATE at Drexel--Drawing the Pipeline of Talent Upward (2014) (0)
Reliability aware circuit optimization (2011) (0)
PROCEDE DE DETERMINATION IN VIVO DE LA CONCENTRATION D'EAU APPAUVRIE EN DEUTERIUM SUR DES ANIMAUX POUR LA THERAPIE DU CANCER (2005) (0)
IGH-O RDER T EMPORAL E FFECTS (2007) (0)
Differentiable Training for Hardware Efficient LightNNs (2018) (0)
Celebration of the SIGDA CADathalon Winners (2007) (0)
Session details: Emerging ideas in energy management techniques (2005) (0)
2015 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) PROCEEDINGS TABLE OF CONTENTS (2015) (0)
Information Theoretic Measures for Power Analysis 1 (1996) (0)
Implementation of Delay Efficient ALU using Vedic Multiplier with AHL (2016) (0)
Understanding and Using Heterogeneity for High Performance, Energy Efficient Computing (2015) (0)
Editorial: Special Issue on Compact Deep Neural Networks With Industrial Applications (2020) (0)
The Quest for Energy-Aware Computing: Confessions of an Accidental Engineer (2020) (0)
ASP-DAC 2005 Best Papers (2005) (0)
NSF Workshop Report : Architectures for Silicon Nanoelectronics and Beyond 2 (2006) (0)
Adaptive Program Execution for Low Power in Superscalar Processors (1999) (0)
Emulation of Biological Networks in Reconfigurable Hardware Fig. 1. Methodology. Fig. 2. Example of Interaction Map and Logical Model, Translation into Verilog, and Gui Snapshot (0)
Constrained Sequence Generation Using Stochastic Sequential Machines (1996) (0)
CPT-V: A Contrastive Approach to Post-Training Quantization of Vision Transformers (2022) (0)
MobileTL: On-device Transfer Learning with Inverted Residual Blocks (2022) (0)
Play It Cool: Dynamic Shifting Prevents Thermal Throttling (2022) (0)
On the Pareto Efficiency of Quantized CNN (2019) (0)
Heterogeneous Dark Silicon Chip Multi-Processors: Design and Run-Time Management (2017) (0)
Programming unreliable networks of computation (2006) (0)
Session details: Low power software design and sensing (2005) (0)
Reducing Circuit Soft Error Rate ( SER ) : From Combinational to Sequential Circuits (2010) (0)
Summary : Dynamic Thread Mapping for High-Performance , Power-Efficient Heterogeneous Many-core Systems (2014) (0)
Celebration of the SIGDA CADathalon Winners (2007) (0)
Session details: Session 3A: Sequential synthesis (2001) (0)
Computational Approaches for Incorporating Short- and Long-Term Dynamics in Smart Water Networks (2018) (0)
INFORMATION THEORETIC AND PROBABILISTIC MEASURES FOR POWER ANALYSIS OF DIGITAL CIRCUITS (1998) (0)
Session details: Dynamic voltage scaling (2005) (0)
CLIP4VideoCap: Rethinking Clip for Video Captioning with Multiscale Temporal Fusion and Commonsense Knowledge (2023) (0)
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 (2006) (0)
Promoter Characterization via Fluorescence-based Biosensor (2012) (0)
The British system of land use regulation: key features and (unintended) economic consequences (2013) (0)
STEADY-STATE PROBABILITY ESTIMATION IN FSMS CONSIDERING HIGH-ORDER TEMPORAL EFFECTS (2007) (0)
RT-Level Power Analysis Using Information Theoretic Measures (2007) (0)
FPGA Prototype Design of Dynamic Frequency Scaling System for Low Power SoC (2009) (0)
Society & Achievement Awards (2011) (0)
VECTOR COMPACTION USING HIERARCHICAL MARKOV MODELS (2007) (0)
Asynchronous Sequential Computation with Molecular Reactions (2011) (0)
Leveraging Classification Models for River Forecasting (2017) (0)
Application re-mapping for fault-tolerance in ambient intelligent systems (2003) (0)
Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependabilit (2013) (0)
Conversations on Leadership-- Lessons from ELATE at Drexel (2014) (0)
"Where are you really from?": Mitigating Unconscious Bias on Campus (2018) (0)
AB0686 Can Fatigue BE Used as A Unique Disease Activity Marker in Ankylosing Spondylitis Patients? (2014) (0)
\emphNeuralPower: Predict and Deploy Energy-Efficient Convolutional Neural Networks (2017) (0)
Understanding and Using Heterogeneity for High Performance, Energy Efficient Computing: Special Session Extended Abstract (2015) (0)
Flywheel: enabling performance increase and power efficiency by using multiple speed pipelines (2004) (0)
Switching Activity Estimation Based on Conditional Independence (2014) (0)

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