Donatella Sciuto

Q: What Schools Are Affiliated With Donatella Sciuto

Donatella Sciuto is affiliated with the following schools: Polytechnic University of Milan, University of Colorado Boulder, Bocconi University

Donatella Sciuto's AcademicInfluence.com Rankings

Donatella Sciuto

Computer Science

#10590

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#11131

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Computer Engineering

#153

World Rank

#155

Historical Rank

Software Engineering

#302

World Rank

#308

Historical Rank

Machine Learning

#4841

World Rank

#4898

Historical Rank

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Computer Science

Why Is Donatella Sciuto Influential?

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According to Wikipedia, Donatella Sciuto is an Italian electronic engineer and academic administrator, the rector of the Polytechnic University of Milan. Her research involves embedded systems, low-power electronics, and multicore Very Large Scale Integration, with applications including smart buildings.

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Donatella Sciuto's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Factors affecting ERP system adoption: A comparative analysis between SMEs and large companies (2005) (479)
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems (1997) (313)
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems (2010) (158)
Address bus encoding techniques for system-level power optimization (1998) (153)
BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system (2014) (125)
Implicit test generation for behavioral VHDL models (1998) (97)
Power estimation of embedded systems: a hardware/software codesign approach (1998) (84)
Power optimization of system-level address buses based on software profiling (2000) (82)
Source-level execution time estimation of C programs (2001) (75)
Occupancy detection via iBeacon on Android devices for smart building management (2015) (75)
Decision-Theoretic Design Space Exploration of Multiprocessor Platforms (2010) (66)
ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration (2009) (64)
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs (2007) (62)
An instruction-level energy model for embedded VLIW architectures (2002) (59)
Energy estimation and optimization of embedded VLIW processors based on instruction clustering (2002) (58)
Partitioning and exploration strategies in the TOSCA co-design flow (1996) (57)
Power estimation for architectural exploration of HW/SW communication on system-level buses (1999) (57)
Metronome: Operating system level performance management via self-adaptive computing (2012) (55)
Multi-Accuracy Power and Performance Transaction-Level Modeling (2007) (53)
A design framework to efficiently explore energy-delay tradeoffs (2001) (53)
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs (2009) (52)
Instruction-level power estimation for embedded VLIW cores (2000) (50)
Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration (2009) (49)
Efficient pattern matching on GPUs for intrusion detection systems (2010) (48)
Functional verification for SystemC descriptions using constraint solving (2002) (44)
Metrics for design space exploration of heterogeneous multiprocessor embedded systems (2002) (44)
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions (2000) (44)
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems (2002) (44)
ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration (2008) (43)
Functional test generation for behaviorally sequential models (2001) (42)
Symbolic functional vector generation for VHDL specifications (1999) (41)
Low-power state assignment techniques for finite state machines (2000) (40)
A design methodology for dynamic reconfiguration: the Caronte architecture (2005) (40)
Automated real-time atrial fibrillation detection on a wearable wireless sensor platform (2012) (40)
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication (2008) (40)
Placement and Floorplanning in Dynamically Reconfigurable FPGAs (2010) (39)
Affinity-driven system design exploration for heterogeneous multiprocessor SoC (2006) (37)
An instruction-level functionally-based energy estimation model for 32-bits microprocessors (2000) (37)
Co-synthesis and co-simulation of control-dominated embedded systems (1996) (36)
On How to Accelerate Iterative Stencil Loops (2015) (36)
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis (2008) (36)
A direct bitstream manipulation approach for Virtex4-based evolvable systems (2010) (36)
The Impact of Source Code Transformations on Software Power and Energy Consumption (2002) (35)
Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems (2008) (34)
Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems (2008) (34)
Pursuing coherence in software process assessment and improvement (2001) (34)
Dynamic Reconfigurability in Embedded System Design (2007) (33)
An instruction-level functionality-based energy estimation model for 32-bits microprocessors (2000) (33)
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms (2010) (32)
A novel methodology for designing TSC networks based on the parity bit code (1997) (31)
Reliability Properties Assessment at System Level: A Co-Design Framework (2001) (30)
Operating system support for online partial dynamic reconfiguration management (2008) (30)
An adaptive approach for online fault management in many-core architectures (2012) (30)
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications (2002) (30)
Energy estimation for 32-bit microprocessors (2000) (30)
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux (2007) (29)
Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs (2010) (29)
Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms (2011) (28)
A design methodology to implement memory accesses in High-Level Synthesis (2011) (28)
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (2013) (27)
BuildingRules: a trigger-action based system to manage complex commercial buildings (2015) (27)
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications (2008) (26)
Static power modeling of 32-bit microprocessors (2002) (26)
Designing self-checking FPGAs through error detection codes (2002) (26)
A Framework for the Functional Verification of SystemC Models (2005) (26)
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System (2007) (26)
Adaptive and Flexible Smartphone Power Modeling (2013) (26)
ASSURE: RTL Locking Against an Untrusted Foundry (2020) (26)
System-level performance estimation strategy for sw and hw (1998) (25)
A polyhedral model-based framework for dataflow implementation on FPGA devices of Iterative Stencil Loops (2016) (25)
Improving evolutionary exploration to area-time optimization of FPGA designs (2008) (25)
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems (2009) (24)
Low-power data forwarding for VLIW embedded architectures (2002) (24)
A model of soft error effects in generic IP processors (2005) (24)
Fault Models and Injection Strategies in SystemC Specifications (2008) (24)
Operating system support for dynamically reconfigurable SoC architectures (2005) (24)
A multi-level strategy for software power estimation (2000) (23)
Exploiting data forwarding to reduce the power budget of VLIW embedded processors (2001) (23)
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance (2010) (23)
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design (2011) (22)
A methodology for control-dominated systems codesign (1994) (22)
Proceedings of the 49th Annual Design Automation Conference (2012) (22)
ThermOS: System support for dynamic thermal management of chip multi-processors (2013) (22)
An efficient Quantum-Dot Cellular Automata adder (2011) (22)
HW/SW methodologies for synchronization in FPGA multiprocessors (2009) (21)
Exploiting TLM and Object Introspection for System-Level Simulation (2006) (21)
Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems (2013) (21)
An Interrupt Controller for FPGA-based Multiprocessors (2007) (21)
An efficient heuristic approach to solve the unate covering problem [logic minimisation] (2000) (21)
On the Evolution of Hardware Circuits via Reconfigurable Architectures (2012) (20)
A design kit for a fully working shared memory multiprocessor on FPGA (2007) (20)
On How to Design Smart Energy-Efficient Buildings (2014) (20)
On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform (2018) (20)
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture (2008) (20)
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform (2009) (20)
On self-adaptive resource allocation through reinforcement learning (2013) (20)
An Evolutionary Approach to Area-Time Optimization of FPGA designs (2007) (20)
ALADIN: a multilevel testability analyzer for VLSI system design (1994) (20)
Caronte: a complete methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms (2005) (19)
Power exploration for embedded VLIW architectures (2000) (19)
A novel SoC design methodology combining adaptive software and reconfigurable hardware (2007) (19)
How an "evolving" fault model improves the behavioral test generation (1997) (19)
Optimization Strategies in Design Space Exploration (2017) (19)
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA (2006) (19)
A parametric design of a built-in self-test FIFO embedded memory (1996) (18)
A Generation Flow for Self-Reconfiguration Controllers Customization (2008) (18)
Decision-theoretic exploration of multiProcessor platforms (2006) (18)
Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-Based Systems (2016) (18)
Tosca: A Pragmatic Approach To Co-Design Automation Of Control-Dominated Systems (1996) (18)
SystemC Code Generation from UML Models (2003) (17)
Information systems check-up as a leverage for SME development (2002) (17)
A system level approach in designing dual-duplex fault tolerant embedded systems (2002) (16)
HW/SW codesign for embedded telecom systems (1994) (16)
Power estimation of system-level buses for microprocessor-based architectures: a case study (1999) (16)
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms (2014) (16)
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware (2011) (16)
Identification of design errors through functional testing (2003) (15)
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture (2006) (15)
FsmTest: Functional test generation for sequential circuits (1996) (15)
MPower: gain back your android battery life! (2013) (15)
A Self-Reconfigurable Implementation of the JPEG Encoder (2007) (15)
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms (2005) (15)
A Unified Approach to Canonical Form-based Boolean Matching (2007) (15)
Symbolic optimization of interacting controllers based onredundancy identification and removal (2000) (14)
A light-weight Network-on-Chip architecture for dynamically reconfigurable systems (2008) (14)
Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices (2009) (14)
MARC (2017) (14)
Automated Fine-Grained CPU Provisioning for Virtual Machines (2014) (14)
Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems (1995) (14)
Model-based design for wireless body sensor network nodes (2012) (14)
A Transform-Parametric Approach to Boolean Matching (2009) (14)
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures (2014) (14)
Fault Analysis for Networks with Concurrent Error Detection (1998) (13)
Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs (2007) (13)
Danger-system: Exploring new ways to manage occupants safety in smart building (2015) (13)
A Framework for Thermal and Performance Management (2012) (13)
Reliable system specification for self-checking data-paths (2005) (13)
The role of VHDL within the TOSCA hardware/software codesign framework (1994) (13)
Library functions timing characterization for source-level analysis (2003) (13)
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures (2006) (13)
Software and Hardware Techniques for SEU Detection in IP Processors (2008) (13)
Static analysis of transaction-level models (2003) (12)
Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation (2010) (12)
Automatic VHDL restructuring for RTL synthesis optimization and testability improvement (1998) (12)
On the automatic integration of hardware accelerators into FPGA-based embedded systems (2012) (12)
Protocol Conformance Testing by Discriminating UIO Sequences (1991) (12)
Lightweight DMA management mechanisms for multiprocessors on FPGA (2008) (12)
Reducing the complexity of instruction-level power models for VLIW processors (2005) (12)
Self-checking FSMs based on a constant distance state encoding (1995) (12)
An application of genetic algorithms and BDDs to functional testing (2000) (12)
ORTHOGONAL MAPPING: A RECONFIGURATION STRATEGY FOR FAULT TOLERANT VLSI/WSI 2-D ARRAYS+ (1989) (12)
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (2012) (12)
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis (2007) (12)
On-line task management for a reconfigurable cryptographic architecture (2009) (11)
Synthesis for testability of large complexity controllers (1995) (11)
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip (2007) (11)
Testable synthesis of high complex control devices (1995) (11)
Test generation for networks of interacting FSMs using symbolic techniques (1996) (11)
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures (2016) (11)
An integrated design approach for self-checking FPGAs (2003) (11)
Constant testability of combinational cellular tree structures (1992) (11)
Fitness inheritance in evolutionary and multi-objective high-level synthesis (2007) (11)
An approach to functional testing of VLIW architectures (2000) (11)
Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign (2008) (11)
Wirelength driven floorplacement for FPGA-based partial reconfigurable systems (2010) (11)
HERA: Hardware evolution over reconfigurable architectures (2011) (10)
Error simulation based on the SystemC design description language (2002) (10)
An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb (2007) (10)
HERA Project's Holistic Evolutionary Framework (2013) (10)
High-Level Modeling and Exploration of Reconfigurable MPSoCs (2008) (10)
An assembly-level execution-time model for pipelined architectures (2001) (10)
Combined software and hardware techniques for the design of reliable IP processors (2006) (10)
Testing Core-Based Systems: A Symbolic Methodology (1997) (10)
A CMOS fault tolerant architecture for switch-level faults (1994) (10)
Transaction based design: another buzzword or the solution to a design problem? (2003) (10)
Designing networks with error detection properties through the fault-error relation (1997) (10)
Testing and diagnosis ofFFT arrays (1991) (9)
Methods and Algorithms for the Interaction of Residential Smart Buildings with Smart Grids (2015) (9)
A Scalable FPGA Design for Cloud N-Body Simulation (2018) (9)
On Functional Testing of Array Processors (1988) (9)
A Highly Parallel FPGA-based Evolvable Hardware Architecture (2009) (9)
Automatic run-time manager generation for reconfigurable MPSoC architectures (2012) (9)
Specification and Verification of Hardware Systems using the Temporal Logic Language TRIO (1991) (9)
Dynamic modeling of inter-instruction effects for execution time estimation (2001) (9)
Analysis and modeling of energy reducing source code transformations (2004) (9)
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems (2003) (9)
BDD-based testability estimation of VHDL designs (1996) (9)
Implicit test pattern generation constrained to cellular automata embedding (1997) (9)
A multilevel testability assistant for VLSI design (1992) (9)
Transistor stuck-at and delay faults detection in static and dynamic CMOS combinational gates (1992) (9)
Morphone.OS: Context-Awareness in Everyday Life (2013) (8)
High-level power estimation of VLSI systems (1997) (8)
Symbolic optimization of FSM networks based on sequential ATPG techniques (1996) (8)
Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow (2006) (8)
VHDL( VHSIC Hardware Description Language) (1996) (8)
Using speculative computation and parallelizing techniques to improve scheduling of control based designs (2006) (8)
Knowledge-based design space exploration of wireless sensor networks (2012) (8)
State encoding for low power embedded controllers (1998) (8)
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems (2009) (8)
Sequential logic minimization based on functional testability (1995) (8)
An instruction-level methodology for power estimation and optimization of embedded VLIW cores (2002) (8)
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs (2004) (8)
A Two-Level Cosimulation Environment (1997) (8)
An algorithm for functional reconfiguration of fixed-size arrays (1988) (8)
Software methodologies for VHDL code static analysis based on flow graphs (1996) (8)
ICT diffusion and strategic role within Italian SMEs (2000) (8)
Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity (2007) (7)
Floorplacement for Partial Reconfigurable FPGA-Based Systems (2011) (7)
Functional fault models and gate level coverage for sequential architectures (1993) (7)
Evaluation and improvement of fault coverage for verification and validation of protocols (1990) (7)
Functional testing and constrained synthesis of sequential architectures (1993) (7)
Modeling assembly instruction timing in superscalar architectures (2002) (7)
Array partitioning: a methodology for reconfigurability and reconfiguration problems (1988) (7)
A wafer level testability approach based on an improved scan insertion technique (1995) (7)
A Framework for Customizable FPGA-based Image Registration Accelerators (2021) (7)
Energy-Aware FPGA-based Architecture for Wireless Sensor Networks (2012) (7)
A flexible model for evaluating the behavior of hardware/software systems (1997) (7)
Testability alternatives exploration through functional testing (2000) (7)
A Compact Transactional Memory Multiprocessor System on FPGA (2010) (7)
Reliable system co-design: the FIR case study (2004) (7)
Synthesis of multi-level self-checking logic (1994) (7)
A multiprocessor self-reconfigurable JPEG2000 encoder (2009) (7)
On Power and Energy Consumption Modeling for Smart Mobile Devices (2014) (7)
Testing of serial input convolvers (1990) (7)
HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures (2008) (7)
MARC: A Resource Consumption Modeling Service for Self-Aware Autonomous Agents (2017) (7)
Coloring the cloud for predictable performance (2013) (7)
Smart technologies for effective reconfiguration: The FASTER approach (2012) (6)
Clock skew reduction in ASIC logic design: a methodology for clock tree management (1998) (6)
Concurrent error detection at architectural level (1998) (6)
Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach (1998) (6)
Tunneling Trust Into the Blockchain: A Merkle Based Proof System for Structured Documents (2021) (6)
The use of a virtual instruction set for the software synthesis of Hw/Sw embedded systems (1996) (6)
A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model (2022) (6)
Operating system runtime management of partially dynamically reconfigurable embedded systems (2010) (6)
The design of reliable devices for mission-critical applications (2003) (6)
BuildingRules (2018) (6)
Mining interesting patterns from hardware-software codesign data with the learning classifier system XCS (2003) (6)
Design for testability techniques for CMOS combinational gates (1991) (6)
A Technique for Reconfiguring Two Dimensional VLSI Arrays (1987) (6)
MPower: Towards an Adaptive Power Management System for Mobile Devices (2012) (6)
A routing algorithm for harvesting multipipeline arrays with small intercell and pipeline delays (1990) (6)
Redundant faults in TSC networks: definition and removal (1996) (6)
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms (2005) (6)
Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method (1994) (6)
EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing (2015) (6)
Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach (2009) (6)
An open-source design and validation platform for reconfigurable systems (2012) (6)
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs (2013) (6)
Timing and Energy Estimation of C Programs [SPECIAL ISSUE ON POWER AWARE EMBEDDED COMPUTING] (2002) (6)
Timing and Energy Estimation of C Programs [SPECIAL ISSUE ON POWER AWARE EMBEDDED COMPUTING] (2002) (6)
An output/state encoding for self-checking finite state machine (1995) (6)
A VHDL-based approach for power estimation of embedded systems (1997) (6)
Guest Editor's Introduction: Design Tools for Embedded Systems (2000) (6)
Exploring the Role of Inter-Organizational Information Systems within SMEs Aggregations (2005) (6)
Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices (2016) (6)
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis (2008) (6)
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal (1999) (5)
Increase the behavioral fault model accuracy using high-level synthesis information (1999) (5)
A Survey on Recent Hardware and Software-Level Cache Management Techniques (2014) (5)
Functional design for testability of control-dominated architectures (1997) (5)
A behavioral approach to testability analysis for neural networks (1992) (5)
BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems (2020) (5)
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs (2013) (5)
Efficient Hardware Design of Iterative Stencil Loops (2016) (5)
On the Development of a Runtime Reconfigurable Multicore System-on-Chip (2012) (5)
Optimization techniques for multiple output function synthesis (1991) (5)
An approach to a design for testability personal consultant (1990) (5)
Island-Based Adaptable Embedded System Design (2011) (5)
Hw/Sw Co-simulation for fast design-space exploration of multiprocessor embedded systems (2001) (5)
An extended-UIO-based method for protocol conformance testing (2000) (5)
Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design (2008) (5)
A reconfigurable multiprocessor architecture for a reliable face recognition implementation (2010) (5)
Run-time mapping of applications on FPGA-based reconfigurable systems (2010) (5)
A Hierarchical Test Generation Approach for Large Controllers (2000) (5)
cODA: An Open-Source Framework to Easily Design Context-Aware Android Apps (2014) (5)
Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks (1997) (5)
On the Automation of Radiomics-Based Identification and Characterization of NSCLC (2022) (4)
Innovative Structures for CMOS Combinational Gates Synthesis (1994) (4)
The Case for Polymorphic Registers in Dataflow Computing (2018) (4)
HW/SW Co-design of Embedded Systems (1999) (4)
Hw/Sw Codesign of Embedded Systems (4)
ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems (2011) (4)
SystemC and SystemVerilog: Where do They Fit? Where are They Going? (2004) (4)
Sistemi per la gestione dell’informazione (2003) (4)
A real-time application design methodology for MPSoCs (2009) (4)
IS management and success of an Italian fashion shoe company (2003) (4)
A data oriented approach to the design of reconfigurable stream decoders (2005) (4)
Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices (2015) (4)
A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures (2006) (4)
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes (1995) (4)
Constraint generation and placement for automatic layout design of analog integrated circuits (1994) (4)
Fast Software-Level Power Estimation for Design Space Exploration (2000) (4)
Tecnologie di recupero e separazione di terre rare: stato dell’arte e prospettive (2012) (4)
Behavioral test generation for the selection of BIST logic (2002) (4)
Fast system-level exploration of memory architectures driven by energy-delay metrics (2001) (4)
BlueSentinel (2014) (4)
A design flow tailored for self dynamic reconfigurable architecture (2008) (4)
System-level metrics for hardware/software architectural mapping (2004) (4)
Synthesis of dynamic class loading specifications on reconfigurable hardware (2004) (4)
Functional Test Generation: Overview and Proposal of a Hybrid Genetic Approach (2002) (4)
A New Timed Petri Net Model for Hardware Representation (1991) (4)
A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces (2014) (3)
Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology (2006) (3)
Designing Reliable Embedded Systems Based on 32 Bit Microprocessors (2001) (3)
Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues (1993) (3)
Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference] (2007) (3)
An application-centered design flow for self reconfigurable systems implementation (2009) (3)
System Level Hardware-Software Design Exploration with XCS (2004) (3)
A Perspective Vision on Complex Residential Building Management Systems (2014) (3)
Data-path testability analysis based on BDDs (1995) (3)
B2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks (2012) (3)
Testability analysis and behavioral testing of the Hopfield neural paradigm (1998) (3)
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems (2015) (3)
Static Analysis of Transaction-Level Communication Models (2008) (3)
Introduzione ai sistemi informatici (2014) (3)
Testing approaches for flow-graph derived FFT arrays (1990) (3)
A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems (2008) (3)
Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign (2006) (3)
FPGA-Based Embedded System Implementation of Audio Signal Alignment (2019) (3)
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems (2013) (3)
A compared evaluation of classes of reconfiguration strategies for fault tolerance in VLSI array processor architectures (1990) (3)
A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow (2008) (3)
Solving the Coloring Problem to Schedule on Partially Dynamically Reconfigurable Hardware (2005) (3)
Towards a performance-as-a-service cloud (2013) (3)
A performance-aware quality of service-driven scheduler for multicore processors (2014) (3)
Testability of artificial neural networks: A behavioral approach (1995) (3)
A2B: An integrated framework for designing heterogeneous and reconfigurable systems (2013) (3)
An Open-Source, Efficient, and Parameterizable Hardware Implementation of the AES Algorithm (2014) (3)
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms (2013) (3)
Mine with it or sell it (2019) (3)
The Shining embedded system design methodology based on self dynamic reconfigurable architectures (2008) (3)
Aspect Orientation in System Level Design (2005) (3)
A complete testing strategy based on interacting and hierarchical FSMs (1997) (3)
A new switching-level approach to multiple-output functions synthesis (1995) (3)
Run-Time mapping for dynamically-added applications in reconfigurable embedded systems (2009) (3)
Specification of embedded monitors for property checking (2001) (2)
Optimizing the Use of Behavioral Locking for High-Level Synthesis (2021) (2)
A synthesis methodology aimed at improving the quality of TSC devices (1999) (2)
Emulating Transactional Memory on FPGA Multiprocessors (2011) (2)
Behavior of self-checking checkers for 1-out-of-3 codes based on pass-transistor logic (1995) (2)
A TSC evaluation function for combinational circuits (1997) (2)
Interorganisational systems within SMEs aggregations: an exploratory study on information requirements of an industrial district (2011) (2)
Multiple stuck-at faults detection in CMOS combinational gates (1991) (2)
Cycles analysis for testability of WSI sequential architectures (1994) (2)
A scalable decentralized system for fair token distribution and seamless users onboarding (2021) (2)
Testing Core-Based Digital Systems : A Symbolic MethodologyF (1997) (2)
Fault detection and fault tolerance issues at CMOS level through AUED encoding (1996) (2)
Analysis and validation of partially dynamically reconfigurable architecture based on Xilinx FPGAs (2010) (2)
Dedicated hardware accelerators for the epistatic analysis of human genetic data (2011) (2)
High-level design of algorithm-driven architectures: The testability and diagnosability issue (1992) (2)
Reconfigurable Computing and Hardware/Software Codesign (2008) (2)
Systematic AUED codes for self-checking architectures (1998) (2)
Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs (2022) (2)
On the Optimization of Behavioral Logic Locking for High-Level Synthesis (2021) (2)
The use of hierarchical information to test large controllers (1997) (2)
A model for system-level timed analysis and profiling (1998) (2)
An Instruction-Level Energy Model for Embedded (2002) (2)
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs (2012) (2)
OpenMPower: An Open and Accessible Database About Real World Mobile Devices (2015) (2)
GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications (1998) (2)
UML Tailoring for SystemC and ISA Modelling (2005) (2)
A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures (2006) (2)
Designing ad-hoc codes for the realization of fault tolerant CMOS networks (1997) (2)
A design workflow for dynamically reconfigurable multi-FPGA systems (2010) (2)
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System (2003) (2)
Online fault detection in a hardware/software co-design environment: system partitioning (2001) (2)
AN INFRASTRUCTURE TO INSTRUMENT APPLICATIONS AND MEASURE PERFORMANCE IN SELF-ADAPTIVE COMPUTING (2012) (1)
A runtime relocation based workflow for self dynamic reconfigurable systems design (2009) (1)
On-line fault detection in a hardware/software co-design environment. (2001) (1)
Fault analysis in networks with concurrent error detection properties (1998) (1)
Bridging faults modeling and detection in CMOS combinational gates (1992) (1)
Concurrently self-checking structures for Fsms (1993) (1)
Linear testability conditions for two-dimensional arrays (1989) (1)
An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems (2012) (1)
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board (2014) (1)
A methodology for the efficient architectural exploration of energy-delay trade-offs for embedded systems (2003) (1)
Extensions of the hArtes Tool Chain (2012) (1)
Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling (2012) (1)
Fault detection in sequential circuits through functional testing (1993) (1)
HLS Support for Polymorphic Parallel Memories (2018) (1)
A testing approach for WSI globally interconnected parallel architectures (1993) (1)
New CMOS Structures for the Synthesis of Dominamt Functions (1993) (1)
VHDL testability analysis based on fault clustering and implicit fault injection (1998) (1)
ion of VHDL Designs (1996) (1)
Towards WSI testable devices: an improved scan insertion technique (1995) (1)
Acknowledging Value of Personal Information: a Privacy Aware Data Market for Health and Social Research (2020) (1)
The Application of a Process Based Model for IS Check-Up within SMEs (2003) (1)
Power Estimation of Embedded Systems: A Hardware/Software Codesign Approach Manuscript received March 15, 1997; revised July 1, 1997. Publisher Item Identifier S 1063-8210(98)02948-5 (2002) (1)
Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework (2015) (1)
Synthesis of Object Oriented Models on Reconfigurable Hardware (2006) (1)
A Decentralized System for Fair Token Distribution and Seamless Users Onboarding (2020) (1)
Design for Testability Techniques for CMOS (1991) (1)
CMOS reliability improvements through a new fault tolerant technique (1994) (1)
Testability conditions for two-dimensional bilateral arrays (1988) (1)
Ruleset Minimization in Multi-tenant Smart Buildings (2016) (1)
An information system check-up model for small and medium enterprises (1997) (1)
1996 proceedings, Eighth Annual IEEE International Conference on Innovative Systems in Silicon, Austin, Texas, USA (1996) (1)
DGECS: Description Generator for Evolved Circuits Synthesis (2012) (1)
TaBit: A framework for task graph to bitstream generation (2012) (1)
Proceedings of the Conference on Design, Automation and Test in Europe (2008) (1)
The FASTER vision for designing dynamically reconfigurable systems (2013) (1)
Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks (1993) (1)
Application of a testing framework to VHDL descriptions at different abstraction levels (1997) (1)
Smart City: tecnologia e creatività a supporto dell’innovazione (2014) (1)
Automatic Test Pattern Generation with BOA (2006) (1)
Simplifying Sequential Gate-Level Test Generation Through Exploitation of High-Level Information (1996) (0)
Comunità virtuale in aula: uno strumento per creare nuone situazioni formative (2000) (0)
Two-dimensional sequential arrays: design for testability approaches (1994) (0)
Automatic clock tree generation in ASIC designs (1995) (0)
Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures (2010) (0)
Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip (2010) (0)
A reconfiguration algorithm for delay minimization in VLSI/WSI array processors (1987) (0)
In Car Audio (2012) (0)
A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications (2013) (0)
Sequential Logic Minimization Based on Functional (1995) (0)
A privacy preserving identification protocol for smart contracts (2021) (0)
ATTORI E MODELLI DI BUSINESS COME CHIAVE INTERPRETATIVA DEL SETTORE MOBILE (2005) (0)
Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed Systems (2020) (0)
Proceedings -Design, Automation and Test in Europe, DATE : Foreword (2008) (0)
Chairs and Committee Members (1997) (0)
Effective Reconfigurable Design: The FASTER Approach (2014) (0)
A2B: a Framework for the Fast Prototyping of Reconfigurable Systems (2013) (0)
Valutazione economica dell'adozione di una intranet (2000) (0)
Critical Success Factors in SME ERP Project Management: Preliminary Results (2005) (0)
AnEvolutionary Approach toArea-Time Optimization ofFPGA designs (2007) (0)
On the minimal test set for single fault location (1993) (0)
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks (2012) (0)
Plaster: an Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms (2021) (0)
Improving the security and the scalability of the AES algorithm (abstract only) (2014) (0)
Run-time Applications Mapping on Fine-Grained Reconfigurable Embedded Systems (2009) (0)
Detection of bridging faults in DFCMOS combinational gates (1989) (0)
A new DFT methodology for sequential circuits (1995) (0)
Controller and Data-Path Separation by VHDL Restructuring (2000) (0)
Iris (2023) (0)
Mapping Interface Method Calls over OCP Buses (2005) (0)
Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs (2005) (0)
Innovative Structures for CMOS (1994) (0)
A functional approach to delay faults test generation for sequential circuits (1994) (0)
Low-Power Data Forwarding for VLIW (2002) (0)
Session details: High-level power estimation (invited talks) (2000) (0)
Two-Dimensional Sequential Array Architectures: Design for Testability Approaches. (1994) (0)
Virtual Community in the Classroom: An Innovating Tool for Elearning (2004) (0)
An architecture for dynamically reconfigurable real time audio processing systems (2008) (0)
Enabling transparent hardware acceleration on Zynq SoC for scientific computing (2020) (0)
Power Reduction on VLIW Processors through Data Forwarding (2000) (0)
On-Going Research on Address Bus Encoding for Low Power: A Status Report (1997) (0)
IEEE COUNCIL ON ELECTRONIC DESIGN AUTOMATION Officers (2008) (0)
Protecting Hardware IP Cores During High-Level Synthesis (2022) (0)
Informatica e cultura dell'informazione (2013) (0)
SPELL: affecting thermal comfort through perceptive techniques (2014) (0)
Influence of caching and encoding on power dissipation of system-level buses for embedded systems (1999) (0)
Behavioral testing of multilevel system software (1988) (0)
Designers' Forum Committee (2004) (0)
Symbolic Optimization of FSM Networks Based on Redundancy Identification and Removal (2000) (0)
BIST architectures selection based on behavioral testing (2000) (0)
Faber: A Hardware/SoftWare Toolchain for Image Registration (2023) (0)
Deflnizione di un ∞usso per la generazione automatica di architetture riconflgurabili (2006) (0)
The Patricia testability analysis tool (1991) (0)
Affinity-Driven System Design Exploration for (2006) (0)
Metodo per la localizzazione di un dispositivo all'interno di un’area (2017) (0)
DynamicReconfiguration: CoreRelocation viaPartial Bitstreams Filtering withMinimal Overhead (2006) (0)
A Transform-Parametric Approach to (2009) (0)
EMPhASIS: An EMbedded Public Attention Stress Identification System (2020) (0)
DESIGN METHODOLOGIES FOR DYNAMIC RECONFIGURABLE MULTI-FPGA SYSTEMS (2009) (0)
On How to Efficiently Implement Regular Expression Matching on FPGA-Based Systems (2014) (0)
Le soluzioni di approvvigionamento elettronico come una nuova forma di associazione imprenditoriale (2003) (0)
An Approach to Functional Testing of Array Processors (1986) (0)
IEEE COUNCIL ON ELECTRONIC DESIGN AUTOMATION (2010) (0)
TIES: A testability increase expert system for VLSI design (1995) (0)
Testability analysis of pipelined data paths (1996) (0)
A Caronte-oriented approach to a network-based educational infrastructure (2006) (0)
A Protocol for On-Chain Tenders (2022) (0)
An efficient cost-based canonical form for Boolean matching (2007) (0)
K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach (2015) (0)
Designers' Forum : Design, Automation and Test in Europe Conference and Exhibition : Munich, Germany, March 3-7, 2003 (2003) (0)
Message from the Program Chair (2021) (0)
State of the Journal (2016) (0)
A Testing Methodology for VHDL Based High-Level Designs (2008) (0)
The Case for Polymorphic Registers in Dataflow Computing (2017) (0)
Embedded Systems Specification and Modeling (2010) (0)
Simplifying Sequential Gate-Level Test GenerationThrough Exploitation of High-Level (2007) (0)
A reconfiguration algorithm for wafer-scale integration of systolic arrays (1987) (0)
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization (2022) (0)
PARTIALDYNAMICRECONFIGURATION:THE CARONTEAPPROACH. ANEW DEGREEOFFREEDOM INTHE HW/SW CODESIGN. (2006) (0)
Session details: Invited speaker 1 (2010) (0)
Special section on VHDL (1997) (0)
High-level design methods for hardware security: is it the right choice? invited (2022) (0)
The hArtes Tool Chain (2012) (0)
Functional testing and verification of array systems (1989) (0)
Improving design turnaround time via two-levels HW/SW co-simulation (1997) (0)
Session details: Multiprocessor and MPSoC architectures (2008) (0)
From behavioral description to systolic array based architectures (1994) (0)
FIDA: A Framework to Automatically Integrate FPGA Kernels Within Data-Science Applications (2018) (0)
Research meets Education: DRESD, a virtuous circle (2008) (0)
Dataflow computing with Polymorphic Registers (2013) (0)
An adaptive genetic algorithm for dynamically reconfigurable modules allocation (2007) (0)
s for V (1996) (0)
Un Ni Iv Ve Er Rs Si It Tà À D Di I V Ve Er Ro on Na a Programma E Abstract (2007) (0)
Fault detection in TFCMOS/DFCMOS combinational gates (1993) (0)
Valutazione economica dell'adozione di una intranet: Evaluation of intranet acquisition projects (2001) (0)
A novel design framework for the design of reconfigurable systems based on NoCs (2010) (0)
Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS (2018) (0)
An Expert Solution to Functional Testability Analysis of VLSI Circuits (1993) (0)
Comunità virtuale in aula: uno strumento innovativo per l’eLearning (2003) (0)
Reconfigurable Architectures Workshop (RAW) (2015) (0)
Session details: System-level synthesis (2007) (0)
Looking into the Crystal Ball: From Transistors to the Smart Earth (2014) (0)
Alfa Romeo technical office; Architettura della città; Casabella; Enios; House in Milan; Ina-casa programme; Nostra signora della misericordia; Palazzo bianco/Palazzo rosso; Rational architecture; Triennale di Milano; Velasca tower;Zentrum Paul Klee (2013) (0)
Una metodologia per la Pianificazione del Sistema Informativo per le Piccole-Medie Imprese (2005) (0)
Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems (2001) (0)
Sink state analysis in multi-tenant smart buildings (2016) (0)

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