Earl E. Jr. Swartzlander

Earl E. Jr. Swartzlander's AcademicInfluence.com Rankings

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#3884

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#5021

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Electrical Engineering

#929

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#1003

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Earl E. Jr. Swartzlander

Computer Science

#4975

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#5255

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Computer Architecture

#31

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#32

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#2252

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computer-science Degrees

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Engineering
Computer Science

Earl E. Jr. Swartzlander's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University

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Earl E. Jr. Swartzlander's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Computer Arithmetic (1980) (443)
Adder and Multiplier Design in Quantum-Dot Cellular Automata (2009) (381)
Adder Designs and Analyses for Quantum-Dot Cellular Automata (2007) (314)
The Sign/Logarithm Number System (1975) (270)
Introduction to Mathematical Techniques in Pattern Recognition (1973) (263)
A Spanning Tree Carry Lookahead Adder (1992) (193)
Truncated multiplication with correction constant [for DSP] (1993) (185)
DCT Implementation with Distributed Arithmetic (2001) (183)
A First Step Toward Cost Functions for Quantum-Dot Cellular Automata Designs (2014) (169)
A Reduced Complexity Wallace Multiplier Reduction (2010) (168)
FFT Implementation with Fused Floating-Point Operations (2012) (159)
Fundamentals of Pattern Recognition (1973) (152)
Parallel Counters (1973) (146)
A radix 4 delay commutator for fast Fourier transform processor implementation (1984) (142)
A comparison of Dadda and Wallace multiplier delays (2003) (140)
Data-dependent truncation scheme for parallel multipliers (1997) (134)
Hybrid CORDIC Algorithms (1997) (117)
Sign/Logarithm Arithmetic for FFT Implementation (1983) (116)
Hardware Designs for Exactly Rounded Elemantary Functions (1994) (116)
Merged Arithmetic (1980) (101)
Design rules for Quantum-dot Cellular Automata (2011) (100)
Are QCA cryptographic circuits resistant to power analysis attack? (2012) (97)
A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells (2002) (93)
Truncated multiplication with approximate rounding (1999) (91)
High-speed multiplier design using multi-input counter and compressor circuits (1991) (90)
Reduced area multipliers (1993) (90)
Analysis of column compression multipliers (2001) (88)
The Quasi-Serial Multiplier (1973) (86)
QCA Systolic Array Design (2013) (79)
Parallel reduced area multipliers (1995) (78)
Digit-pipelined direct digital frequency synthesis based on differential CORDIC (2006) (77)
A Family of Variable-Precision Interval Arithmetic Processors (2000) (76)
Floating-Point Fused Multiply-Add Architectures (2007) (76)
MAD Gates—Memristor Logic Design Using Driver Circuitry (2017) (76)
A floating-point fused add-subtract unit (2008) (65)
Power-delay characteristics of CMOS multipliers (1997) (65)
A floating-point fused dot-product unit (2008) (60)
Estimating the power consumption of CMOS adders (1993) (59)
Low power parallel multipliers (1996) (59)
Design of Semiconductor QCA Systems (2013) (57)
A scaled DCT architecture with the CORDIC algorithm (2002) (53)
Memristor-based arithmetic (2010) (53)
Inner Product Computers (1978) (52)
Optimizing Arithmetic Elements For Signal Processing (1992) (52)
A unified view of CORDIC processor design (1996) (51)
Priority Tries for IP Address Lookup (2010) (50)
High radix booth multipliers using reduced area adder trees (1994) (49)
Improved Architectures for a Fused Floating-Point Add-Subtract Unit (2012) (47)
Exact rounding of certain elementary functions (1993) (46)
Low Power Arithmetic Components (1996) (44)
Fused floating-point arithmetic for DSP (2008) (44)
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata (2007) (43)
Design and Analysis of Approximate Redundant Binary Multipliers (2019) (42)
Systolic Array Processors (1989) (42)
Improved Architectures for a Floating-Point Fused Dot Product Unit (2013) (42)
Time redundant error correcting adders and multipliers (1992) (41)
Hardware design and arithmetic algorithms for a variable-precision, interval arithmetic coprocessor (1995) (41)
Digital neural network implementation (1992) (41)
CDMA as a multiprocessor interconnect strategy (2001) (41)
Survey of low power techniques for ROMs (1997) (41)
Parallel multipliers for Quantum-Dot Cellular Automata (2009) (41)
Concurrent error detection in ALUs by recomputing with rotated operands (1992) (40)
Systolic Signal Processing Systems (1987) (40)
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations (2010) (39)
A radix-8 wafer scale FFT processor (1992) (36)
Quadruple Time Redundancy Adders (2003) (36)
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms (2000) (36)
16-bit × 16-bit MAC design using fast 5:2 compressors (2000) (35)
Multidimensional systolic arrays for the implementation of discrete Fourier transforms (1999) (35)
A 16-bit/spl times/16-bit MAC design using fast 5:2 compressors (2000) (34)
Modified Booth algorithm for high radix fixed-point multiplication (1993) (34)
Hybrid Han-Carlson adder (2012) (33)
Optimized Memristor-Based Multipliers (2017) (33)
A recursive fast multiplier (1998) (32)
A review of large parallel counter designs (2004) (32)
Bridge Floating-Point Fused Multiply-Add Design (2008) (32)
A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications (1999) (32)
Truncated error correction for flexible approximate multiplication (2012) (32)
Design of quantum-dot cellular automata circuits using cut-set retiming (2011) (31)
A systolic array for 2-D DFT and 2-D DCT (1994) (29)
Arithmetic for Ultra-High-Speed Tomography (1980) (29)
Memcomputing (Memristor + Computing) in Intrinsic SiOx-Based Resistive Switching Memory: Arithmetic Operations for Logic Applications (2017) (28)
A Modified Partial Product Generator for Redundant Binary Multipliers (2016) (28)
Optimizing multipliers for WSI (1993) (28)
Computer arithmetic implemented with QCA: A progress report (2010) (28)
Modified Booth algorithm for high radix multiplication (1992) (28)
Parallel prefix adder design with matrix representation (2005) (28)
Cost-efficient decimal adder design in Quantum-dot cellular automata (2012) (27)
Data Compression Device Based on Modified LZ4 Algorithm (2018) (27)
Merged CORDIC algorithm (1995) (27)
Quadruple time redundancy adders [error correcting adder] (2003) (27)
Modular Design of Conditional Sum Adders Using Quantum-dot Cellular Automata (2006) (26)
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate CORDIC Rotations (2006) (25)
Calculators (1995) (25)
Data wordlength reduction for low-power signal processing software (2004) (25)
Truncated Multiplication with Symmetric Correction (2006) (25)
Software and Hardware Techniques for Accurate, Self-Validating Arithmetic (1996) (25)
Digital optical arithmetic. (1986) (24)
Pipelined Carry Lookahead Adder Design in Quantum-dot Cellular Automata (2005) (24)
Ultra high speed transaxial image reconstruction of the heart, lungs, and circulation via numerical approximation methods and optimized processor architecture. (1979) (24)
A variable-precision interval arithmetic processor (1994) (24)
A Fused Floating-Point Three-Term Adder (2014) (24)
Arithmetic for digital neural networks (1991) (23)
Merged arithmetic for signal processing (1978) (23)
Memristor based adders (2014) (23)
Restoring divider design for quantum-dot cellular automata (2011) (22)
A fast hybrid multiplier combining Booth and Wallace/Dadda algorithms (1992) (22)
Optimal initial approximations for the Newton-Raphson division algorithm (1994) (22)
A fast hybrid carry-lookahead/carry-select adder design (2001) (22)
Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR (2000) (21)
Modified non-restoring division algorithm with improved delay profile and error correction (2011) (21)
Keep it straight: teaching placement how to better handle designs with datapaths (2012) (21)
Bidirectional voltage biased implication operations using SiOx based unipolar memristors (2015) (21)
An analysis of the CORDIC algorithm for direct digital frequency synthesis (2002) (20)
QCA Systolic Matrix Multiplier (2010) (20)
Parallel counter implementation (1992) (20)
A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers (2011) (20)
Multipliers with coplanar crossings for Quantum-Dot Cellular Automata (2010) (19)
Truncated Logarithmic Approximation (2013) (18)
Quantifying academic placer performance on custom designs (2011) (18)
The critically damped CORDIC algorithm for QR decomposition (1996) (17)
Rapid Execution of Fan Beam Image Reconstruction Algorithms Using Efficient Computational Techniques and Special-Purpose Processors (1981) (17)
A reduction scheme to optimize the Wallace multiplier (1998) (17)
High-Speed CORDIC Based on an Overlapped Architecture and a Novel σ-Prediction Method (2000) (17)
Improving the recursive multiplier (2000) (17)
Variable-precision, interval arithmetic coprocessors (1996) (17)
Low-Power Multipliers with Data Wordlength Reduction (2005) (17)
A Goldschmidt Division Method With Faster Than Quadratic Convergence (2011) (17)
Critically damped CORDIC algorithm (1994) (17)
The redundant cell adder (1991) (16)
A new hierarchical packet classification algorithm (2012) (16)
Superpipelined adder designs (1993) (16)
VLSI concurrent error correcting adders and multipliers (1993) (15)
Parallel Montgomery multipliers (2004) (14)
Modified carry skip adder for reducing first block delay (2000) (14)
A Fused Floating-Point Four-Term Dot Product Unit (2016) (14)
Efficient time redundancy for error correcting inner-product units and convolvers (1995) (13)
Digital signal processing with VLSI technology (1983) (13)
An architecture for a radix-4 modular pipeline fast Fourier transform (2003) (13)
Cascaded implementation of an iterative inverse-square-root algorithm, with overflow lookahead (1995) (13)
Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata (2014) (13)
Efficient systolic arrays for FFT algorithms (1995) (13)
A pipelined architecture for the multidimensional DFT (2001) (13)
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications (2018) (13)
Implementation of a high speed multiplier using carry lookahead adders (2013) (13)
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication (1999) (13)
Floating-point implementation of complex multiplication (2009) (12)
Granularly-pipelined CORDIC processors for sine and cosine generators (1996) (12)
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes (2017) (12)
Montgomery modular multiplier design in quantum-dot cellular automata using cut-set retiming (2010) (12)
Design of a Goldschmidt iterative divider for quantum-dot cellular automata (2009) (12)
FREQUENCY-DOMAIN DIGITAL FILTERING WITH VLSI. (1983) (12)
An improved reciprocal approximation algorithm for a Newton Raphson divider (2007) (11)
A modular pipelined implementation of large fast Fourier transforms (2002) (11)
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division (2010) (11)
Merged arithmetic revisited (1997) (11)
High Speed FFT Processor Implementation (1984) (11)
High-speed cosine generator (1994) (10)
Fault tolerant Newton-Raphson dividers using time shared TMR (1996) (10)
Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS (2002) (10)
Simulation of variable precision IEEE floating point using C++ and its application in digital signal processor design (1993) (10)
Modular pipeline fast fourier transform algorithm (2003) (10)
Survey of low power techniques for VLSI design (1996) (10)
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders (2018) (10)
A processor for staggered interval arithmetic (1995) (10)
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation (1992) (9)
Defect tolerance and yield for a wafer scale FFT processor system (1991) (9)
Structure-Aware Placement Techniques for Designs With Datapaths (2013) (9)
Computer design development : principal papers (1976) (9)
A VLSI delay commutator for FFT implementation (1984) (9)
Multidimensional systolic arrays for multidimensional DFTs (1996) (9)
32 bit single cycle nonlinear VLSI cell for the ICA algorithm (2008) (9)
Optimizing adders for WSI (1992) (9)
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology (2006) (9)
Enhanced concurrent error correcting arithmetic unit design using alternating logic (2001) (9)
Switching activity in parallel multipliers (2001) (9)
A software interface and hardware design for variable-precision interval arithmetic (1995) (8)
Error-correcting Goldschmidt dividers using time shared TMR (1998) (8)
The modular pipeline fast Fourier transform algorithm and architecture (2003) (8)
Application of optimized parallel processing digital computers and numerical approximation methods to the ultra high-speed three-dimensional reconstruction of the intact thorax. (1979) (8)
Improved non-restoring division algorithm with dual path calculation (2013) (8)
A review of QCA adders and metrics (2012) (8)
Reliability estimation for time redundant error correcting adders and multipliers (1994) (8)
Design of Radix 4 SRT Dividers for Single Precision DSP in Deep Submicron CMOS Technology (2006) (8)
Computer Arithmetic: Volume III (2015) (8)
Measuring delay time in adders using circuit simulation (1994) (7)
Fast transform processor implementation (1984) (7)
The Negative Two’s Complement Number System (2007) (7)
Application Specific Processors (1997) (7)
High-Speed Computer Arithmetic (2014) (7)
Systolic FFT Processors: Past, Present and Future (2006) (7)
Direct digital frequency synthesis using piece-wise polynomial approximation (2003) (7)
A Routing Algorithm for Signal Processing Networks (1979) (7)
Proceedings of the 1986 International Conference on Parallel Processing/August 19-22, 1986 (1986) (7)
Optimized memristor-based ripple carry adders (2016) (7)
Rapid prototyping fault-tolerant heterogeneous digital signal processing systems (1995) (7)
High performance IP lookup circuit using DDR SDRAM (2008) (7)
Long Residue Checking for Adders (2012) (6)
Parallel Implementation of a Fast Third-Order Volterra Digital Filter (1997) (6)
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine (2007) (6)
A WSI macrocell fault circumvention strategy (1991) (6)
A new pipelined implementation of the fast Fourier transform (2000) (6)
The origins of digital computers: Selected papers, 2nd edition (1977) (6)
Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction (1992) (6)
FFT arrays with built-in error correction (1994) (6)
Recomputing by operand exchanging: a time-redundancy approach for fault-tolerant neural networks (1995) (6)
Speculative Carry Generation With Prefix Adder (2008) (6)
Systolic FFT Processors: A Personal Perspective (2008) (6)
Merged arithmetic for computing wavelet transforms (1998) (6)
VLSI Signal Processing Technology (1997) (6)
Negative Save Sign Extension for Multi-term Adders and Multipliers (2008) (5)
A low-power dual-path floating-point fused add-subtract unit (2012) (5)
Time redundancy for error detecting neural networks (1995) (5)
Three-dimensional FFTs on a digital-signal parallel processor, with no interprocessor communication (1996) (5)
A new asynchronous multiplier using Enable/Disable CMOS Differential Logic (1994) (5)
A rounding method with improved error tolerance for division by convergence (2008) (5)
Truncated Multiplications for the Negative Two's Complement Number System (2006) (5)
Serial-parallel multipliers (1993) (5)
Design of a hybrid prefix adder for nonuniform input arrival times (2002) (5)
Interconnection effects in fast multipliers (1999) (5)
Supersystems: Technology and Architecture (1982) (5)
Variable spanning tree adder (1995) (5)
High-speed CORDIC architecture based on redundant sum formation and overlapped /spl sigma/-selection (1999) (4)
A vector multiply-accumulate architecture for GF(2/sup m/) (2005) (4)
Finite word-length effects of an unified systolic array for 2-D DCT/IDCT (1996) (4)
Arithmetic error analysis of a new reciprocal cell (1992) (4)
Fault-tolerant arithmetic via time-shared TMR (1999) (4)
Image processing address generator chip (1985) (4)
Security Issues in QCA Circuit Design - Power Analysis Attacks (2014) (4)
A cordic arithmetic processor (1998) (4)
Overlapped subarray testing for wafer scale integration (1989) (4)
Computer Arithmetic II: Tutorial (1990) (4)
VLSI, MCM, and WSI: A Design Comparison (1998) (4)
Tunable N-path mismatch shaping for multibit bandpass delta-sigma modulators (2009) (3)
Creating new algorithms and modifying old algorithms to use the variable precision floating point simulator (1994) (3)
Generations of calculators (1995) (3)
The optimum Booth radix for low power integer multipliers (2013) (3)
Memristor based adder circuit design (2016) (3)
ASIC evaluation of ECHO hash function (2009) (3)
A contention-free Radix-2 8k-point fast Fourier transform engine using single port SRAMs (2008) (3)
High-Speed Computerized Tomography (1977) (3)
Realization of a nonlinear digital filter on a DSP array processor (1997) (3)
Time-redundant multiple computation for fault-tolerant digital neural networks (1995) (3)
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture (2007) (3)
Fault-tolerant high-performance CORDIC processors (2000) (3)
A standardized interface control unit for heterogeneous digital signal processors (1994) (3)
Applications of the inner product computer (1973) (3)
An efficient systolic array for the discrete cosine transform based on prime-factor decomposition (1995) (3)
Product select multiplier (1994) (3)
On separable error detection for addition (2013) (3)
Microprogrammed Control for Specialized Processors (1979) (3)
Design and implementation of an interface control unit for rapid prototyping (1993) (3)
Time-shared TMR for fault-tolerant CORDIC processors (2001) (3)
Memristor-Based Addition and Multiplication (2019) (3)
Complexity of merged two's complement multiplier-adders (1999) (3)
Multiply-accumulate architecture for a special class of optimal extension fields (2005) (3)
Memristor based high fan-out logic gates (2016) (3)
Implementation of several RLS nonlinear adaptive algorithms using a commercial floating point digital signal processor (1993) (3)
An architecture for first-order tunable mismatch shaping in oversampled data converters (2010) (2)
Fused floating-point magnitude unit (2013) (2)
Signal processing architectures with VLSI (1980) (2)
Digital Beam Forming Processor (1980) (2)
IMAGE ROTATION CONTROLLER CHIP. (1984) (2)
Sorting networks with built-in error correction (1994) (2)
An asynchronous communication protocol for heterogeneous digital signal processing systems (1994) (2)
Three dimensional system on chip technology (2005) (2)
Fused floating-point two-term sum-of-squares unit (2013) (2)
Power analysis attack of QCA circuits: A case study of the Serpent cipher (2013) (2)
High-speed VLSI implementation of FIR lattice filters (1995) (2)
Absolute and Differential Temperature Monitors Developed for Apollo Space Experiments (1969) (2)
A new scheme for prediction of rotation directions in CORDIC processing (1999) (2)
Optimization of spanning tree carry lookahead adders (1996) (2)
Conference Record - Asilomar Conference on Signals, Systems and Computers: Foreword (2007) (2)
Time-shared modular redundancy for fault-tolerant FFT processors (1999) (2)
Design of 3-D quantum-dot cellular automata adders (2015) (2)
A digit-pipelined direct digital frequency synthesis architecture (2003) (2)
A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters (2010) (2)
Boundary scan in board manufacturing (1994) (2)
Recent results in merged arithmetic (1998) (2)
Priority Area-based Quad-Tree Packet Classification Algorithm and Its Mathematical Framework (2013) (2)
VLSI NETWORKS FOR IMAGE PROCESSING. (1981) (2)
Fast error-correcting Newton-Raphson dividers using time shared TMR (1997) (2)
Parallel GF(2n) multipliers (2017) (2)
Power consumption in fast dividers using time shared TMR (1999) (2)
Dadda Multiplier designs using memristors (2017) (2)
Arithmetic for high speed FFT implementation (1985) (2)
System Design with Memristor Technologies (2018) (2)
Pipelined parallel multiplier implementation (1993) (1)
The case for application specific computing (1991) (1)
Multidimensional systolic arrays and their implementations for discrete fourier transform and discrete cosine transform (1996) (1)
A Power-Scalable Switch-Based Multi-processor FFT (2009) (1)
Low-Cost Duplicate Multiplication (2015) (1)
Memristor Adder Design (2018) (1)
Parametric delay and area models for adders (1993) (1)
Parallel GF(2n) Modular Squarers (2019) (1)
Computer Networking In The Context Of Very Large Scale Integration (VLSI) (1982) (1)
Review of "Introduction to Mathematical Techniques in Pattern Recognition" by Harry C. Andrews (1973) (1)
2 Quantum-dot Cellular Automata (2013) (1)
Memristor-Based Computing (2018) (1)
Improved non-restoring square root algorithm with dual path calculation (2014) (1)
High-speed VLSI implementation of IIR lattice filters (1996) (1)
SOFTWARE AND FIRMWARE FOR DISTRIBUTED SIGNAL PROCESSING. (1980) (1)
Sum-of-products computation based on a weight-sorting algorithm (1999) (1)
Fast multiplier bit-product matrix reduction using bit-ordering and parity generaton (1992) (1)
Compactly merged arithmetic for wavelet transforms (1998) (1)
JavaFlow — A Java dataflow machine (2009) (1)
VLSI Testing: A Decade of Experience (1985) (1)
Proceedings : International Conference on Systolic Arrays, May 25-27, 1988, Sheraton Grand (Harbor Island) Hotel San Diego, California, USA (1988) (1)
A comparison of VLSI, MCM and WSI technologies (1995) (1)
A Bfloat16 Fused Multiplier-Adder (2020) (1)
The future of computing — Arithmetic circuits implemented with memristors (2017) (1)
A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing (2019) (1)
Generic signal processor implementation with VHSIC (1990) (1)
Proceedings : 11th Symposium on Computer Arithmetic, June 29-July 2, 1993, Windsor, Ontario (1993) (1)
An efficient FFT processor for ADSL applications (2001) (1)
Fault simulation with PLDs (1997) (1)
Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters (2010) (1)
Implementation of parallel processors with wafer scale integration (1992) (1)
Microprogrammed control for signal processing (1977) (1)
The fully-serial pipelined multiplier (2011) (1)
Characterization and analysis of errors in circuit test (1995) (1)
Advanced technology for improved signal processor efficiency (1992) (1)
Optimization of spanning tree adders (2006) (1)
Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays (1993) (1)
The Quasi-SerialMultiplier (1973) (0)
Bipolar merged arithmetic for wavelet architectures (1999) (0)
The star multiplier (1995) (0)
Fast multiply-accumulate architecture (2000) (0)
Adder Designs and Analyses for Quantum-Dot (2007) (0)
Implementation of a speculative Ling adder (2009) (0)
High speed recursion-free CORDIC architecture (2010) (0)
A new design for a lookahead carry generator (1994) (0)
Editor's Notice (1991) (0)
The psychological effects of prefrontal leukotomy on schizophrenics. (1952) (0)
WSI implemented with button board interconnection (1990) (0)
Is It Possible to Fairly Compare Interconnection Networks? (1994) (0)
Editorial (1989) (0)
Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication (2015) (0)
Proceedings : 9th Symposium on Computer Arithmetic, September 6-8, 1989 Santa Monica, California, USA (1989) (0)
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning (2022) (0)
Most current applications require both (1984) (0)
Memristor-based adder designs (2018) (0)
RAPID PROTOTYPING TESTBED FOR DISTRIBUTED SIGNAL PROCESSING. (1983) (0)
Hybrid residue generators for increased efficiency (2011) (0)
Constant-delay MSB-first bit-serial adder (2002) (0)
What Types of Research Papers Should We Be Writing? (1994) (0)
Computer Arithmetic for VLSI Signal Processing (2006) (0)
HIGH SPEED SPECTRUM ANALYZER IMPLEMENTATION. (1985) (0)
WSI design of a radix 2 butterfly using macrocell pools (1994) (0)
Modern System Design Using Memristors (2017) (0)
Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow) (2015) (0)
A Routing AlgorithmforSignal ProcessingNetworks (1979) (0)
A VLSI Based Ultra Fast FFT (1985) (0)
Automated synthesis of Dadda multipliers (2004) (0)
Optimization of the final adder stage of fast multipliers (2008) (0)
DISTRIBUTED SIGNAL PROCESSING SYSTEMS. (1981) (0)
Hardware design for end-to-end modular exponentiation in redundant number representation (2005) (0)
Hybrid pipelined and multiplexed FIR filter architecture (2000) (0)
The origins of digital computers: Selected papers: edited by Brian Randell. 464 pages, diagrams, tables, 7×10 in. Springer-Verlag, New York, 1973, Price, $21.60. (approx. £10.80) (1976) (0)
35+ years of computer arithmetic (2004) (0)
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm (2009) (0)
Arithmetic circuit design with memristor based high fan-out logic gates (2016) (0)
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders (2017) (0)
Error modeling in board test (1994) (0)
Charge Coupled Devices in Signal Processing Systems. Volume III. Digital Function Feasibility Demonstration. (1976) (0)
Oscillateur commandé par variation de tension (2007) (0)
Frequency Domain Digital Filtering with VLSI (Very Large Scale Integration) (1983) (0)
Session 8 signal and data processing circuits (1984) (0)
Fixed-Point Computer Arithmetic (2008) (0)
Electronic system of the HCO/ATM spectroheliometer (1970) (0)
A coprocessor for accurate and reliable numerical computations (1995) (0)
Implementation of sort-based counters (2009) (0)
From Concept to Production in Secure Voice Communications (2001) (0)
Editorial (1994) (0)
Accelerated Nuclear Radiation Effects on the Raspberry Pi 3B+ (2022) (0)
Analysis of execution time distributions of a nonlinear digital filter (1997) (0)
Foreword: Advances in Distributed Computing Systems (1985) (0)
HIGH DENSITY BIPOLAR LOGIC TECHNOLOGY. (1977) (0)
Comment on "The Focus Number System" (1979) (0)
The inner product computer (Ph.D. Thesis abstr.) (1973) (0)
The seven wonders of computer arithmetic (2004) (0)
Wafer Scale Integration (2012) (0)
A low-latency serial architecture for the 1-D discrete wavelet transform (1997) (0)
Plenary Address 3: Heterogeneous Parallel Computing (1994) (0)
Absoluteand Differential TemperatureMonitors Developed forApollo Space Experiments (1969) (0)
Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, July 10-12, 2000, Boston, Massachusetts (2000) (0)
Verbal Blast from the Copper Country. (1962) (0)
Fault-tolerant neural architectures: the use of rotated operands (1995) (0)
Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing (2017) (0)
Review of "Fundamentals of Pattern Recognition" by Edward A. Patrick (1973) (0)
International Conference on Wafer Scale Integration, January 3-5, 1989, Fairmont Hotel, San Francisco, California, USA : proceedings (1989) (0)
Rapid prototyping of heterogeneous digital signal processors (1996) (0)
Editorial (1989) (0)
An implementation of level-index arithmetic based on the low latency CORDIC system (1998) (0)
Parallel Hardware Designs for Correctly Rounded Elementary Functions (2013) (0)
A comparative evaluation of adders based on performance and testability (1993) (0)
Editorial Message (1998) (0)
Memristor logic gates (2018) (0)
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications (2017) (0)
Floating-Point Computer Arithmetic (2008) (0)
Editorial (1990) (0)
Efficient sign extension for multiple addition (2003) (0)
Guest Editorial (2003) (0)
Merged scaling multiplication CORDIC algorithm (1997) (0)
Impact of leakage on high performance designs (2005) (0)
35+ years of computer arithmetic: a view from the trenches (2004) (0)
Arithematic for VLSI Signal Processing (2006) (0)
Memristor-based multiplier designs (2018) (0)
Message from Conference Chairs (2011) (0)
STARS: Electronic Calculators: Desktop to Pocket (2013) (0)
Evaluation of complexity and delay of arithmetic circuits as CMOS realizations (2001) (0)
A self-testing method for the pipelined A/D converter (2003) (0)
11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings (1993) (0)
Comprehensive modeling of VLSI test (1996) (0)
Editorial (1989) (0)
Optimal design method for fast carry-skip adders (2001) (0)

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University of Texas at Austin

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