Eby Friedman | Academic Influence

Eby Friedman's AcademicInfluence.com Rankings

Eby Friedman

Computer Science

#3966

World Rank

#4170

Historical Rank

#1395

USA Rank

Machine Learning

#951

World Rank

#965

Historical Rank

#91

USA Rank

Artificial Intelligence

#1170

World Rank

#1191

Historical Rank

#200

USA Rank

Database

#1805

World Rank

#1891

Historical Rank

#452

USA Rank

computer-science Degrees

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Computer Science

Eby Friedman's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science University of California, Berkeley

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Why Is Eby Friedman Influential?

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According to Wikipedia, Eby G. Friedman is an electrical engineer, and Distinguished Professor of Electrical and Computer Engineering at the University of Rochester. Friedman is also a visiting professor at the Technion - Israel Institute of Technology. He is a Senior Fulbright Fellow and a Fellow of the IEEE.

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Eby Friedman's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

TEAM: ThrEshold Adaptive Memristor Model (2013) (609)
MAGIC—Memristor-Aided Logic (2014) (517)
VTEAM: A General Model for Voltage-Controlled Memristors (2015) (487)
Clock distribution networks in synchronous digital integrated circuits (2001) (468)
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies (2014) (465)
3-D Topologies for Networks-on-Chip (2006) (459)
On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions (2005) (433)
System Timing (2000) (384)
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits (1999) (318)
Figures of merit to characterize the importance of on-chip inductance (1998) (290)
Multi-voltage CMOS Circuit Design (2006) (256)
Equivalent Elmore delay for RLC trees (1999) (237)
Repeater design to reduce delay and power in resistive interconnect (1997) (221)
MRL — Memristor Ratioed Logic (2012) (217)
Predictions of CMOS compatible on-chip optical interconnect (2005) (215)
Three-dimensional Integrated Circuit Design (2008) (210)
Power Distribution Networks with On-Chip Decoupling Capacitors (2007) (199)
Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance (2009) (199)
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits: A summary (1999) (191)
Multi-Voltage CMOS Circuit Design: Kursun/Multi-Voltage CMOS Circuit Design (2006) (170)
Dynamically Tuning Processor Resources with Adaptive Processing (2003) (168)
Memristor-based IMPLY logic design procedure (2011) (137)
Low-voltage-swing monolithic dc-dc conversion (2004) (134)
Clock distribution networks in VLSI circuits and systems (1995) (131)
AC-DIMM: associative computing with STT-MRAM (2013) (129)
Memristor-Based Circuit Design for Multilayer Neural Networks (2018) (124)
Domino logic with variable threshold voltage keeper (2003) (123)
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor (2003) (116)
A unified design methodology for CMOS tapered buffers (1995) (115)
Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits (2009) (111)
An RLC interconnect model based on fourier analysis (2005) (108)
Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load (1996) (105)
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits (1997) (104)
Managing static leakage energy in microprocessor functional units (2002) (100)
Optimal clock skew scheduling tolerant to process variations (1996) (98)
Simultaneous switching noise in on-chip CMOS power distribution networks (2002) (98)
High Performance Integrated Circuit Design (2012) (96)
Scaling trends of on-chip power distribution noise (2002) (89)
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints (2006) (88)
Memristive Model for Synaptic Circuits (2017) (88)
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current (2004) (87)
On-Chip Inductance in High Speed Integrated Circuits (2001) (83)
Effective Radii of On-Chip Decoupling Capacitors (2008) (83)
An intra-chip free-space optical interconnect (2010) (80)
Design methodology for global resonant H-tree clock distribution networks (2007) (79)
Logic operations in memory using a memristive Akers array (2014) (79)
Timing Optimization Through Clock Skew Scheduling (2000) (78)
Optimum wire sizing of RLC interconnect with repeaters (2003) (77)
The Desired Memristor for Circuit Designers (2013) (77)
Tools for the computer-aided design of multigigahertz superconducting digital circuits (1999) (75)
Effect of shield insertion on reducing crosstalk noise between coupled interconnects (2004) (72)
A bulk-driven CMOS OTA with 68 dB DC gain (2004) (72)
Synaptic Characteristics of Ag/AgInSbTe/Ta-Based Memristor for Pattern Recognition Applications (2017) (70)
Power Distribution Networks in High Speed Integrated Circuits (2003) (66)
Electrical modeling and characterization of 3-D vias (2008) (65)
Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI (1986) (65)
On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions (2006) (65)
Clock distribution networks for 3-D ictegrated Circuits (2008) (64)
Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis (2007) (64)
Models of memristors for SPICE simulations (2012) (63)
Inductive properties of high-performance power distribution grids (2002) (62)
Exploiting on-chip inductance in high speed clock distribution networks (2000) (62)
Efficiency analysis of a high frequency buck converter for on–chip integration with a dual–V DD microprocessor (2002) (58)
Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation (2013) (58)
Clock Distribution Networks in 3-D Integrated Systems (2011) (57)
Distributed On-Chip Power Delivery (2012) (56)
Clock distribution design in VLSI circuits-An overview (1993) (56)
Repeater insertion in tree structured inductive interconnect (1999) (54)
On-Chip Power Delivery and Management (2016) (54)
Monolithic DC-DC converter analysis and MOSFET gate voltage optimization (2003) (53)
Shielding Methodologies in the Presence of Power/Ground Noise (2009) (50)
Clock skew scheduling for improved reliability via quadratic programming (1999) (49)
Compact Model for Spin–Orbit Magnetic Tunnel Junctions (2016) (49)
Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect (1998) (47)
Low swing dual threshold voltage domino logic (2002) (47)
Clock Feedthrough in CMOS Analog Transmission Gate Switches (2002) (46)
3-D integrated heterogeneous intra-chip free-space optical interconnect. (2012) (46)
Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies (2013) (45)
Incorporating interconnect, register, and clock distribution delays into the retiming process (1997) (45)
Crosstalk modeling for coupled RLC interconnects with application to shield insertion (2006) (45)
Node voltage dependent subthreshold leakage current characteristics of dynamic circuits (2004) (44)
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits (2005) (44)
Retiming With Non-zero Clock Skew, Variable Register, and Interconnect Delay (1994) (43)
Decoupling capacitors for multi-voltage power distribution systems (2006) (42)
A high-speed CMOS op-amp design technique using negative Miller capacitance (2004) (42)
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew (1996) (42)
Power characteristics of inductive interconnect (2004) (41)
A hybrid radix-4/madix-8 low power signed multiplier architecture (1997) (40)
Uniform repeater insertion in RC trees (2000) (39)
Design of tapered buffers with local interconnect capacitance (1995) (39)
Integration of clock skew and register delays into a retiming algorithm (1993) (38)
A clock distribution scheme for large RSFQ circuits (1995) (36)
Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With $RC$ Interconnect (2010) (35)
High input voltage step-down DC-DC converters for integration in a low voltage CMOS process (2004) (35)
Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance (2009) (35)
Functional modeling of RSFQ circuits using Verilog HDL (1997) (35)
A comparison of analog and digital circuit implementations of low power matched filters for use in portable wireless communication terminals (1997) (34)
Interconnect coupling noise in CMOS VLSI circuits (1999) (34)
Design and simulation of Fractional-N PLL frequency synthesizers (2004) (34)
Peak crosstalk noise estimation in CMOS VLSI circuits (1999) (33)
Dynamic and short-circuit power of CMOS gates driving lossless transmission lines (1998) (33)
Interconnect delay minimization through interlayer via placement in 3-D ICs (2005) (33)
High Performance Clock Distribution Networks (1997) (33)
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect (2002) (32)
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections (2000) (32)
Ramp Input Response of RC Tree Networks (1996) (32)
Reduced delay uncertainty in high performance clock distribution networks (2003) (32)
Electrical and optical on-chip interconnects in scaled microprocessors (2005) (32)
A hybrid radix-4/radix-8 low power, high speed multiplier architecture for wide bit widths (1996) (32)
Retiming and clock scheduling for digital circuit optimization (2002) (31)
Crosstalk noise model for shielded interconnects in VLSI-based circuits (2003) (31)
Impedance characteristics of decoupling capacitors in multi-power distribution systems (2004) (29)
Efficient algorithms for fast IR drop analysis exploiting locality (2012) (29)
Pessimism reduction in static timing analysis using interdependent setup and hold times (2006) (28)
Delay and power expressions characterizing a CMOS inverter driving an RLC load (2000) (28)
Thermal analysis of oxide-confined VCSEL arrays (2011) (27)
Efficiency optimization of integrated DC-DC buck converters (2010) (27)
Fast algorithms for IR voltage drop analysis exploiting locality (2011) (27)
An area efficient fully monolithic hybrid voltage regulator (2010) (27)
Adaptive Compact Magnetic Tunnel Junction Model (2014) (26)
Design and low speed testing of a four-bit RSFQ multiplier-accumulator (1997) (26)
A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips (2011) (26)
Impedance characteristics of power distribution grids in nanoscale integrated circuits (2004) (26)
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks (2020) (25)
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits (2016) (25)
Interconnect Routing for Large-Scale RSFQ Circuits (2019) (25)
Sensitivity of interconnect delay to on-chip inductance (2000) (25)
A Cadence-based design environment for single flux quantum circuits (1997) (25)
A low power thyristor-based CMOS programmable delay element (2004) (25)
Distributed power network co-design with on-chip power supplies and decoupling capacitors (2011) (25)
Effective Resistance of a Two Layer Mesh (2011) (24)
Toward a systematic design methodology for large multigigahertz rapid single flux quantum circuits (1999) (24)
CMOS voltage interface circuit for low power systems (2002) (24)
Topological design of clock distribution networks based on non-zero clock skew specifications (1993) (24)
On-chip /spl Delta/I noise in the power distribution networks of high speed CMOS integrated circuits (2000) (24)
Variable threshold voltage keeper for contention reduction in dynamic circuits (2002) (24)
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs (2007) (24)
Stability of Distributed Power Delivery Systems With Multiple Parallel On-Chip LDO Regulators (2016) (24)
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing (2016) (23)
Synchronous performance and reliability improvement in pipelined ASICs (1994) (23)
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation (1994) (23)
On-chip point-of-load voltage regulator for distributed power supplies (2010) (23)
Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits (2009) (23)
Supply and Threshold Voltage Scaling Techniques (2006) (23)
3D heterogeneous sensor system on a chip for defense and security applications (2004) (23)
An area efficient on-chip hybrid voltage regulator (2012) (23)
Power Noise in TSV-Based 3-D Integrated Circuits (2013) (23)
Exponentially tapered H-tree clock distribution networks (2005) (22)
Decoupling technique and crosstalk analysis for coupled RLC interconnects (2004) (22)
A system for critical path analysis based on back annotation and distributed interconnect impedance models (1988) (22)
Repeater insertion to reduce delay and power in RC tree structures (1997) (22)
Memristor-Based Multithreading (2014) (22)
Maximizing performance by retiming and clock skew scheduling (1999) (21)
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty (2001) (21)
Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing (2015) (21)
Repeater insertion in RLC lines for minimum propagation delay (1999) (20)
Buffer sizing for delay uncertainty induced by process variations (2004) (20)
Timing-driven variation-aware nonuniform clock mesh synthesis (2010) (20)
Monotonicity constraints on path delays for efficient retiming with localized clock skew and variable register delay (1995) (20)
Inductive characteristics of power distribution grids in high speed integrated circuits (2002) (19)
Digitally Controlled Pulse Width Modulator for On-Chip Power Management (2014) (19)
Properties of on-chip inductive current loops (2002) (19)
Domino logic with dynamic body biased keeper (2002) (19)
Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating (2015) (19)
Fast algorithms for power grid analysis based on effective resistance (2010) (19)
Lumped versus distributed RC and RLC interconnect impedances (2000) (18)
Memristive Accelerator for Extreme Scale Linear Solvers (2015) (18)
Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages (2005) (18)
Shielding effect of on-chip interconnect inductance (2003) (18)
Circuit synthesis of clock distribution networks based on non-zero clock skew (1994) (18)
Alleviating Thermal Constraints While Maintaining Performance Via Silicon- Based On-chip Optical Interconnects (2007) (18)
Transparent repeaters (2000) (18)
Optimizing Inductive Interconnect for Low Power (2003) (17)
Orthogonal code generator for 3G wireless transceivers (2003) (17)
Low power repeaters driving RC interconnects with delay and bandwidth constraints (2004) (17)
Exponentially tapered H-tree clock distribution networks (2004) (17)
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS (2016) (16)
Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates (2002) (16)
A 0.8 volt high performance OTA using bulk-driven MOSFETs for low power mixed-signal SOCs (2003) (16)
Inductive interconnect width optimization for low power (2003) (16)
2T-1R STT-MRAM memory cells for enhanced on/off current ratio (2014) (16)
Substrate coupling in digital circuits in mixed-signal smart-power systems (2004) (16)
Transactions Briefs A Hybrid Radix-4 / Radix-8 Low Power Signed Multiplier Architecture (1997) (16)
Distributed LDO regulators in a 28 nm power delivery system (2015) (16)
Wire shaping of RLC interconnects (2007) (15)
Hexagonal TSV Bundle Topology for 3-D ICs (2017) (15)
Repeater Insertion in SFQ Interconnect (2020) (15)
Clock frequency and latency in synchronous digital systems (1991) (15)
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits (2012) (15)
Multistate Register Based on Resistive RAM (2015) (15)
Unification of speed, power, area, and reliability in CMOS tapered buffer design (1994) (15)
Inductance/area/resistance tradeoffs in high performance power distribution grids (2002) (15)
Via placement for minimum interconnect delay in three-dimensional (3D) circuits (2006) (14)
Sizing CMOS inverters with Miller Effect and Threshold voltage Variations (2006) (14)
Maximum effective distance of on-chip decoupling capacitors in power distribution grids (2006) (14)
MOS Current Mode Logic Near Threshold Circuits (2014) (14)
Cascode buffer for monolithic voltage conversion operating at high input supply voltages (2005) (14)
Substrate and Ground Noise Interactions in Mixed-Signal Circuits (2006) (14)
Minimizing power dissipation in non-zero skew-based clock distribution networks (1995) (13)
Analog vs. digital: a comparison of circuit implementations for low-power matched filters (1996) (13)
Delay uncertainty due to on-chip simultaneous switching noise in high performance CMOS integrated circuits (2000) (13)
A CMOS Miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough (2002) (13)
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations (1997) (13)
Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage (2004) (13)
Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors (2010) (12)
Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits (2001) (12)
Electrical characteristics of multi-layer power distribution grids (2003) (12)
Toward Increasing the Difficulty of Reverse Engineering of RSFQ Circuits (2020) (12)
The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment (1999) (12)
Decoupling capacitors for power distribution systems with multiple power supply voltages (2004) (12)
Design for Testability of SFQ Circuits (2017) (12)
Thermal conduction path analysis in 3-D ICs (2014) (12)
A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations (1999) (12)
Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors (2018) (11)
Digitally controlled wide range pulse width modulator for on-chip power supplies (2013) (11)
All-Spin-Orbit Switching of Perpendicular Magnetization (2016) (11)
A dynamic reconfigurable clock generator (2001) (11)
Energy efficient adaptive clustering of on-chip power delivery systems (2015) (11)
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors (2017) (11)
On-die decoupling capacitance: frequency domain analysis of activity radius (2006) (11)
Latching characteristics of a CMOS bistable register (1993) (10)
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits (2015) (10)
Single Flux Quantum Integrated Circuit Design (2022) (10)
Performance criteria for evaluating the importance of on-chip inductance (1998) (10)
Fast and accurate simulation of tree structured interconnect (2000) (10)
Optimum wire shaping of an RLC interconnect (2003) (10)
Global Interconnects in VLSI Complexity Single Flux Quantum Systems (2020) (9)
Noise coupling in multi-voltage power distribution systems with decoupling capacitors (2005) (9)
Noise Issues in On-Chip Power Distribution Networks (2011) (9)
Simultaneous clock scheduling and buffered clock tree synthesis (1997) (9)
Forward body biased keeper for enhanced noise immunity in domino logic circuits (2004) (9)
Low Power Clock Network Design (2011) (9)
Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling (2009) (9)
Noise immunity of digital circuits in mixed-signal smart power systems (1999) (9)
Incorporating circuit-level information into the retiming process (2000) (9)
Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs (2008) (9)
Multi-Layer Interdigitated Power Distribution Networks (2011) (9)
Optimum wire tapering for minimum power dissipation in RLC interconnects (2006) (9)
Effective capacitance of RLC loads for estimating short-circuit power (2006) (9)
Resource Based Optimization for Simultaneous Shield and Repeater Insertion (2010) (9)
Splitter Trees in Single Flux Quantum Circuits (2021) (9)
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators (2008) (9)
On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits (2005) (9)
On the Extraction of On-Chip Inductance (2003) (9)
Noise Coupling Models in Heterogeneous 3-D ICs (2016) (9)
A high precision CMOS current mirror/divider (1999) (9)
Low power flexible Rake receivers for WCDMA (2004) (9)
Estimation of transient voltage fluctuations in the CMOS-based power distribution networks (2001) (8)
Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits (2002) (8)
Power Network Optimization Based on Link Breaking Methodology (2013) (8)
Pipelining of high performance synchronous digital systems (1991) (8)
Compact substrate models for efficient noise coupling and signal isolation analysis (2010) (8)
Synthesis of clock tree topologies to implement nonzero clock skew schedule (1999) (8)
Inductance effects in RLC trees (1999) (8)
Chip-scale demonstration of 3D integrated intrachip free-space optical interconnect (2012) (8)
Exploiting hysteresis in a CMOS buffer (1999) (8)
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime (2015) (8)
The effects of channel width tapering on the power dissipation of serially connected MOSFETs (1993) (8)
On-chip DC-DC converters for three-dimensional ICs (2009) (8)
Asynchronous Dynamic Single-Flux Quantum Majority Gates (2020) (8)
Design Methodology for Global Resonant ${\rm H}$-Tree Clock Distribution Networks (2006) (8)
Globally Asynchronous, Locally Synchronous Clocking and Shared Interconnect for Large-Scale SFQ Systems (2019) (8)
Inductance Model of Interdigitated Power and Ground Distribution Networks (2009) (7)
Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system (2000) (7)
Transient analysis of a CMOS inverter driving resistive interconnect (2000) (7)
Analog Design Issues in Digital VLSI Circuits and Systems (1997) (7)
Adaptive power gating of 32-bit Kogge Stone adder (2016) (7)
Timing-driven via placement heuristics for three-dimensional ICs (2008) (7)
Exploiting on-chip inductance in high speed clock distribution networks (2000) (7)
Timing optimization in logic with interconnect (2008) (7)
Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems (2018) (7)
Low power repeaters driving RLC interconnects with delay and bandwidth constraints (2005) (7)
Heterogeneous 3-D circuits: Integrating free-space optics with CMOS (2016) (7)
Variation of inductance with frequency in high performance power distribution grids [ICs] (2002) (7)
Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs (2017) (7)
Scaling trends of power noise in 3-D ICs (2015) (7)
On-Chip Interconnect: The Past, Present, and Future (2006) (7)
Mutual inductance modeling for multiple RLC interconnects with application to shield insertion (2004) (7)
Sensitivity evaluation of global resonant H-tree clock distribution networks (2006) (7)
A high speed CMOS buffer for driving large capacitive loads in digital ASICs (1998) (7)
Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction (2009) (7)
A Fourier series-based RLC interconnect model for periodic signals (2005) (7)
Report for the NSF Workshop on Cross ‐ layer Power Optimization and Management (2012) (7)
Arithmetic encoding for memristive multi-bit storage (2012) (7)
Monolithic voltage conversion in low-voltage CMOS technologies (2005) (6)
Clock distribution architectures for 3-D SOI integrated circuits (2008) (6)
Automated Synthesis of Skew-Based Clock Distribution Networks (1998) (6)
Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints (2010) (6)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors (2018) (6)
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits (2011) (6)
Partitioning RSFQ Circuits for Current Recycling (2021) (6)
Recent progress on 3-D integrated intra-chip free-space optical interconnect (2012) (6)
Noise aware decoupling capacitors for multi-voltage power distribution systems (2005) (6)
Globally integrated power and clock distribution network (2010) (6)
Methodology for multi-layer interdigitated power and ground network design (2010) (6)
Tapered transmission gate chains for improved carry propagation [arithmetic logic circuits] (2002) (6)
Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis (2008) (6)
Frequency Characteristics of High Speed Power Distribution Grids (2003) (6)
Pseudo-random clocking to enhance signal integrity (2008) (6)
Dynamic power management with power network-on-chip (2014) (6)
Speed and Noise Immunity Enhanced Low Power Dynamic Circuits (2003) (5)
Data bus swizzling in TSV-based three-dimensional integrated circuits (2013) (5)
An Intra-Chip Free-Space Optical Interconnect: Extended Technical Report (2010) (5)
Peak noise prediction in loosely coupled interconnect [VLSI circuits] (1999) (5)
An automated, low power, high speed complementary PLA design system for VLSI applications (1984) (5)
On-chip test circuit for measuring substrate and line-to-line coupling noise (2006) (5)
Assembly Process and Electrical Properties of Top-Transferred Graphene on Carbon Nanotubes for Carbon-Based 3-D Interconnects (2020) (5)
Field driven STT-MRAM cell for reduced switching latency and energy (2014) (5)
A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications (2004) (5)
Power grid analysis based on a macro circuit model (2010) (5)
Design methodology to distribute on-chip power in next generation integrated circuits (2012) (5)
Power Noise and Near-Field EMI of High-Current System-in-Package With VR Top and Bottom Placements (2019) (5)
Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays (2018) (5)
Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators (2019) (5)
Efficient implementation of a complex ±1 multiplier (2002) (5)
STT-MRAM memory cells with enhanced on/off ratio (2012) (4)
Three-Dimensional Integrated Circuit Design, 2nd Edition (2017) (4)
Topological synthesis of clock trees for VLSI-based DSP systems (1997) (4)
Methodology for placing localized guard rings to reduce substrate noise in mixed-signal circuits (2008) (4)
MTJ Magnetization Switching Mechanisms for IoT Applications (2018) (4)
Minimizing sensitivity to delay variations in high-performance synchronous circuits (1999) (4)
Power Delivery Exploration Methodology Based on Constrained Optimization (2020) (4)
TRADE-OFFS IN CMOS VLSI CIRCUITS (2002) (4)
Flux Mitigation in Wide Superconductive Striplines (2022) (4)
Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology (2009) (4)
Current profile of a microcontroller to determine electromagnetic emissions (2013) (4)
Surface Inductance of Superconductive Striplines (2022) (4)
Clock tree layout design for reduced delay uncertainty (2004) (4)
Linear and Switch-Mode Conversion in 3-D Circuits (2011) (4)
Bias Distribution in ERSFQ VLSI Circuits (2020) (4)
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks (2013) (4)
Performance characteristics of 14 nm near threshold MCML circuits (2013) (4)
Power Grid Noise in TSV-Based 3-D Integrated Systems (2011) (4)
The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections (2002) (4)
Sleep Switch Dual Threshold Voltage Domino Logic (2006) (4)
Clock distribution models of 3-D integrated systems (2011) (4)
Placement of substrate contacts to alleviate substrate noise in epi and non-epi technologies (2000) (4)
Synthesizing distributed buffer clock trees for high performance ASICs (1994) (4)
Input port reduction for efficient substrate extraction in large scale IC’s (2008) (4)
Transient power in CMOS gates driving LC transmission lines (1998) (4)
On the write energy of non-volatile resistive crossbar arrays with selectors (2018) (4)
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation (2012) (4)
A universal CMOS voltage interface circuit (1999) (4)
Demonstration of Speed and Power Enhancements through Application of Non-Zero Clock Skew Scheduling (2000) (3)
Signal waveform characterization in RLC trees (1999) (3)
Resistive Power in CMOS Circuits (2003) (3)
Substrate Coupling and Interconnect Noise in Mixed-Signal and High Speed Digital ICs (1999) (3)
QuCTS—Single-Flux Quantum Clock Tree Synthesis (2022) (3)
Superconductive Logic Using 2ϕ—Josephson Junctions With Half Flux Quantum Pulses (2022) (3)
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates (2008) (3)
Contact merging algorithm for efficient substrate noise analysis in large scale circuits (2009) (3)
Low power digital CMOS buffer systems for driving highly capacitive interconnect lines (2000) (3)
Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling (2001) (3)
Power efficient tree-based crosslinks for skew reduction (2009) (3)
Multi-Bit CNT TSV for 3-D ICs (2020) (3)
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling (2002) (3)
Design Methodologies for on-Chip Inductive Interconnect (2005) (3)
Equivalent rise time for resonance in power/ground noise estimation (2008) (3)
Power network-on-chip for scalable power delivery (2014) (3)
Peak Noise Prediction in Loosely Coupled Interconnect (1999) (3)
Pipelining and Clocking of High Performance Synchronous Digital Systems (1994) (3)
Distributed power delivery for energy efficient and low power systems (2012) (3)
Introduction to the special issue on low power wireless communications (1997) (2)
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696] (2010) (2)
CHOICE OF THE OPTIMUM TIMING SCHEME FOR RSFQ DIGITAL CIRCUITS (2005) (2)
Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems (2020) (2)
On the stability of distributed on-chip low dropout regulators (2017) (2)
Optimizing RLC tree delays by employing repeater insertion (1999) (2)
Physical Design Issues in 3-D Integrated Technologies (2008) (2)
Physical Analysis of NoC Topologies for 3-D Integrated Systems (2011) (2)
Cryogenic Dynamic Logic (2020) (2)
Low Power CMOS Bi-Directional Voltage Converter (2001) (2)
Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies (2017) (2)
Transient IR voltage drops in CMOS-based power distribution networks (2000) (2)
Versatile Framework for Power Delivery Exploration (2018) (2)
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors (2016) (2)
Thermal Modeling and Analysis (2017) (2)
Uniform Repeater Insertion in Trees (2000) (2)
Power dissipated by CMOS gates driving lossless transmission lines (1998) (2)
Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment (2005) (2)
Hybrid energy harvesting in 3-D IC IoT devices (2017) (2)
Distributed Power Delivery with Ultra-Small LDO Regulators (2016) (2)
3-D Circuit Architectures (2009) (2)
Electrical and Thermal Models of CNT TSV and Graphite Interface (2018) (2)
3-D floorplanning algorithm to minimize thermal interactions (2015) (2)
Distributed sinusoidal resonant converter with high step-down ratio (2017) (2)
Two-phase Clocking for Medium to Large RSFQ Circuits (2005) (2)
Transient simulation of on-chip transmission lines via exact pole extraction (2008) (2)
Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity (2001) (2)
Challenges in High Current On-Chip Voltage Stacked Systems (2020) (2)
Spintronic/CMOS-Based Thermal Sensors (2020) (2)
Closed-Form Expressions for Fast IR Drop Analysis (2016) (2)
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators (2020) (2)
A circuit technique for accurately measuring coupling capacitance (2002) (2)
Quasi-Resonant Interconnects: A Low Power Design Methodology (2007) (2)
A design methodology for low power, reduced area, reliable CMOS buffers (1994) (2)
Line width optimization for interdigitated power/ground networks (2010) (2)
Substrate Noise Reduction Based On Noise Aware Cell Design (2007) (2)
Transformations of signed-binary number representations for efficient VLSI arithmetic (2003) (2)
Clock Distribution In Synchronous Systems (1999) (2)
Design Automation of Superconductive Digital Circuits: A review (2021) (2)
Memristive multistate pipeline register (2014) (2)
Associative Processor Thermally Enables 3-D Integration of Processing and Memory (2013) (2)
Manufacturing Technologies for Three-Dimensional Integrated Circuits (2017) (2)
Basic Transmission Line Theory (2001) (2)
An RLC Interconnect Model Based on (2005) (2)
On-Chip Power Grids with Multiple Supply Voltages (2016) (2)
A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise (2001) (2)
Timing and power models for CMOS repeaters driving resistive interconnect (1996) (1)
Predictions , Challenges , and Opportunities in CMOS Compatible On-Chip Optical Interconnect (1)
Physical Design Techniques for 3-D ICs (2009) (1)
World Abstracts on Microelectronics and Reliability (1)
Stripline Topology for Flux Mitigation (2023) (1)
Chapter 11 – Conclusions (2009) (1)
Logic Locking in Single Flux Quantum Circuits (2021) (1)
Buffer Sizing for Crosstalk Induced Delay Uncertainty (2004) (1)
Methodology to achieve higher tolerance to delay variations in synchronous circuits (2010) (1)
Thermal Modeling of Rapid Single Flux Quantum Circuit Structures (2022) (1)
Power characteristics of inductive interconnect (2003) (1)
A Semi-Analytical Simulation Model for Capacitor Based E-O Modulators (2006) (1)
PMTJ Temperature Sensor Utilizing VCMA (2019) (1)
Memristors and Related Applications (2011) (1)
Computationally efficient clustering of power supplies in heterogeneous real time systems (2014) (1)
Power noise in 14, 10, and 7 nm FinFET CMOS technologies (2016) (1)
Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique (2020) (1)
Effects of Inductance On The Propagation Delay and Repeater Insertion Process in RLC Lines (2001) (1)
Minimizing noise via shield and repeater insertion (2009) (1)
Feedback in silicon compilers (1985) (1)
Impedance/Noise Issues in On-Chip Power Distribution Networks (2008) (1)
Clock Skew Scheduling of Level-Sensitive Circuits (2009) (1)
Clock and Power Distribution Networks for 3-D Integrated Circuits (2009) (1)
Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures (2019) (1)
19th Int'l Symposium on Quality Electronic Design (2018) (1)
Layer ordering to minimize TSVs in heterogeneous 3-D ICs (2016) (1)
Secure Power Management and Delivery Within Intelligent Power Networks on-Chip (2017) (1)
Inductive Noise Coupling in Superconductive Passive Transmission Lines (2021) (1)
Design models of resistive crossbar arrays with selector devices (2016) (1)
Physical Design Trends for Interconnects (2008) (1)
EMI Suppression With Distributed $LLC$ Resonant Converter for High-Voltage VR-on-Package (2020) (1)
Subthreshold Leakage Current Characteristics of Dynamic Circuits (2006) (1)
A substrate noise circuit for accurately testing mixed-signal ICs (2002) (1)
What are clock distribution networks? (2005) (1)
From 100 milliwatts/MIPS to 10 microwatts/MIPS [low-power VLSI] (1994) (1)
The limiting performance of a CMOS bistable register based on waveform considerations (1992) (1)
Complex ±1 Multiplier Based on Signed-Binary Transformations (2004) (1)
Electrical Properties of Through Silicon Vias (2017) (1)
Noise estimation due to signal activity for capacitively coupled CMOS logic gates (2000) (1)
Tapered buffers for gate array and standard cell circuits (1994) (1)
Representatives IEEE Solid-State Circuits Society IEEE Neural Networks Society IEEE Sensors Council (2004) (0)
Test Circuits for 3-D Systems Integration (2012) (0)
A two level metal, software compatible, CMOS/SOS gate array family (1983) (0)
On-Chip Power Noise Reduction Techniques (2011) (0)
Design of tapered serial chains for reduced delay and power dissipation (1994) (0)
Rapid Single Flux Quantum (RSFQ) Circuits (2021) (0)
All-JJ Logic Based on Bistable JJs (2023) (0)
Retiming and Clock Scheduling for High-performance Synchronous Circuits (1998) (0)
Isca (2021) (0)
Power Optimization Based on Link Breaking Methodology (2016) (0)
Superconductive IC Manufacturing (2021) (0)
Sub-crosspoint RRAM decoding for improved area efficiency (2014) (0)
Repeater Insertion in Tree Structured (2001) (0)
Inductance Model of Interdigitated Power and Ground Networks (2016) (0)
Efficiency analysis of a high frequency buck converter for on–chip integration with a dual–VDDmicroprocessor (2002) (0)
Power Noise Reduction Techniques (2016) (0)
GALS Clocking and Shared Interconnect for Large Scale SFQ Systems (2021) (0)
Compact Model of Superconductor-Ferromagnetic Transistor (2021) (0)
Signal Transfer in ICs with Multiple Supply Voltages (2006) (0)
Variation of Grid Inductance with Frequency (2011) (0)
Wave Pipelining in DSFQ Circuits (2021) (0)
A 150-MHz 1.25 mu m CMOS/SOS DSP integrated circuit (1989) (0)
Clock Skew Scheduling in Rotary Clocking Technology (2009) (0)
Timing Optimization for Multiterminal Interconnects (2009) (0)
Receiver power issues related to matched filter implementation for portable wireless communication terminals (1995) (0)
Integrated Circuit Signal Delay (1999) (0)
Chapter 3 TRADE-OFFS IN CMOS VLSI CIRCUITS (0)
On-chip optical interconnect for reduced delay uncertainty (2007) (0)
Case Study: Clock Distribution Networks for Three-Dimensional ICs (2017) (0)
Tile-Based Power Delivery Networks for High Current, Voltage Stacked Systems (2021) (0)
Graphs in VLSI (2023) (0)
Interconnect Prediction Models (2009) (0)
Physical Design Techniques for Three-Dimensional ICs (2017) (0)
On-chip Power Noise Reduction Techniques in High Performance ICs (2008) (0)
Challenges in ultra deep submicrometer high performance VLSI circuits (2004) (0)
Sense Amplifier for Spin-Based Cryogenic Memory Cell (2021) (0)
Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical Interconnect (2010) (0)
Distributed Port Assignment for Extraction of Power Delivery Networks (2020) (0)
Timing Properties of Synchronous Systems (2000) (0)
Hybrid Voltage Regulator (2016) (0)
Power Delivery for Three-Dimensional ICs (2017) (0)
Hierarchical Power Distribution Networks (2016) (0)
SPROUT—Smart Power Routing Tool for Board-Level Exploration and Prototyping (2022) (0)
Low Power Quasi-Resonant Interconnects (2006) (0)
2000 IEEE Workshop on Signal Processing Systems : SiPS 2000 : design and implementation, 11-13 October, 2000, Lafayette, Louisiana (2000) (0)
Intelligent Power Networks On-Chip (2016) (0)
Link breaking methodology: mitigating noise within power networks (2012) (0)
Scaling Trends of Power Supply Noise in TSV-Based Three-Dimensional Integrated Circuits (2014) (0)
Power Supply Clustering in Heterogeneous Systems (2016) (0)
Conclusions (2021) (0)
Algorithms, architectures, and circuits for vlsi-based cdma communications (2005) (0)
Thermal Management Techniques (2009) (0)
Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths (2001) (0)
Timing of Large RSFQ Digital Circuits (2005) (0)
Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor (2018) (0)
Temperature-Frequency Boundary of Cryogenic Dynamic Logic (2023) (0)
Chapter 7 – Interconnect Prediction Models (2017) (0)
A differential high-speed digital CMOS buffer with hysteresis for improved noise immunity (2000) (0)
Noise Characteristics of On-Chip Power Networks with Decoupling Capacitors (2016) (0)
Chapter 21 – Conclusions (2017) (0)
Interconnect-Based Design Methodologies for Three-Dimensional (2009) (0)
Synchronization in Three-Dimensional ICs (2017) (0)
Distributed LDO regulators in a 28 nm power delivery system (2015) (0)
Chapter 11 – Timing Optimization for Multiterminal Interconnects* (2017) (0)
Energy metrics for power efficient crosslink and mesh topologies (2012) (0)
Inductive coupling effects in large TSV arrays (2015) (0)
Josephson Junction Stuck-At Fault Detection in SFQ Circuits (2023) (0)
Computer-Aided Design and Analysis (2011) (0)
Impedance Characteristics of Multi-Layer Grids (2016) (0)
Resistive Memory Based Acceleration of Data Intensive Computing (2013) (0)
Floorplanning Algorithm to Minimize Thermal Interactions (2014) (0)
A repeater timing model and insertion algorithm to reduce delay in RC tree structures (1998) (0)
Clock Scheduling for Improved Reliability (2000) (0)
Converter Topologies for On-Package Voltage Stacking (2022) (0)
Exploiting Hysteresis in a CMOS (1996) (0)
A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects (2016) (0)
Dynamic Single Flux Quantum Majority Gates (2021) (0)
Multiple On-Chip Power Supply Systems (2016) (0)
Noise Coupling in TSV-Based Heterogeneous 3-D ICs (0)
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping (2021) (0)
Chapter 8 – Timing Optimization for Multiterminal Interconnects (2009) (0)
Accurate and Efficient Evaluation of the Transient Response in RLC Circuits: The DTT Method (2001) (0)
Mosfet Current T-Voltage Characteristics (2001) (0)
Clock Skew Scheduling and Clock Tree Synthesis (2009) (0)
Computer-Aided Design of Power Distribution Networks (2016) (0)
Design Methodology for Synthesizing Clock Distribution Networks Exploiting Nonzero Localized Clock S-Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (2004) (0)
Multi-layer Interdigitated Power Networks (2016) (0)
3-D ICs as a Platform for IoT Devices (2017) (0)
Thermal Management Strategies for Three-Dimensional ICs (2017) (0)
Case Study: Clock Distribution Networks for 3-D ICs (2009) (0)
Design challenges in high performance three-dimensional circuits (2009) (0)
ased Design Environment for Single Flux uantum Circuits (1997) (0)
Scaling Trends of On-Chip Power Noise (2016) (0)
Inductive Properties of Electric Circuits (2016) (0)
a CMOS Bistable Register (1993) (0)
Signal Delay in VLSI Systems (2000) (0)
SFQ/DQFP Interface Circuits (2023) (0)
Superconductive Circuits (2021) (0)
Variability Issues in Three-Dimensional ICs (2017) (0)
2008 IEEE CIRCUITS AND SYSTEMS SOCIETY (2008) (0)
Graph-Based Power Network Routing for Board-Level High Performance Systems (2020) (0)
Sources of Power Consumption in CMOS ICs (2006) (0)
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS (1994) (0)
Case Study: 3-D Power Distribution Topologies and Models (2017) (0)
Clock and Power Distribution Networks for 3-D ICs (2009) (0)
Inductance/Area/Resistance Tradeoffs (2016) (0)
NOCS 2007 Committees (2007) (0)
3D IC Floorplanning Based on Thermal Interactions (2018) (0)
Design Guidelines for ERSFQ Bias Networks (2021) (0)
Grid-Based Redistribution Layers Within 3-D Power Networks (2021) (0)
Evaluating the Transient Response of Linear Networks (2001) (0)
Nanosession: Logic Devices and Circuit Design (2013) (0)
Chapter 20 – 3-D Circuit Architectures (2017) (0)
Simultaneous shield and repeater insertion (2009) (0)
Repeater Inser tion in Tree Structured Inductive Interconnect : Under lying Theory (2001) (0)
MTJ-Based Dithering for Stochastic Analog-to-Digital Conversion (2021) (0)
Optimizing RC tree delay in high speed ASICs through repeater insertion (1998) (0)
Inductive Properties of On-Chip Power Distribution Grids (2016) (0)
Inductive Effects in On-Chip Power Distribution Networks (2004) (0)
Delay Insertion and Clock Skew Scheduling (2009) (0)
Passivity-Based Automated Design of Stable Multi-Feedback Distributed Power Delivery Systems (2017) (0)
Optimum Wire Shaping of an � Interconnect (2003) (0)
Inductive noise coupling in multilayer superconductive ICs (2022) (0)
Sense Amplifier for Spin-Based Cryogenic Memory Cells (2019) (0)
Manufacturing of Three-Dimensional Packaged Systems (2017) (0)
Three-Dimensional ICs with Inductive Links (2017) (0)
Low‐Voltage Power Supplies (2006) (0)
Inductive Coupling Noise in Multilayer Superconductive ICs (2021) (0)
Physics and Devices of Superconductive Electronics (2021) (0)
Test point insertion for RSFQ circuits (2017) (0)
Buck Converters for On‐Chip Integration (2006) (0)
Exploratory power noise models of standard cell 14, 10, and 7 nm FinFET ICs (2016) (0)
Double Magnetic Tunnel Junction-Based Nonvolatile Logic (2022) (0)
Chapter 10 – Timing Optimization for Two-Terminal Interconnects* (2017) (0)
Cost Considerations for Three-Dimensional Integration (2017) (0)
Clock Scheduling and Clock Tree Synthesis (2000) (0)
Manufacturing of 3-D Packaged Systems (2009) (0)
High Performance Power Distribution Systems (2011) (0)
3-D Integrated Circuit Fabrication Technologies (2009) (0)
A Performance On-Demand Approach to Power-Efficient Computing (2004) (0)
Characterizing Inductance Effects in RLC Trees (2001) (0)
Introduction (2021) (0)
Stability in Distributed Power Delivery Systems (2016) (0)
Case Study: Thermal Coupling in 3-D Integrated Circuits (2017) (0)
Modeling of On-Chip Simultaneous Swithcing Noise in VDSM CMOS Circuits (2000) (0)
Nanoscale on-chip decoupling capacitors (2008) (0)
Power Efficiency of 14 nm MCML Near Threshold Circuits (2013) (0)
On-Chip Power Distribution Networks (2016) (0)
Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing (2022) (0)
EDA for Superconductive Electronics (2021) (0)
Synchronization (2021) (0)
Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs (2017) (0)

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