Edward Joseph Mccluskey
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Engineering Computer Science
Edward Joseph Mccluskey's Degrees
- Bachelors Electrical Engineering University of California, Berkeley
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(Suggest an Edit or Addition)Edward Joseph Mccluskey's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Minimization of Boolean functions (1956) (820)
- Error detection by duplicated instructions in super-scalar processors (2002) (584)
- Concurrent Error Detection Using Watchdog Processors - A Survey (1988) (583)
- Control-flow checking by software signatures (2002) (578)
- Probabilistic Treatment of General Combinational Networks (1975) (441)
- Built-In Self-Test Techniques (1985) (392)
- Curriculum 68: Recommendations for academic programs in computer science: a report of the ACM curriculum committee on computer science (1968) (359)
- Logic design principles - with emphasis on testable semicustom circuits (1986) (309)
- Which concurrent error detection scheme to choose ? (2000) (296)
- An experimental chip to evaluate test techniques experiment results (1995) (287)
- Introduction to the theory of switching circuits (1965) (285)
- ED4I: Error Detection by Diverse Data and Duplicated Instructions (2002) (271)
- Design for Autonomous Test (1981) (266)
- Verification Testing - A Pseudoexhaustive Test Technique (1984) (230)
- Altering a pseudo-random bit sequence for scan-based BIST (1996) (208)
- Stuck-fault tests vs. actual defects (2000) (186)
- Software-implemented EDAC protection against SEUs (2000) (185)
- Fault Equivalence in Combinational Logic Networks (1971) (177)
- Very-low-voltage testing for weak CMOS logic ICs (1993) (169)
- Logic synthesis of multilevel circuits with concurrent error detection (1997) (163)
- Pseudorandom Testing (1987) (160)
- Diagnosing CMOS bridging faults with stuck-at fault dictionaries (1990) (159)
- Testing for resistive opens and stuck opens (2001) (149)
- "RESISTIVE SHORTS" WITHIN CMOS GATES (1991) (145)
- Reconfigurable architecture for autonomous self-repair (2004) (124)
- Test point insertion based on path tracing (1996) (120)
- Word-voter: a new voter design for triple modular redundant systems (2000) (108)
- Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST (1995) (106)
- Gate exhaustive testing (2005) (103)
- Control-flow checking using watchdog assists and extended-precision checksums (1989) (103)
- Built-In Self-Test Structures (1985) (103)
- Detecting delay flaws by very-low-voltage testing (1996) (102)
- Common-mode failures in redundant VLSI systems: a survey (2000) (100)
- Finite state machine synthesis with concurrent error detection (1999) (98)
- Signal Flow Graph Techniques for Sequential Circuit State Diagrams (1963) (97)
- Analysis of Logic Circuits with Faults Using Input Signal Probabilities (1975) (96)
- Bit-fixing in pseudorandom sequences for scan BIST (2001) (96)
- Detecting bridging faults with stuck-at test sets (1988) (95)
- Multiple-output propagation transition fault test (2001) (93)
- PADded cache: a new fault-tolerance technique for cache memories (1999) (91)
- The Coding of Internal States of Sequential Circuits (1964) (83)
- IC quality and test transparency (1989) (81)
- Designing CMOS Circuits for Switch-Level Testability (1987) (78)
- On-line delay testing of digital circuits (1994) (75)
- A Statistical Failure/Load Relationship: Results of a Multicomputer Study (1982) (74)
- DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS (1991) (73)
- A reliable LZ data compressor on reconfigurable coprocessors (2000) (71)
- TWO-PATTERN TEST CAPABILITIES OF AUTONOMOUS TPG CIRCUITS (1991) (70)
- A Design Diversity Metric and Analysis of Redundant Systems (2002) (70)
- Probability models for pseudorandom test sequences (1988) (69)
- Delay defect screening using process monitor structures (2004) (68)
- Hybrid designs generating maximum-length sequences (1988) (68)
- Column-Based Precompiled Configuration Techniques for FPGA (2001) (68)
- Multivalued Integrated Injection Logic (1977) (67)
- Circuits for pseudoexhaustive test pattern generation (1988) (67)
- Derivation of optimum test sequences for sequential machines (1964) (66)
- A design diversity metric and reliability analysis for redundant systems (1999) (65)
- Transformed pseudo-random patterns for BIST (1995) (64)
- Quantitative analysis of very-low-voltage testing (1996) (64)
- Analysis of pattern-dependent and timing-dependent failures in an experimental test chip (1998) (64)
- Circuits for Pseudo-Exhaustive Test Pattern Generation. (1986) (62)
- IC qualityd and test transparency (1988) (61)
- Dependable adaptive computing systems-the ROAR project (1998) (61)
- Error detection by selective procedure call duplication for low energy consumption (2002) (60)
- Dependable Computing and Online Testing in Adaptive and Configurable Systems (2000) (60)
- ELF-Murphy data on defects and tests sets (2004) (60)
- Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique (1986) (59)
- Design of Digital Computers (1975) (59)
- Concurrent Fault Detection Using a Watchdog Processor and Assertions (1983) (58)
- Launch-on-Shift-Capture Transition Tests (2008) (57)
- Detection of group invariance or total symmetry of a Boolean function (1956) (56)
- Lower Overhead Design for Testability of Programmable Logic Arrays (1984) (56)
- Diagnosis of sequence-dependent chips (2002) (55)
- Switching theory (2003) (52)
- Synthesizing for scan dependence in built-in self-testable designs (1993) (52)
- Linear Feedback Shift Register Design Using Cyclic Codes (1988) (51)
- Built-in reseeding for serial BIST (2003) (50)
- Test data compression (2003) (48)
- A multi-configuration strategy for an application dependent testing of FPGAs (2004) (48)
- Concurrent error detection and testing for large PLA's (1982) (47)
- An experimental chip to evaluate test techniques: chip and experiment design (1995) (47)
- Seed encoding with LFSRs and cellular automata (2003) (46)
- Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection (1994) (46)
- Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs (2005) (46)
- BIST reseeding with very few seeds (2003) (46)
- An Iterative Cell Switch Design for Hybrid Redundancy (1973) (45)
- Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs (1984) (44)
- Orthogonal scan: low overhead scan for data paths (1996) (43)
- Cold delay defect screening (2000) (43)
- Column-Based Precompiled Configurating Techniques for FPGA Fault Tolerance (2001) (42)
- Design techniques for testable embedded error checkers (1990) (41)
- MINVDD testing for weak CMOS ICs (2001) (41)
- Test Length for Pseudorandom Testing (1987) (41)
- Fault grading FPGA interconnect test configurations (2002) (41)
- Executable assertions and flight software (1984) (41)
- Self-Testing Embedded Parity Checkers (1984) (40)
- A Note on the Number of Internal Variable Assignments for Sequential Switching Circuits (1959) (39)
- On-line testing and recovery in TMR systems for real-time applications (2001) (39)
- Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks (1990) (38)
- SHOrt voltage elevation (SHOVE) test for weak CMOS ICs (1997) (38)
- Three-pattern tests for delay faults (1994) (38)
- Experimental results for IDDQ and VLV testing (1998) (37)
- The Reduction of Redundancy in Solving Prime Implicant Tables (1962) (36)
- Quality and single-stuck faults (1993) (36)
- A memory coherence technique for online transient error recovery of FPGA configurations (2001) (35)
- Fault Location in FPGA-Based Reconfigurable Systems (1998) (35)
- Fault-Tolerant Systems in A Space Environment: The CRC ARGOS Project (1998) (34)
- Transients in combinational logic circuits (1962) (33)
- Automated logic synthesis of random pattern testable circuits (1994) (33)
- Built-In Verification Test (1982) (33)
- Minimum-state sequential circuits for a restricted class of incompletely specified flow tables (1962) (33)
- Permanent fault repair for FPGAs with limited redundant area (2001) (33)
- An Essay on Prime Implicant Tables (1961) (32)
- California scan architecture for high quality and low power testing (2007) (32)
- Fault-tolerant computing for radiation environments (2001) (31)
- On the testing of multiplexers (1988) (31)
- Iterative Combinational Switching Networksߞ General Design Considerations (1958) (31)
- Reduction of Feedback Loops in Sequential Circuits and Carry Leads in Iterative Networks (1962) (31)
- Testing for tunneling opens (2000) (30)
- Software implemented hardware fault tolerance (2000) (30)
- Optimized reseeding by seed ordering and encoding (2005) (30)
- Performance evaluation of checksum-based ABFT (2001) (30)
- Floating Point Fault Tolerance with Backward Error Assertions (1995) (29)
- Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets (1986) (29)
- On the modeling and testing of gate oxide shorts in CMOS logic gates (1991) (27)
- Functional tests for scan chain latches (1995) (26)
- Verification Testing (1982) (26)
- Logic Design of Multivalued I2L Logic Circuits (1979) (26)
- Parallel Signatur Analysis Design with Bounds on Aliasing (1997) (25)
- Analysis of Gate Oxide Shorts in CMOS Circuits (1993) (25)
- An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets (1984) (25)
- Classifying Bad Chips and Ordering Test Sets (2006) (24)
- Switch Complexity in Systems with Hybrid Redundancy (1973) (24)
- An undergraduate computer engineering option for electrical engineering (1971) (24)
- Analysis and detection of timing failures in an experimental Test Chip (1996) (24)
- Synthesis-for-scan and scan chain ordering (1996) (23)
- Detecting stuck-open faults with stuck-at test sets (1989) (23)
- ATPG for scan chain latches and flip-flops (1997) (23)
- Testability Considerotions in Microprocessor-Based Design (1980) (23)
- Diversity techniques for concurrent error detection (2001) (23)
- A self-test and self-diagnosis architecture for boards using boundary scans (1989) (23)
- Minimal sums for boolean functions having many unspecified fundamental products (1961) (22)
- A survey of switching circuit theory (1962) (21)
- Combinational logic synthesis for diversity in duplex systems (2000) (21)
- CMOS scan-path IC design for stuck-open fault testability (1987) (21)
- The Watchdog Task: Concurrent error detection using assertions (1985) (21)
- Design of redundant systems protected against common-mode failures (2001) (20)
- Error-correcting codes — A linear programming approach (1959) (20)
- An evaluation of pseudo random testing for detecting real defects (2001) (19)
- Applying two-pattern tests using scan-mapping (1996) (19)
- How Many Test Patterns are Useless? (2008) (19)
- Failing Frequency Signature Analysis (2008) (19)
- VLSI Design for Testability (1984) (19)
- Fundamental mode and pulse mode sequential circuits (1962) (18)
- Design of large embedded CMOS PLAs for built-in self-test (1988) (18)
- Concurrent System-Level Error Detection Using a Watchdog Processor (1985) (18)
- Low Energy Error Detection Technique Using Procedure Call Duplication (2001) (17)
- Speed clustering of integrated circuits (2004) (17)
- Fast run-time fault location in dependable FPGA-based applications (2001) (17)
- Transient errors and rollback recovery in LZ compression (2000) (17)
- Efficient multiplexer synthesis techniques (2000) (17)
- Non-conventional faults in BiCMOS digital circuits (1992) (17)
- Multilevel I2L with threshold gates (1977) (17)
- Detecting resistive shorts for CMOS domino circuits (1998) (17)
- High-level synthesis for orthogonal scan (1997) (17)
- Test and Diagnosis Procedure for Digital Networks (1971) (16)
- Hardware Fault-Tolerance (1985) (16)
- Checking experiments to test latches (1995) (16)
- A Hybrid Design of Maximum-Length Sequence Generators (1986) (16)
- Fault escapes in duplex systems (2000) (15)
- Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage results (1989) (15)
- Algebraic minimization and the design of two-terminal contact networks (1956) (14)
- Sequential Circuit Output Probabilities From Regular Expressions (1978) (14)
- IDDQ data analysis using current signature (1998) (14)
- Efficient design diversity estimation for combinational circuits (2004) (14)
- Logical design theory of NOR gate networks with no complemented inputs (1963) (14)
- Detecting bridging faults in dynamic CMOS circuits (1997) (14)
- Bridging, transition, and stuck-open faults in self-testing CMOS checkers (1991) (14)
- An output encoding problem and a solution technique (1997) (13)
- Testability of parity checkers (1989) (13)
- Multiple stuck-at fault testability of self-testing checkers (1988) (13)
- ALGEBRAIC PROPERTIES OF FAULTS IN LOGIC NETWORKS. (1970) (13)
- Calculation of Coverage Parameter (1987) (13)
- Test Length for Pseudo Random Testing (1985) (13)
- SHOrt Voltage Elevation (SHOVE) test (1996) (13)
- Design for testability (1986) (12)
- Effective TARO pattern generation (2005) (12)
- Quantitative Evaluation of Self-Checking Circuits (1984) (12)
- DESIGN DIVERSITY FOR REDUNDANT SYSTEMS (1999) (12)
- Primitive Polynomial Generation Algorithms Implementation and Performance Analysis (2004) (12)
- A comparison of sequential and iterative circuits (1960) (12)
- An Experiment on Intermittent-Failure Mechanisms (1987) (12)
- An ACS robotic control algorithm with fault tolerant capabilities (2000) (11)
- RP-SYN: synthesis of random pattern testable circuits with test point insertion (1999) (11)
- Behavioral synthesis of testable systems with VHDL (1990) (11)
- Stuck-At Fault Detection in Parity Trees (1986) (11)
- An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment (1994) (11)
- Simple Bounds on Serial Signature Analysis Aliasing for Random Testing (1992) (11)
- Microcomputers in the Computer Engineering Curriculum (1977) (10)
- S: Error Detection by Diverse Data and Duplicated Instructions (2002) (10)
- Design diversity for concurrent error detection in sequential logic circuits (2001) (10)
- Fault Equivalence in Sequential Machines. (1971) (10)
- Minicomputers in the Digital Laboratory Program (1973) (10)
- Panel Discussions (1955) (9)
- Writing executable assertions to test flight software (1984) (9)
- Experimental results for slow-speed testing (2002) (9)
- An apparatus for pseudo-deterministic testing (1994) (9)
- Iddq test pattern generation for scan chain latches and flip-flops (1997) (9)
- REFINED BOUNDS ON SIGNATURE ANALYSIS ALIASING FOR RANDOM TESTING (1991) (9)
- Logic Synthesis for Concurrent Error Detection (1993) (9)
- Encoding of incompletely specified Boolean matrices (1899) (8)
- Comparing causes of system failure (1986) (8)
- Bounds on signature analysis aliasing for random testing (1991) (8)
- Cosine survey of electrical engineering departments (1973) (8)
- Scan synthesis for one-hot signals (1997) (8)
- Dependable Adaptive Computing Systems the Stanford Crc Roar Project (2001) (8)
- Roundtable : Test data compression (2003) (8)
- An Experimental Study Comparing 74LS181 Test Sets (1985) (7)
- Partial hardware partitioning: a new pseudo-exhaustive test implementation (1988) (7)
- Some faults need an Iddq test (1996) (7)
- Modeling power-supply disturbances in digital circuit (1986) (7)
- Why We Need Design-for-testability (1991) (7)
- Comparisons of Various Scan Delay Test Techniques (2005) (7)
- Multiple Fault Detection in Parity Trees (1986) (7)
- Linear Complexity Assertions for Sorting (1994) (7)
- Testing digital circuits with constraints (2002) (6)
- Arithmetic and galois checksums (1989) (6)
- Pseudo-random pattern testing of bridging faults (1997) (6)
- An exponential failure/load relationship: results of a multi-computer statistical study (1981) (6)
- A Synthesis-for-Test Design System (1994) (6)
- Open faults in BiCMOS gates (1994) (6)
- ACS Implementation of A Robotic Control Algorithm with Fault Tolerant Capabilities (2000) (6)
- The critical path for multiple faults (1989) (6)
- Design for testability and testing of IEEE 1149.1 TAP controller (2002) (5)
- Fault tolerance in adaptive real-time computing systems (2001) (5)
- Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic (1994) (5)
- Boolean Network Probabilities and Network Design (1978) (5)
- A simple technique for locating gate-level faults in combinational circuits (1995) (5)
- Dependable computing techniques for reconfigurable hardware (2001) (5)
- Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis (1984) (5)
- Some faults need an I/sub ddq/ test (1996) (5)
- Center for Reliable Computing TECHNICAL REPORT ED 4 I : Error Detection by Diverse Data and Duplicated Instructions (2001) (5)
- Test quality for high level structural test (2004) (5)
- Techniques for estimation of design diversity for combinational logic circuits (2001) (5)
- Diagnosis of tunneling opens (2001) (4)
- ACM Curricula Recommendations for Computer Science (1983) (4)
- Effectiveness of single fault tests to detect multiple faults in parity trees (1987) (4)
- ALGORITHM-BASED FAULT TOLERANCE: A PERFORMANCE PERSPECTIVE BASED ON ERROR RATE (2001) (4)
- Fast Run-Time Fault Location in Dependable FPGAs (2001) (4)
- Recurrent Test Patterns (1983) (4)
- A VLSI CMOS Circuit Design Technique to Aid Test Generation (1986) (4)
- Inconsistent Fail due to Limited Tester Timing Accuracy (2008) (4)
- Fault-Tolerance Projects at Stanford CRC (1999) (4)
- Procedure call duplication: minimization of energy consumption with constrained error detection latency (2001) (4)
- Design of Low-Cost General-Purpose Self-Diagnosing Computers (1974) (4)
- On benchmarking digital testing systems (1988) (4)
- Design of a parallel encoder/decoder for the Hamming code, using ROM (1972) (3)
- Test chip experimental results on high-level structural test (2005) (3)
- ACM Recommended Curricula for Computer Science and Information Processing Programs in Colleges and Universities, 1968-1981 (1981) (3)
- Error Sequence Analysis (2008) (3)
- CONTROL-FLOW CHECKING WATCHDOG ASSISTS AND EXTENDED-PRECISION CHECKSUMS USING (1989) (3)
- LOW-OVERHEAD BUILT-IN BIST RESEEDING (2002) (3)
- Efficient Multiplexer Synthesis (2000) (3)
- Backward error assertions for checking solutions to systems of linear equations (1989) (3)
- Review: B. Dunham, R. Fridshal, The Problem of Simplifying Logical Expressions (1960) (3)
- Assignment of carry variables in iterative networks (1961) (3)
- Relating aliasing in signature analysis to test length and register design (1991) (3)
- Test Set Reordering Using the Gate Exhaustive Test Metric (2007) (3)
- Design of Autonomous TPG Circuits for Use in Two-Pattern Testing (1995) (3)
- BIST-guided ATPG (2005) (3)
- Delay Testing for Sequential Circuits with Scan (1997) (2)
- Summary of Structural integrity Checking (1980) (2)
- Two CMOS Metastability Sensors (1986) (2)
- Center for Reliable Computing: current research. (1975) (2)
- Improving Detectability of Resistive Open Defects in FPGAs (2002) (2)
- LogicDesign of Multivalued 12L Logic Circuits (1979) (2)
- Test Point Insertion for Non-Feedback Bridging Faults (1998) (2)
- Dynamic assertion testing of flight control software (1985) (2)
- A model for parallel computer systems (1970) (2)
- AVOIDING ILLEGAL STATES IN PSEUDORANDOM TESTING OF DIGITAL CIRCUITS (2002) (2)
- Logic design of multi-valued I 2 L logic circuits (1978) (2)
- Techniques for test output response analysis (1991) (1)
- WSIM: A Symbolic Waveform Simulator (1994) (1)
- Dependable reconfigurable computing design diversity and self repair (2002) (1)
- Practice and Theory (1988) (1)
- Digital integrated circuit testing for art historians and test experts (2004) (1)
- Ieee Vlsi Test Symposium (2011) (1)
- Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns (2010) (1)
- Center for Reliable Computing (1999) (1)
- Comments on Determination of Redundancies in a Set of Patterns (1957) (1)
- The Effect of Fault Dropping on Fault Simulation Time (1993) (1)
- A methodology for testing fault-tolerant software (1985) (1)
- Fundamental Mode and Pulse Mode Operations of Sequential Circuits (1962) (1)
- Exhaustive and Pseudo-Exhaustive Testing. (1987) (1)
- Synthesis of autonomous TPG circuits oriented for two-pattern testing (1992) (1)
- Synthesis for Scan Dependence in Built-In Self-Testable Designs (1994) (1)
- Proceedings of the third ACM symposium on Operating systems principles (1971) (1)
- Modeling the effect of chip failures on cache memory systems (1987) (1)
- The Measurement and Statistical Modeling of Computer Reliability as Affected by System Activity (1985) (1)
- NON-SELF-TESTABLE FAULTS IN DUPLEX SYSTEMS (1999) (1)
- Inadequacy of Conventional Dynamic Recovery Mechanisms in the Presence of Temporary Failures. (1987) (1)
- Review: Shreeram Abhyankar, Minimal "Sum of Products of Sums" Expressions of Boolean Functions (1959) (0)
- Review: Shreeram Abhyankar, Absolute Minimal Expressions of Boolean Functions (1959) (0)
- 1 OUTPUT ENCODING FOR HAZARD-FREE ROBUST PATH DELAY FAULT TESTABILITY (0)
- 1982 International Symposium on Fault-Tolerant Computing (FTCS-12) Preprints. (1982) (0)
- Teaching Testing (1983) (0)
- Reliability Evaluation of Computer Systems (1979) (0)
- Review: Albert A. Mullin, Wayne G. Kellner, A Residue Test for Boolean Functions (1960) (0)
- A method of shuffling compactor inputs in VLSI self-testing (1991) (0)
- A Method and the Effect of Shuffling Compactor Inputs in VLSI Self-Testing (1992) (0)
- An Undergraduate Computer Engineering Option (2018) (0)
- Future Directions in Computer Architecture (2006) (0)
- Practice and theory (IC testing) (1988) (0)
- Review: James T. Culbertson, Mathematics and Logic for Digital Devices (1958) (0)
- Debating the Future of Burn-In (2002) (0)
- Using checking experiments to test two-state latches (2001) (0)
- Appendix A . Testing for Tunneling Opens (2000) (0)
- Reliable Digital Systems and Related Stanford University Research (1987) (0)
- 43 – Logic Design (2002) (0)
- Integrated Circuit Gates (1975) (0)
- Minicomputers in the Digital Laboratory April 1972 I Program (0)
- On properties and implementations of inverting ALSC for use in built-in self-testing (1993) (0)
- T e s t P oi nt I ns e rt i on for N on-F e e dback B ri dgi ng F aul t s (1996) (0)
- Design of the Detector II: A CMOS Gate Array for the Study of Concurrent Error Detection Techniques. (1987) (0)
- Review: Edwin Hirschhorn, Simplification of a Class of Boolean Functions (1958) (0)
- Testers don ' t always work when you need them ! ) Defects vs . Faults Some Data from the ELF 35 and Murphy Chips (2002) (0)
- University computer curricula (1974) (0)
- Center for Reliable Computing TECHNICAL REPORT Built-In Reseeding for Built-In Self Test (2003) (0)
- Counting Two-State Transition-Tour Sequences (1996) (0)
- Jeffrey Richard C.. Arithmetical analysis of digital computing nets. Journal of the Association for Computing Machinery, vol. 3 (1956), pp. 360–375. (1960) (0)
- Pseudorandom BIST: Theory, Simulation and Tester Data (2003) (0)
- Reliable Advanced Electronic Systems Research (1993) (0)
- Critical fault patterns determination in fault-tolerant computer systems (1978) (0)
- Development of a flight software testing methodology (1985) (0)
- Experimental Data on Test Escapes Table of Contents (2005) (0)
- FaultEquivalence inCombinational LogicNetworks (1971) (0)
- ANALYSIS OF LOGIC CIRCUITS WITH FAULTS USING INPUT SIGNAL PROBABILITIES (1995) (0)
- Center for Reliable Computing TECHNICAL REPORT Software-Implemented EDAC Protection Against SEUs (2001) (0)
- Logic design education at Stanford University (1988) (0)
- Example of Scan-Mapping Applying Two-Pattern Tests Using Scan-Mapping (1998) (0)
- Diversity Techniques for Concurrent Error Detection Module 1 Module 2 Comparator Error Figure 1.1. a Duplex System for Ced (2000) (0)
- Test Teaching (1985) (0)
- Memorial session for S. H. Caldwell (1904-1960) (1961) (0)
- Akers Sheldon B. Jr., A truth table method for the synthesis of combinational logic. IRE transactions on electronic computers , vol. EC-10 (1961), pp. 604–615. (1963) (0)
- EllloEllEElll lIEEllll (0)
- Mullin Albert A. and Kellner Wayne G.. A residue test for Boolean functions. Transactions of the Illinois State Academy of Science , vol. 51 nos. 3 and 4, (1958), pp. 14–19. (1960) (0)
- SESSION X: LSI TECHNOLOGY (1975) (0)
- Book Reviews (1822) (0)
- Two-Pattern Test Capabilities of Autonomous TGP Circuits (Special Issue on VLSI Testing and Testable Design) (1993) (0)
- Synthesis-for-Scan and Scan Path Ordering (1998) (0)
- Session Abstract (2006) (0)
- Center for Reliable Computing TECHNICAL REPORT Fault Escapes In Duplex Systems (2000) (0)
- Logic design (2003) (0)
- WHY DEFECTS ESCAPE SOME OF OUR TESTS (2000) (0)
- A Multiplexer (mux) Is a Standard (0)
- Procedure Call Duplication : Minimization of Energy Consumption with Error Detection Latency Constraint (2001) (0)
- Culbertson James T.. Mathematics and logic for digital devices . D. Van Nostrand Company, Inc., Princeton, N. J., New York, Toronto, and London 1958, x + 224 pp. (1958) (0)
- State of the Journal (2016) (0)
- ANALYSIS OF FAIL-ALL-TEST-SET CUTs AND FAIL-SOME-TEST-SET CUTs IN AN EXPERIMENTAL TEST CHIP (1999) (0)
- TECHNIQUES FOR TESTING DIGITAL CIRCUITS WITH ILLEGAL STATES (2001) (0)
- About Signal Flow Graph Techniques for Sequential Circuits (1964) (0)
- Abhyankar Shreeram. Minimal “sum of products of sums” expressions of Boolean functions. IRE transactions on electronic computers, vol. EC-7 (1958), pp. 268–276. (1959) (0)
- Bibliography of 1986 CRC (Center for Reliable Computing) Publications. (1987) (0)
- Reviews ofBooks andPapers intheComputer Field (1959) (0)
- EVALUATION AND DESIGN OF DEPENDABLE SYSTEMS WITH DESIGN DIVERSITY (0)
- ABSTRACT ARITHMETIC AND GALOIS CHECKSUMS (1989) (0)
- Review: Richard C. Jeffrey, Arithmetical Analysis of Digital Computing Nets (1960) (0)
- Invited Lecture by Edward J. McCluskey, the 2008 SIGDA: Pioneering Achievement Award Recipient (2008) (0)
- Proceedings of the 5th Annual Symposium on Computer Architecture, Palo Alto, CA, USA, April 1978 (1978) (0)
- Abhyankar Shreeram. Absolute minimal expressions of Boolean functions. IRE transactions on electronic computers, vol. EC-8 (1959), pp. 3–8. (1959) (0)
- VIII. Switching Functions (1964) (0)
- TheComputer Groupisanassociation ofIEEEmembers withprofessional interest inthefield ofElectronic Computers. AllIEEEmembers areeligible formembership, andwill receive allGrouppublications uponpayment ofafeeof$4.00 peryear. Membersofcertain professional societies areeligible tobeAffiliates ofTheComput (1967) (0)
- Short Pseudorandom Test Sequences. (1987) (0)
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