Eric Beyne

Eric Beyne's AcademicInfluence.com Rankings

Eric Beyne

Engineering

#6964

World Rank

#8321

Historical Rank

Electrical Engineering

#2129

World Rank

#2234

Historical Rank

Applied Physics

#2325

World Rank

#2365

Historical Rank

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Engineering

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Eric Beyne's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology (2010) (306)
MEMS for wireless communications: 'from RF-MEMS components to RF-MEMS-SiP' (2003) (247)
3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias (2006) (191)
3D System Integration Technologies (2006) (178)
3D stacked IC demonstration using a through Silicon Via First approach (2008) (149)
Hermal cycling reliability of snagcu and snpb solder joints: a comparison for several ic-packages (2004) (128)
Multilayer thin-film MCM-D for the integration of high-performance RF and microwave circuits (2001) (126)
The rise of the 3rd dimension for system intergration (2006) (120)
Bow-tie slot antenna fed by CPW (1999) (117)
Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance (2010) (116)
Cu pumping in TSVs: Effect of pre-CMP thermal budget (2011) (116)
Impact of 3D design choices on manufacturing cost (2009) (103)
The indent reflow sealing (IRS) technique-a method for the fabrication of sealed cavities for MEMS devices (2000) (99)
Wafer-level packaging technology for high-Q on-chip inductors and transmission lines (2004) (98)
The 3-D Interconnect Technology Landscape (2016) (90)
A generic methodology for deriving compact dynamic thermal models, applied to the PSGA package (1998) (86)
Through-silicon via and die stacking technologies for microsystems-integration (2008) (81)
A fully-packaged electromagnetic microrelay (1999) (81)
Accurate modeling of high-Q spiral inductors in thin-film multilayer technology for wireless telecommunication applications (2001) (81)
Electrodeposition for the synthesis of microsystems (2000) (79)
Design issues and considerations for low-cost 3D TSV IC technology (2010) (71)
3D interconnection and packaging: impending reality or still a dream? (2004) (71)
Impact of the electrodeposition chemistry used for TSV filling on the microstructural and thermo-mechanical response of Cu (2011) (71)
3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding (2009) (68)
Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration (2011) (67)
Chip-package codesign of a low-power 5-GHz RF front end (2000) (64)
Technologies for highly miniaturized autonomous sensor networks (2006) (56)
Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking (2010) (56)
Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers (2011) (54)
CPW fed cusp antenna (1999) (53)
Mechanical FEM Simulation of bonding process on Cu lowK wafers (2004) (52)
Degradation of Cu6Sn5 intermetallic compound by pore formation in solid-liquid interdiffusion Cu/Sn microbump interconnects (2014) (52)
Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications (2011) (51)
3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias (2011) (50)
SOP integration and codesign of antennas (2004) (50)
Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology (2017) (49)
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot (2009) (49)
Thermal modeling and management in ultrathin chip stack technology (2002) (47)
Impact of post-plating anneal and through-silicon via dimensions on Cu pumping (2013) (47)
Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture (2007) (46)
Temperature dependent electrical characteristics of through-si-via (TSV) interconnections (2010) (43)
Thin-film as enabling passive integration technology for RF SoC and SiP (2005) (42)
Direct gold and copper wires bonding on copper (2003) (41)
Thermomechanical models for leadless solder interconnections in flip chip assemblies (1998) (41)
Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies (2008) (40)
In-depth Raman spectroscopy analysis of various parameters affecting the mechanical stress near the surface and bulk of Cu-TSVs (2012) (39)
Elimination Of The Axial Deformation Problem Of Cu-TSV In 3D Integration (2010) (38)
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV) (2009) (38)
Integration of passive components for microwave filters in MCM-D (1997) (37)
MULTI-LAYER THIN-FILM MCM-D FOR THE INTEGRATION OF HIGH PERFORMANCE WIRELESS FRONT-END SYSTEMS (2001) (36)
Parameterized Modeling of Thermomechanical Reliability for CSP Assemblies (2003) (36)
Correlation between Cu microstructure and TSV Cu pumping (2014) (36)
Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking (2008) (36)
Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications (2011) (35)
Void-Free Filling of HAR TSVs Using a Wet Alkaline Cu Seed on CVD Co as a Replacement for PVD Cu Seed (2011) (34)
Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology (2013) (33)
Solving Technical and Economical Barriers to the Adoption of Through-Si-Via 3D Integration Technologies (2008) (33)
Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology (2012) (32)
Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process (2016) (32)
Thermal analysis of hot spots in advanced 3D-stacked structures (2009) (31)
Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits (2001) (31)
Electrically yielding Collective Hybrid Bonding for 3D stacking of ICs (2009) (30)
Inductance and quality-factor evaluation of planar lumped inductors in a multilayer configuration (1997) (30)
Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding (2012) (29)
High-$Q$ Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA (2006) (28)
High-Efficiency Polymer-Based Direct Multi-Jet Impingement Cooling Solution for High-Power Devices (2019) (28)
3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies (2007) (28)
Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices — Technology directions (2012) (28)
Formation, processing and characterization of Co-Sn intermetallic compounds for potential integration in 3D interconnects (2015) (27)
Compact thermal modeling of hot spots in advanced 3D-stacked ICs (2009) (27)
Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack (2012) (27)
Reliability Challenges Related to TSV Integration and 3-D Stacking (2016) (27)
A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch (2018) (26)
Cost effectiveness of 3D integration options (2010) (26)
High efficiency direct liquid jet impingement cooling of high power devices using a 3D-shaped polymer cooler (2017) (25)
Circularly polarised aperture antenna fed by CPW and built in MCM-D technology (1999) (25)
Generalized analysis of coupled lines in multilayer microwave MCM-D technology-application: integrated coplanar Lange couplers (1999) (25)
Parylene N as a dielectric material for through silicon vias (2008) (25)
Chip-package co-design of a 5 GHz RF front-end for WLAN (2000) (25)
Experimental characterization and model validation of liquid jet impingement cooling using a high spatial resolution and programmable thermal test chip (2019) (25)
3D stacking induced mechanical stress effects (2014) (24)
Integrated high-frequency inductors using amorphous electrodeposited Co-P core (2002) (24)
Design-oriented measurement-based Scaleable models for multilayer MCM-D integrated passives, implementation in a design library offering automated layout (2000) (24)
Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects (2012) (24)
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping (2009) (24)
Insertion bonding: A novel Cu-Cu bonding approach for 3D integration (2010) (24)
Solder parameter sensitivity for CSP life-time prediction using simulation-based optimization method (2001) (24)
Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips (2011) (23)
Transient thermal modeling and characterization of a hybrid component (1996) (23)
Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices (2012) (23)
Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics (2015) (23)
Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages (2003) (22)
Recent Advances in 3D Integration at IMEC (2006) (22)
Small Pitch, High Aspect Ratio Via-Last TSV Module (2016) (22)
High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias (2013) (22)
Interposer technology for high band width interconnect applications (2013) (22)
Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications (2013) (22)
Integrated microwave filters in MCM-D (1996) (21)
Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology (2007) (21)
Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs (2014) (21)
Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques (2000) (20)
Ni/Cu/Sn bumping scheme for fine-pitch micro-bump connections (2011) (20)
Key elements for sub-50μm pitch micro bump processes (2013) (20)
Through-Silicon via Technology for 3D IC (2011) (20)
X-band brick wall antenna fed by CPW (1998) (20)
Use of Wafer Applied Underfill for 3D Stacking (2011) (20)
Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance (2010) (19)
3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects (2016) (19)
Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs (2010) (19)
The Use of BCB and Photo-BCB Dielectric in MCM-D for High Speed Digital and Microwave Applications (1995) (19)
Spiral inductors integrated in MCM-D using the design space concept (1998) (19)
Measurements and Analysis of Substrate Noise Coupling in TSV-Based 3-D Integrated Circuits (2014) (19)
Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime (2014) (19)
Experimental Thermal Characterisation of Electronic Packages in a Fluid Bath Environment (1997) (18)
Antenna arrays in MCM-D technology fed by coplanar CPW networks (2000) (18)
Analysis of microbump induced stress effects in 3D stacked IC technologies (2012) (18)
Influence of Si wafer thinning processes on (sub)surface defects (2017) (18)
Expected Failures in 3-D Technology and Related Failure Analysis Challenges (2018) (18)
Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages (2016) (18)
A reliable and compact polymer-based package for capacitive RF-MEMS switches (2004) (18)
Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs (2011) (18)
Numerically efficient spatial-domain moment method for multislot transmission lines in layered media-application to multislot lines in MCM-D technology (1999) (17)
Entire Domain Basis Function Expansion of the Differential Surface Admittance for Efficient Broadband Characterization of Lossy Interconnects (2020) (17)
Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's (2011) (17)
A novel concept for ultra-low capacitance via-last TSV (2010) (17)
3D-SIP integration for autonomous sensor nodes (2006) (17)
Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding (2020) (17)
Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies (2012) (17)
Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage (2012) (17)
FET arrays as CPI sensors for 3D stacking and packaging characterization (2012) (17)
FEM study of deformation and stresses in copper wire bonds on Cu lowK structures during processing (2004) (16)
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications (2010) (16)
Full-wave analysis of multiconductor multislot planar guiding structures in layered media (2003) (16)
Ultra low stress and low temperature patternable silicone materials for applications within microelectronics (2004) (16)
Integration of passive components in thin film multilayer MCM-D technology for wireless front-end applications (2000) (16)
Accelerated Ageing with In Situ Electrical Testing: A Powerful Tool for the Building-In Approach to Quality and Reliability in Electronics (1994) (16)
Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration (2016) (16)
Advanced metallization scheme for 3×50µm via middle TSV and beyond (2015) (16)
Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery (2019) (16)
Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices (2015) (16)
Nanohardness study of CoSn/sub 2/ intermetallic layers formed between CO UBM and Sn flip-chip solder joints (2004) (15)
Chip-package co-design of a 4.7 GHz VCO (2000) (15)
Suppression of the parasitic modes in CPW discontinuities using MCM-D technology-application to a novel 3-dB power splitter (1998) (15)
Integration of a low stress photopatternable silicone into a wafer level package (2004) (15)
Compact transient thermal models for the polymer stud grid array (PSGATM) package (1997) (15)
Experimental and numerical investigation of direct liquid jet impinging cooling using 3D printed manifolds on lidded and lidless packages for 2.5D integrated systems (2020) (15)
Advances in microwave MCM-D technology (2000) (15)
Fine pitch copper wire bonding on copper bond pad process optimization (2002) (14)
3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking (2006) (14)
Characterization of through-silicon vias using laser terahertz emission microscopy (2021) (14)
Comparison of a Cu UBM versus a Co UBM for Sn Flip-Chip Bumps (2005) (14)
High-Q integrated spiral inductors for high performance wireless front-end systems (2000) (14)
Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits (2011) (14)
Distributed microwave MCM-D circuits for X- and K-band applications (1999) (14)
Influence of Composition of SiCN as Interfacial Layer on Plasma Activated Direct Bonding (2019) (14)
Low-Cost Energy-Efficient On-Chip Hotspot Targeted Microjet Cooling for High- Power Electronics (2020) (14)
W2W permanent stacking for 3D system integration (2014) (14)
Minimizing interposer warpage by process control and design optimization (2014) (14)
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions (2010) (14)
Wafer-level package interconnect options (2006) (13)
Design issues in heterogeneous 3D/2.5D integration (2013) (13)
Investigation of the reliability of Cu and Co UBM layers in thermal-cycling tests (2003) (13)
3D Printed Liquid Jet Impingement Cooler: Demonstration, Opportunities and Challenges (2018) (13)
Multilayer thin-film technology enabling technology for solving high-density interconnect and assembly problems (2003) (13)
THE RISE OF THE 3 RD DIMENSION FOR SYSTEM INTEGRATION (2006) (13)
Integrated passives for a DECT VCO (2000) (13)
Reflow process optimization for micro-bumps applications in 3D technology (2014) (13)
Extremely Low-Force Debonding of Thinned CMOS Substrate by Laser Release of a Temporary Bonding Material (2016) (13)
Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages (2015) (12)
Impact of oxide liner properties on TSV Cu pumping and TSV stress (2015) (12)
Impact of Via Density on the Mechanical Integrity of Advanced Back-End-of-Line During Packaging (2016) (12)
Statistical Distribution of Through-Silicon via Cu Pumping (2017) (12)
Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects (2016) (12)
Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding (2011) (12)
Experimental Characterization of a Chip-Level 3-D Printed Microjet Liquid Impingement Cooler for High-Performance Systems (2019) (12)
Extreme wafer thinning optimization for via-last applications (2016) (12)
Optimal choice of the FEM damage volumes for estimation of the solder joint reliability for electronic package assemblies (2003) (12)
Characterisation, modelling and design of bond-wire interconnects for chip-package co-design (2003) (12)
3D stacking using Cu-Cu direct bonding (2012) (12)
Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling (2014) (12)
Impact of barrier integrity on liner reliability in 3D through silicon vias (2013) (12)
Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking (2016) (12)
"Hole-in-One TSV", a New Via Last Concept for High Density 3D-SOC Interconnects (2018) (12)
Design of an optimal heat-sink geometry for forced convection air cooling of Multi-Chip Modules (1994) (12)
Direct Au and Cu wire bonding on Cu/low-k BEOL (2002) (12)
Reliability concerns in copper TSV's: Methods and results (2012) (12)
Advances in SiCN-SiCN Bonding with High Accuracy Wafer-to-Wafer (W2W) Stacking Technology (2018) (11)
Optimizing Au and In micro-bumping for 3D chip stacking (2008) (11)
Transient analysis based thermal characterization of die-die interfaces in 3D-ICs (2012) (11)
The influence of packaging materials on RF performance (2002) (11)
3D technology roadmap and status (2011) (11)
Microstructure simulation of grain growth in Cu Through Silicon Via using phase-field modeling (2014) (11)
Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges (2014) (11)
Hydrogen outgassing induced liner/barrier reliability degradation in through silicon via's (2014) (11)
Thermal stability of copper Through-Silicon Via barriers during IC processing (2011) (11)
Outperformance of Cu pillar flip chip bumps in electromigration testing (2011) (11)
High-Q RF inductors on standard silicon realized using wafer-level packaging techniques (2003) (11)
MCM-D technology for integrated passives components (2000) (11)
Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration (2020) (11)
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps (2012) (11)
Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond (2014) (11)
Study of the effect of Sn grain boundaries on IMC morphology in solid state inter-diffusion soldering (2019) (11)
Active-lite interposer for 2.5 & 3D integration (2015) (11)
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations (2011) (11)
Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices (2018) (11)
Design of microwave MCM-D CPW quadrature couplers and power dividers in X-, Ku-, and Ka-band (2000) (11)
An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration (2003) (10)
Cu interconnects and low-k dielectrics, challenges for chip interconnections and packaging (2003) (10)
Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems (2019) (10)
High-Q RF inductors on low resistivity silicon through wafer post-processing (2002) (10)
RIE dynamics for extreme wafer thinning applications (2018) (10)
Technology Assessment of Through-Silicon Via by Using $C$ – $V$ and $C$ – $t$ Measurements (2011) (10)
Electrical characterization, modeling and reliability analysis of a via last TSV (2010) (10)
Modelling of thermal vias in thin film multichip modules (1994) (10)
Through-Si-Via Technology Solutions for 3D System Integration (2009) (10)
A MCM-D-type module for the ATLAS pixel detector (1998) (10)
Fast convolution based thermal model for 3D-ICs: Methodology, accuracy analysis and package impact (2014) (10)
Defect detection in Through Silicon Vias by GHz Scanning Acoustic Microscopy: Key ultrasonic characteristics (2014) (10)
Brick‐wall antenna in multilayer thin‐film technology (1998) (10)
Effects of packaging on mechanical stress in 3D-ICs (2015) (10)
Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs (2020) (9)
Edge trimming for surface activated dielectric bonded wafers (2017) (9)
Modelling and characterisation of the polymer stud grid array (PSGA) package: electrical, thermal and thermo-mechanical qualification (2001) (9)
Evaluation of structural degradation in packaged semiconductor components using a transient thermal characterisation technique (1996) (9)
Effects of isothermal storage on grain structure of Cu/Sn/Cu microbump interconnects for 3D stacking (2019) (9)
Sequential‐rotation arrays of circularly polarized aperture antennas in the MCM‐D technology (2005) (9)
Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance (2013) (9)
Sequential-rotation arrays of circularly polarized CPW-fed aperture antennas in the MCM-D technology (2000) (9)
Evaluation of Mechanical Stress Induced During IC Packaging (2018) (9)
Investigation of Advanced Dicing Technologies for Ultra Low-k and 3D Integration (2016) (9)
A Highly Reliable 1.4μm Pitch Via-Last TSV Module for Wafer-to-Wafer Hybrid Bonded 3D-SOC Systems (2019) (9)
Technology platform for 3-D stacking of thinned embedded dies (2008) (9)
Package level interconnect options (2005) (9)
Experimental thermal characterization and thermal model validation of 3D packages using a programmable thermal test chip (2015) (9)
Compensating differences between measurement and calibration wafer in probe-tip calibrations (2002) (9)
Electrical field induced ageing of polymer light-emitting diodes in an oxygen-rich atmosphere studied by emission microscopy, scanning electron microscopy and secondary ion mass spectroscopy (1998) (9)
Broadband modeling and transient analysis of MCM interconnections (1994) (9)
Accurate RF electrical characterization of CSPs using MCM-D thin film technology (2004) (9)
Modeling Copper Plastic Deformation and Liner Viscoelastic Flow Effects on Performance and Reliability in Through Silicon Via (TSV) Fabrication Processes (2019) (9)
2 × 2 and 4 × 4 arrays of annular slot antennas in MCM-D technology fed by coplanar CPW networks (1999) (8)
3D stacking using Cu-Cu direct bonding for 40um pitch and beyond (2012) (8)
Performance analysis of MCM systems (1997) (8)
Die to wafer 3D stacking for below 10um pitch microbumps (2016) (8)
Numerical comparison of the thermal performance of 3D stacking and Si interposer based packaging concepts (2013) (8)
Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding (2017) (8)
3D stacking of Co- and Ni-based microbumps (2016) (8)
Reliability challenges for barrier/liner system in high aspect ratio through silicon vias (2014) (8)
Analysis of high-Q on-chip inductors realized by wafer-level packaging techniques (2003) (8)
On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing (2013) (8)
THERMO-MECHANICAL ANALYSIS OF A CHIP SCALE PACKAGE (CSP) USING LEAD FREE AND LEAD CONTAINING SOLDER MATERIALS (2004) (8)
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform (2014) (8)
Highly-conformal plasma-enhanced atomic-layer deposition silicon dioxide liner for high aspect-ratio through-silicon via 3D interconnections (2012) (8)
Conjugate Heat Transfer and Fluid Flow Modeling for Liquid Microjet Impingement Cooling with Alternating Feeding and Draining Channels (2019) (8)
Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier (2006) (8)
Cobalt UBM for fine pitch microbump applications in 3DIC (2015) (8)
Integration of the ZoneBOND™ temporary bonding material in backside processing for 3D applications (2012) (8)
Impact of Cu TSVs on BEOL metal and dielectric reliability (2014) (8)
3D IC assembly using thermal compression bonding and wafer-level underfill — Strategies for quality improvement and throughput enhancement (2016) (8)
Fast Transient Convolution-Based Thermal Modeling Methodology for Including the Package Thermal Impact in 3D ICs (2016) (8)
Effect of TSV presence on FEOL yield and reliability (2013) (8)
Influence of printed circuit board properties on solder joint fatigue life of assembled IC packages (2004) (8)
Active-lite interposer for 2.5 & 3D integration (2015) (7)
Introducing a silicone under the bump configuration for stress relief in a wafer level package (2003) (7)
Nozzle scaling effects for the thermohydraulic performance of microjet impingement cooling with distributed returns (2020) (7)
Single-release-layer process for temporary bonding applications in the 3D integration area (2015) (7)
Comparison of x-ray diffraction, wafer curvature and Raman spectroscopy to evaluate the stress evolution in Copper TSV's (2012) (7)
In-line metrology for characterization and control of extreme wafer thinning of bonded wafers (2017) (7)
Low temperature technology options for integrated high density capacitors (2006) (7)
Enabling SPICE-type modeling of the thermal properties of 3D-stacked ICs (2006) (7)
Thermal characterization of the inter-die thermal resistance of hybrid Cu/dielectric wafer-to-wafer bonding (2016) (7)
High density interconnect substrates using multilayer thin film technology on laminate substrates (MCM‐SL/D) (2001) (7)
Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster (2021) (7)
Process characterization of thin wafer debonding with thermoplastic materials (2012) (7)
Cost comparison between 3D and 2.5D integration (2012) (7)
Compact broadband resistance model for microstrip transmission lines (2004) (7)
Si interposer build-up options and impact on 3D system cost (2013) (7)
Mechanical behavior of BEOL structures containing lowK dielectrics during bonding process (2003) (7)
Selective cooling of microelectronics using electrostatic actuated liquid droplets - modelling and experiments (2004) (7)
Wafer applied and no flow underfill screening for 3D stacks (2012) (7)
Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs (2015) (7)
More than just a package - wafer-level packaging of MEMS (2004) (7)
Technology Assessment of Through-Silicon Via by Using <formula formulatype="inline"><tex Notation="TeX"> $C$</tex></formula>–<formula formulatype="inline"><tex Notation="TeX">$V$</tex></formula> and <formula formulatype="inline"> <tex Notation="TeX">$C$</tex></formula>–<formula formulatype="inline"> (2011) (7)
Cost components for 3D system integration (2014) (7)
Spin-on dielectric liner TSV for 3D wafer level packaging applications (2010) (7)
RF characterization and modeling of through-silicon vias (2013) (7)
Wafer reconstruction: An alternative 3D integration process flow (2013) (6)
The underfill-microbump interaction mechanism in 3D ICs: Impact and mitigation of induced stresses (2014) (6)
Experimental and Numerical Study of 3-D Printed Direct Jet Impingement Cooling for High-Power, Large Die Size Applications (2021) (6)
Extreme Thinning of Si Wafers for Via-Last and Multi-wafer Stacking Applications (2018) (6)
Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging (2011) (6)
Thermal Compression Bonding: Understanding Heat Transfer by in Situ Measurements and Modeling (2017) (6)
Extending on-die wiring hierarchy with wafer level packaging concepts (2004) (6)
Convolution based compact thermal model for 3D-ICs: Methodology and accuracy analysis (2013) (6)
Simulation of Cu pumping during TSV fabrication (2013) (6)
Ultra thin electronics for space applications (2001) (6)
Raman spectroscopy study of stress in 3D-stacked chips and correlation with FEM and electrical measurements (2014) (6)
Thermal modelling of the polymer stud grid array (PSGATM) steady-state analysis (1997) (6)
IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs (2021) (6)
CIMID, a technology for high density integration of electronic systems (1994) (6)
Accurate measurement and characterisation of MCM-D integrated passives up to 50 GHz (2000) (6)
Metrology and inspection challenges for manufacturing 3D stacked IC's (2013) (6)
Dielectric liner reliability in via-middle through silicon vias with 3 Micron diameter (2016) (6)
Challenges and solutions on pre-assembly processes for thinned 3D wafers with micro-bumps on the backside (2014) (6)
Materials and Technology for RF-MEMS (2004) (6)
Parametric compact models for the 72-pins polymer stud grid array™ (2001) (6)
Evolution of temporary wafer (de)bonding technology towards low temperature processes for enhanced 3D integration (2012) (6)
Wafer-level packaging technology for extended global wiring and inductors (2003) (6)
Development of multi-stack dielectric wafer bonding (2016) (6)
Processing active devices on Si interposer and impact on cost (2015) (6)
Parametric compact models for flip chip assemblies (2000) (6)
3D-convolution based fast transient thermal model for 3D integrated circuits: methodology and applications (2015) (6)
Thermal fatigue analysis of the flip-chip assembly on the Polymer Stud Grid Array (PSGA/sup TM/) package (1999) (6)
Cu bonding to Cu low K wafers: a systematic study of the mechanical bonding process (2005) (6)
Residual thermomechanical stresses in thinned-chip assemblies (2000) (6)
10 and 7 μm Pitch Thermo-compression Solder Joint, Using A Novel Solder Pillar And Metal Spacer Process (2020) (5)
3D SoC integration, beyond 2.5D chiplets (2021) (5)
Mechanical characterization of micro-bump for aggressive bump scaling (2012) (5)
Advances in Thin Wafer Debonding and Ultrathin 28-nm FinFET Substrate Transfer (2017) (5)
Backside power delivery as a scaling knob for future systems (2019) (5)
RF evaluation of low-cost leadless packages and development of distributed electrical models (2003) (5)
Surface planarization of Cu and CuNiSn Micro-bumps embedded in polymer for below 20μm pitch 3DIC applications (2016) (5)
Investigation of Co UBM for direct bumping on Cu/LowK dies (2003) (5)
Thermo mechanical challenges for processing and packaging stacked ultrathin wafers (2013) (5)
Thermal Management of Electronic Systems II (1997) (5)
Thermal Modeling and Model Validation for 3D Stacked ICs (2019) (5)
First Demonstration of a Low Cost/Customizable Chip Level 3D Printed Microjet Hotspot-Targeted Cooler for High Power Applications (2019) (5)
Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology (2014) (5)
Analytical Thermo-Mechanical Model for Non-Underfilled Area Array Flip Chip Assemblies (2004) (5)
New ultrathin 3D integration technique: technological and thermal investigations (2000) (5)
Film Characterization of Low-Temperature Silicon Carbon Nitride for Direct Bonding Applications (2020) (5)
Thermal compression bonding of 20 μm pitch micro bumps with pre-applied underfill - Process and reliability (2015) (5)
Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning (2015) (5)
Novel Cu–Cu Bonding Technique: The Insertion Bonding Approach (2011) (5)
Methodologies to mitigate package induced stresses in the BEOL (2016) (5)
High-q spiral inductors for high performance integrated RF front-end sub-systems (2000) (5)
Demonstration of Package Level 3D-printed Direct Jet Impingement Cooling applied to High power, Large Die Applications (2020) (5)
Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects (2020) (5)
Fast and Accurate Modelling of Large TSV Arrays in 3D-ICs Using a 3D Circuit Model Validated Against Full-Wave FEM Simulations and RF Measurements (2016) (5)
Analysis of 3D interconnect performance: Effect of the Si substrate resistivity (2014) (5)
Signal propagation in high-speed MCM circuits (1995) (5)
A new method of synthesizing high-Tc superconducting materials (1989) (5)
Material technology for 2.5D/3D package (2015) (5)
Cu-Cu hybrid bonding as option for 3D IC stacking (2012) (5)
Study of the influence of material properties and geometric parameters on warpage for Fan-Out Wafer Level Packaging (2018) (5)
Thermal fatigue analysis of the flip chip assembly on the polymer stud grid array (PSGA) package (1999) (5)
Fine Pitch Rapid Heat Self-Aligned Assembly and Liquid-Mediated Direct Bonding of Si Chips (2016) (5)
Design and Technology Solutions for 3D Integrated High Performance Systems (2021) (5)
MCM-D for high speed digital applications-electrical modelling and performance evaluation (1997) (5)
Study of 3D process impact on advanced CMOS devices (2013) (4)
Temporary bonding for High-topography Applications: Spin-on Material Versus Dry Film (2014) (4)
Direct Bonding of low Temperature Heterogeneous Dielectrics (2019) (4)
Modeling and characterization of the polymer stud grid array (PSGA) package: electrical, thermal and thermo-mechanical qualification (2003) (4)
Co-Sn intermetallic compoundsfor potential integration in 3D interconnects (2014) (4)
Technology optimization for high bandwidth density applications on 3D interposer (2016) (4)
HIGH DENSITY AND HIGH BANDWIDTH CHIP-TO-CHIP CONNECTIONS WITH 20μm PITCH FLIP-CHIP ON FAN-OUT WAFER LEVEL PACKAGE (2018) (4)
High TC superconducting thick-films : Process conditions and characterisation of powders and films (1988) (4)
Performance and Reliability Impact of Copper Plasticity in Backside TSV-Last Fabrication Process (2016) (4)
3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes (2020) (4)
In-tier diagnosis of power domains in 3D TSV ICs (2012) (4)
Advances in Temporary Carrier Technology for High-Density Fan-Out Device Build-up (2019) (4)
Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions (2010) (4)
System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs (2020) (4)
Bonding on Cu: a new stress evaluation approach by Raman spectroscopy (2002) (4)
Thermal fatigue reliability analysis of redistributed flip chip assemblies (1998) (4)
Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking (2013) (4)
Fine Pitch Micro-Bump Interconnections for Advanced 3D Chip Stacking (2011) (4)
Dual Frequency Wide Band Cusp Antenna Fed by Coplanar Waveguide (1998) (4)
Generic thermal modeling study of the impact of 3D -interposer material and thickness options on the thermal performance and die-to-die thermal coupling (2014) (4)
Impact of ELD layers in mechanical properties of microbumps for 3D stacking (2016) (4)
Impact of wafer thinning on front-end reliability for 3D integration (2016) (4)
Accurate RF electrical characterisation of CSPs using MCM-D thin film technology (2002) (4)
3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding (2020) (4)
Temporary wafer bonding defect impact assessment on substrate thinning: Process enhancement through systematic defect track down (2012) (4)
Broadband coplanar couplers in multilayer thin film MCM-D technology (1999) (4)
Practical Evaluation of a Cu Thick Film Multilayer System and Wire Bonding on Cu Conductors (1985) (4)
3D stacking using ultra thin dies (2012) (4)
Demonstration of a novel low cost single material temporary bond solution for high topography substrates based on a mechanical wafer debonding and innovative adhesive removal (2015) (4)
Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes (2015) (4)
Ultra thin die embedding technology with 20μm-pitch interconnection (2010) (4)
Interconnect and Packaging Technologies for Realizing Miniaturized Smart Devices (2006) (4)
A Novel Intermetallic Compound Insertion Bonding to Improve Throughput for Sequential 3-D Stacking (2020) (4)
Fat damascene wires for high bandwidth routing in silicon interposer (2012) (4)
The Increasing Role of Polymers in Advanced Packaging - From Stress Buffer Layers to Wafer Level Underfills and Beyond (2017) (4)
Multimodal characterization of planar microwave structures (2004) (4)
A Highly Reliable 1×5μm Via-last TSV Module (2018) (4)
The Growing Application Field of Laser Debonding: From Advanced Packaging to Future Nanoelectronics (2019) (4)
Characterization and FE analysis on the shear test of electronic materials (2004) (4)
Edge Trimming Induced Defects on Direct Bonded Wafers (2018) (4)
Thermo-mechanical design of a generic 0-level MEMS package using chip capping and Through Silicon Via's (2010) (4)
Characterisation, Modelling and Design of Bond-Wire Interconnects for Chip-Package Co-Design (2003) (4)
3D-SoC integration utilizing high accuracy wafer level bonding (2016) (4)
Thermo-mechanical analysis of flip chip on substrate bumps - assemblies (1997) (4)
In‐situ Electrical Measurements on Thick Film Dielectrics (1993) (4)
Galerkin versus razor-blade testing in the method of moments formulation for multiconductor transmission lines (2000) (4)
Realisation of a DECT VCO circuit with MCM-D technology (2000) (4)
Non-destructive acoustic metrology and void detection in 3×50μm TSV (2016) (4)
High‐Q RF inductors on 20 Ω.cm silicon realized through wafer‐level packaging techniques (2003) (4)
Thermal management of electronic systems II : proceedings of Eurotherm Seminar 45, 20-22 September 1995, Leuven, Belgium (1997) (4)
TSV process-induced MOS reliability degradation (2018) (4)
A Modified Electromigration Test Structure for Flip Chip Interconnections (2006) (4)
Via Last using Polymer Liners and their Reliability (2010) (3)
Investigation of Co Thin Film as Buffer Layer Applied to Cu/Sn Eutectic Bonding and UBM With Sn, SnCu, and SAC Solders Joints (2017) (3)
Pulsed DC Sputtered Aluminum Nitride: A Novel Approach To Control Stress And C-axis Orientation (2004) (3)
The Shear Test as Interface Characterization Tool Applied to the Si-BCB Interface (2009) (3)
Trends in packaging and high density interconnection (2000) (3)
Characterization of inorganic dielectric layers for low thermal budget wafer-to-wafer bonding (2017) (3)
Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers (2004) (3)
Growth rate of IMC in the binary sytems of Co/Sn and Cu/Sn (2017) (3)
Morphological characterization and mechanical behavior by dicing and thinning on direct bonded Si wafer (2020) (3)
Comparison of the RF electrical performance of the PSGA and the BGA package (2001) (3)
Direct Bonding Using Low Temperature SiCN Dielectrics (2022) (3)
Distributed circuit models for near-CSP interconnects (2002) (3)
Novell embedded microbump approach for die-to-die and wafer-to-wafer interconnects with variable microbump diameters and down to 5 um interconnect pitch scaling (2019) (3)
Process technology for the fabrication of a Chip-in-Wire style packaging (2008) (3)
Heat transfer and pressure drop correlations for direct on-chip microscale jet impingement cooling with alternating feeding and draining jets (2022) (3)
Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows (2015) (3)
Large area interposer lithography (2014) (3)
Thermal mismatch induced reliability issues for Cu filled through-silicon vias (2012) (3)
Performance analysis of a 10-Gbit/s digital switch on MCM (1996) (3)
Thermal, Mechanical and Reliability assessment of Hybrid bonded wafers, bonded at 2.5μm pitch (2020) (3)
The antenna: Cornerstone for system-on-package integration of future wireless systems (2002) (3)
Trends in wafer-level packaging of MEMS (2003) (3)
Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning (2016) (3)
An Efficient Bump Pad Design to Mitigate the Flip Chip Package Induced Stress (2015) (3)
Novel Failure Analysis Techniques for 1.8 µm Pitch Wafer-to-Wafer Bonding (2018) (3)
Novel Temporary Bonding and Debonding Solutions Enabling an Ultrahigh Interonnect Density Fo-Wlp Structure Assembly with Quasi-Zero Die Shift (2019) (3)
Reliability of 3D package using wafer level underfill and low CTE epoxy mold compound materials (2014) (3)
Defect localization of metal interconnection lines in 3-dimensional through-silicon-via structures by differential scanning photocapacitance microscopy (2018) (3)
Study of wafer warpage for Fan-Out wafer level packaging: finite element modelling and experimental validation (2019) (3)
Demonstration of a collective hybrid die-to-wafer integration (2020) (3)
Effect of test structure on electromigration characteristics in 3D-TSV stacked devices (2014) (3)
Coplanar Versus Slotline Mode in Exciting CPW-FED Planar Antennas (1999) (3)
Direct Hybrid Bonding (2008) (3)
Lead Free Solder Joint Reliability Estimation by Finite Element Modelling Advantages , Challenges and Limitations (2004) (3)
Constant impedance scaling paradigm for scaling LC transmission lines (2006) (3)
Inductive Links for 3D Stacked Chip-to-Chip Communication (2019) (3)
ESD protection design in active-lite interposer for 2.5 and 3D systems-in-package (2015) (3)
Reliability study of liner/barrier/seed options for via-middle TSV's with 3 micron diameter and below (2015) (3)
Advances in Temporary Bonding and Release Technology for Ultrathin Substrate Processing and High-Density Fan-Out Device Build-up (2018) (3)
SAMs (self-assembled monolayers) passivation of cobalt microbumps for 3D stacking of Si chips (2016) (3)
The PSGA, a lead-free CSP for high performance & high reliable packaging (2001) (3)
Characterization of Impact of Vertical Stress on FinFETs (2019) (3)
Accurate broadband parameter extraction methodology for S-parameter measurements (2005) (3)
Through-silicon via technology for three-dimensional integrated circuit manufacturing (2012) (3)
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route (2019) (3)
Photosensitive polymer reliability for fine pitch RDL applications (2020) (3)
Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices (2017) (3)
Fine-pitch bonding technology with surface-planarized solder micro-bump/polymer hybrid for 3D integration (2021) (3)
Convolution Based Steady State Compact Thermal Model for 3D-Integrated Circuits: Methodology for Including the Thermal Impact of Die to Die Interconnections (2014) (3)
In-line metrology and inspection for process control during 3D stacking of IC's (2012) (3)
Efficient Link Architecture for On-Chip Serial links and Networks (2006) (3)
Buried Power Rails and Nano-Scale TSV: Technology Boosters for Backside Power Delivery Network and 3D Heterogeneous Integration (2022) (3)
Underfill material screening and process characterization for 3D stacking (2012) (3)
Electromigration: Investigation of heterogeneous systems (1993) (3)
RF Technologies and Systems (2009) (3)
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails (2022) (2)
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor (2022) (2)
On the Dielectric Material Properties for Thin Film Integrated RF and Microwave Applications (1999) (2)
RF SiP technologies enabling wireless modules (2011) (2)
Alternative Cu pillar bumps design to reduce thermomechanical stress induced during flip chip assembly (2017) (2)
Thermal Analysis of Polymer 3D Printed Jet Impingement Coolers for High Performance 2.5D Si Interposer Packages (2019) (2)
Etch process modules development and integration in 3D-SOC applications (2018) (2)
On the feasibility of die-to-wafer inorganic dielectric bonding (2016) (2)
Surface Treatment to Enable Low Temperature and Pressure Copper Direct Bonding (2016) (2)
Hermetically Sealed On-Chip Packaging of MEMS Devices (2000) (2)
Transient Thermal Characterization of the Polymer Stud Grid Array (2001) (2)
Design and Integration Technology for Miniature Medical Microsystems (2008) (2)
Protective Layer for Collective Die to Wafer Hybrid Bonding (2019) (2)
Advanced Dicing Technologies for Combination of Wafer to Wafer and Collective Die to Wafer Direct Bonding (2019) (2)
Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly (2018) (2)
A Quantitative Study of the Adhesion Between Copper, Barrier and Organic Low-K Materials (2000) (2)
2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms (2014) (2)
Acoustic modulation during laser debonding of collective hybrid bonded dies (2021) (2)
Introduction of a New Carrier System for Collective Die-to-Wafer Hybrid Bonding and Laser-Assisted Die Transfer (2020) (2)
On the use of bare-die field Programmable Devices in miniaturized systems (1999) (2)
A Simple and Efficient RF Technique for TSV Characterization (2017) (2)
A novel in-situ resistance measurement to extract IMC resistivity and kinetic parameter for CoSn 3D stacks (2017) (2)
Alternative patterning techniques enabling fine pitch interconnection on topography surfaces (2010) (2)
3D Heterogeneous Package Integration of Air/Magnetic Core Inductor: 89%-Effi- ciency Buck Converter with Backside Power Delivery Network (2020) (2)
Development and Evaluation of Photodefinable Wafer Level Underfill (2015) (2)
Picking large thinned dies with high topography on both sides (2014) (2)
Fine-pitch 3D system integration and advanced CMOS nodes: technology and system design perspective (2021) (2)
Physics of self-aligned assembly at room temperature (2018) (2)
CMOS-integrated sige MEMS: Application to micro-mirrors (2009) (2)
Edge trimming for wafer-to-wafer 3D integration (2016) (2)
Chip-MCM co-design of a 14 GHz LNA (2001) (2)
Advances in microwave (2)
Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices (2014) (2)
A step towards MCM design automation (1998) (2)
Verifying thermal/thermo-mechanical behavior of a 3D stack — challenges and solutions (2010) (2)
Through silicon via to FinFET noise coupling in 3-D integrated circuits (2015) (2)
Mixed assembly on PCB of wide variety components (MCM-D, SMDs, bare dies) using wire bonding and SMT (2002) (2)
A Novel Resistance Measurement Methodology for $In~Situ$ UBM/Solder Interfacial Reaction Monitoring (2020) (2)
Electrical performance of high speed digital systems on thin film MCM (1997) (2)
Anomalous ${C}$ – ${V}$ Inversion in TSVs: The Problem and Its Cure (2018) (2)
Analysis and Modeling of Power Grid Transmission lines (2006) (2)
Experimental study of the microstrip backfire antenna (1984) (2)
A Unique Temporary Bond Solution Based on a Polymeric Material Tacky at Room Temperature and Highly Thermally Resistant Application Extension from 3D-SIC to FO-WLP (2017) (2)
Electro-migration behavior of Pb-free Flip Chip Bumps (2006) (2)
MCM-D switching units for interconnection technology validation (1996) (2)
A novel structure of MOSFET array to measure ioff-ion with high accuracy and high density (2015) (2)
Transient analysis of lossy interconnections using TRANSPLUS (1993) (2)
Thinning, Via Reveal, and Backside Processing – Overview (2014) (2)
Thermal Modelling of the Polymer Stud Grid Array (PSGA) Packages (1997) (2)
A study on substrate noise coupling among TSVs in 3D chip stack (2018) (2)
Electrical characterisation of BGA package for RF applications (2002) (2)
Thiol‐Based Self‐Assembled Monolayers (SAMs) as an Alternative Surface Finish for 3D Cu Microbumps (2015) (2)
Unipolar and Bipolar Resonant Tunneling Components (1997) (2)
Electromigration, fuse and thermo-mechanical performance of solder bump versus Cu pillar flip chip assemblies (2011) (2)
In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers (2017) (2)
Convolution based compact thermal model application to the evaluation of the thermal impact of die to die interface including interconnections (2014) (2)
Demonstration of a collective hybrid die-to-wafer integration using glass carrier (2021) (2)
Packaging Material Evaluation for 2.5D/3D TSV Application (2016) (2)
An in-situ resistance measurement to extract IMC resistivity and kinetic parameter of alternative metallurgies for 3D stacking (2018) (2)
Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node (2021) (2)
Packaging for MEMS and MST devices : The indent reflow sealing method (2000) (2)
Thin film tunnels versus air-bridges in coplanar waveguide discontinuities (1998) (2)
TCB optimization for stacking large thinned dies with 40 and 20 μm pitch microbumps (2018) (2)
Semi-analytical model for calculation of induced strains in solder joints of underfilled flip chip assemblies (2002) (2)
Wireless Sensor Systems – The e‐CUBES Project (2008) (2)
Characterization of Silicon Carbon Nitride for Low Temperature Wafer-to-Wafer Direct Bonding (2020) (2)
Room temperature and zero pressure high quality oxide direct bonding for 3D self-aligned assembly (2014) (2)
3D Integration Technologies at IMEC (2008) (2)
3D Wafer Level Packaging: Processes and Materials for Trough Silicon Vias & Thin Die Embedding (2008) (2)
A High-Bandwidth Fine-Pitch 2.57Tbps/mm In-package Communication Link Achieving 48fJ/bit/mm Efficiency (2019) (2)
Power from Below: Buried Interconnects Will Help Save Moore's Law (2021) (2)
Chip-MCM Co-design of a 14 GHz low noise amplifier using the MCM-D design library (2001) (2)
3D Interconnect technology for space applications (2005) (2)
Wafer Level Package Integrated Functions (2004) (1)
A system level approach to a structured MCM design methodology (1998) (1)
Semi-additive Cu-polymer RDL process for interposers applications (2014) (1)
Influence of Composition of SiCN Film for Surface Activated Bonding (2018) (1)
Influence Of Solder Joint Shape On The Thermo-Mechanical Reliability Of CSP's (2004) (1)
A broad band loss model for MCM interconnections (1993) (1)
Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding (2021) (1)
Insights into Scaled Logic Devices Connected from Both Wafer Sides (2022) (1)
Cost-effective RF interposer platform on low-resistivity Si enabling heterogeneous integration opportunities for beyond 5G (2022) (1)
Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network (2022) (1)
The Polymer Stud Grid Array (PSGA TM) Package: Test and Electrical Characterisation for RF Applications (2001) (1)
Metallurgies evaluation (Sn vs. SnCu0.7% vs. SnAg) for 3D bumping and stacking (2014) (1)
Carrier Systems for Collective Die-to-Wafer Bonding (2022) (1)
3D stacking using bump-less process for sub 10 µm pitches (2016) (1)
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module (2016) (1)
ESD protection design in smart interposer (2015) (1)
Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging (2022) (1)
Broadband permittivity characterization of polymers up to 110GHz using co-planar waveguides (2021) (1)
Thermal Management and Processing Optimization for 3D Multi-layer Stacked ICs (2019) (1)
Wafer thinning and back side processing to enable 3D stacking (2012) (1)
Wafer level packaging technology for low-loss on-chip transmission lines and inductors (2003) (1)
Simulation of Cu pad expansion in wafer-to-wafer Cu/SiCN hybrid bonding (2022) (1)
Residual thermomechanical stresses in ultrathin chip stack technology (2000) (1)
Reliability Study of Polymers Used in Sub-4-μm Pitch RDL Applications (2021) (1)
3D Stacking Heterogeneous Integration for Devices and Modules (2012) (1)
3D stacking cobalt and nickel microbumps and kinetics of corresponding IMCs at low temperatures (2017) (1)
Cobalt-Tin Intermetallic Compounds as Alternative Surface Finish for Low Temperature Die-to-Wafer Solder Stacking (2021) (1)
Thermal Performance Comparison of Advanced 3D Packaging Concepts for Logic and Memory Integration in Mobile Cooling Conditions (2018) (1)
Impact of backside process on high aspect ratio via-middle Cu through silicon via reliability (2017) (1)
Stress and bowing engineering in passive silicon interposer (2015) (1)
Thermal and Thermo-Mechanical Evaluation of a ‘Chip in Moulded Interconnect Device’ (1997) (1)
Stress mitigation of 3D-stacking/packaging induced stresses (2018) (1)
A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring (2014) (1)
Photosensitive insulation coating for a copper redistribution layer process (2014) (1)
Process development to enable die sorting and 3D IC stacking (2012) (1)
System Optimization: High-Frequency Buck Converter With 3-D In-Package Air-Core Inductor (2021) (1)
Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism (2022) (1)
Recent advances in system integration and MEMS packaging (2005) (1)
Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy (2021) (1)
High-Q Inductors for Realization of Low Insertion Loss Baluns and Couplers Integrated in Thin Film Multilayer MCM-D Technology for Wireless Applications (2000) (1)
Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via (2017) (1)
Extreme Thinned-Wafer Bonding Using Low Temperature Curable Polyimide for Advanced Wafer Level Integrations (2018) (1)
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects (2017) (1)
SAMs (self-assembled monolayers) passivation of Cobalt microbumps for 3D applications (2015) (1)
Convolution-Based Fast Thermal Model for 3-D-ICs: Transient Experimental Validation (2017) (1)
Using mass metrology for process monitoring and control during 3 D stacking of IC ’ s (2012) (1)
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node (2022) (1)
Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips (2020) (1)
RF characterization of mold compound materials and high-$Q$ integrated passives using fan-out wafer-level packaging technology (2019) (1)
Low Warpage Wafer Level Transfer Molding Post 3D Die to Wafer Assembly (2016) (1)
FCOB: packaging issues for RF-MEMS applications and reliability study (2005) (1)
Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking (2022) (1)
Time domain performance of leadless CSPs extracted from scattering parameter measurements and circuit models (2003) (1)
Backside Power Delivery with a Direct 14:1/19:1 High-Ratio Point-of-Load Power Converter for Servers and Datacenters (2021) (1)
Defect learning methodology applied to microbump process at 20μm pitch and below (2018) (1)
NOZZLE ARRAY SCALING EFFECTS ON THE THERMAL/HYDRAULIC PERFORMANCE OF LIQUID JET IMPINGEMENT COOLERS FOR HIGH PERFORMANCE ELECTRONIC APPLICATIONS (2018) (1)
Thermal Analysis of a 3D Flip-chip Fan-out Wafer Level Package (fcFOWLP) for High Bandwidth 3D Integration (2019) (1)
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer (2016) (1)
Constant impedance scaling paradigm for interconnect synthesis (2006) (1)
Non-destructive In-line IMC Thickness Measurement Using Acoustic Metrology for 3D Stacking (2019) (1)
Integrated magnetic cores in FOWLP and their applications (2020) (1)
3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers (2012) (1)
Process development and characterization of 3D multi-die stacking (2020) (1)
Liquid mediated direct bonding and bond propagation (2016) (1)
Small Pitch Micro-Bumping and Experimental Investigation for Under Filling 3D Stacking (2012) (1)
Evaluation of copper thick film for high frequency digital interconnection (1988) (1)
Metrology and inspection rquirements for 3D stacking of ICs (2012) (0)
What’s in Space – Exploration and Improvement of Line/Space Defect Inspection of Fine-Pitch Redistribution Layer for Fan-Out Wafer Level Packaging (2019) (0)
Multi-tier $\mathrm{N}=4$ Binary Stacking, combining Face-to-Face and Back-to-Back Hybrid Wafer-to-Wafer Bonding Technology (2021) (0)
Adhesion study between materials for integration of copper and inorganic low-k dielectrics (2001) (0)
Chip ultra-thinning and embedding technology for autonomous sensors array applications (2009) (0)
Design and Characterization of CPW Feedthroughs in Multilayer Thin Film (2001) (0)
Method for adjusting and for bonding of parts and a component made of aligned and bonded parts (2008) (0)
A method for producing a laminated board (2000) (0)
On Thin Film MCM-D Interconnects (1998) (0)
A novel iso-thermal intermetallic compound insertion bonding approach to improve throughput for 3D die to wafer stacking (2020) (0)
Cost-performance optimization of fine-pitch W2W bonding: functional system partitioning with heterogeneous FEOL/BEOL configurations (2020) (0)
Package level thermal analysis of backside power delivery network (BS-PDN) configurations (2022) (0)
Enabling pre-assembly process of 3D wafers with high topography at the backside (2015) (0)
High spatial resolution measurements of thermo-mechanical stress effects in flip-chip packages (2019) (0)
Characterization of Optical End-Point Detection for Via Reveal Processing (2018) (0)
A method for aligning and bonding semiconductor chips to carrier wafer (Patent) (2016) (0)
Ultrafine Pitch 3D Stacked Integrated Circuits: Technology, Design Enablement, and Application (2019) (0)
Road through the interconnect red brick wall (2003) (0)
Thermal analysis of 3D functional partitioning for high-performance systems (2021) (0)
Process Complexity and Cost Considerations of Multi-Layer Die Stacks (2019) (0)
Thermo-compression flip chip bonding using gold ball bumps for RF and MEMS application (2004) (0)
Novel planar antenna arrays in MCM-D technology (1999) (0)
A method for transfer and stacking of semiconductor components (2001) (0)
Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits (2014) (0)
Vapor deposited thin organic–inorganic capping layers preventing copper line oxidation in polymer-based RDL technologies (2022) (0)
Confined IMCs for low temperature and high throughput D2W bonding (2022) (0)
A multi-layer thin-film MCM-D QPSK modulator for VSAT applications (2001) (0)
Investigating moisture diffusion in Mold Compounds (MCs) for Fan-Out-Wafer-Level-Packaging (FOWLP) (2022) (0)
Method and apparatus for measuring the thermal impedance of integrated semiconductor components (1995) (0)
Origin of Voids at the SiO2/SiO2 and SiCN/SiCN Bonding Interface Using Positron Annihilation Spectroscopy and Electron Spin Resonance (2023) (0)
Ensemble grille a bossages polymeres (1995) (0)
Tutorial T7A: Advanced IC Packaging (2007) (0)
Method for aligning micro-electronic components (US Application no. 14/576637 - Patent Publ. no. US20150179605 A1) (2015) (0)
Packaging approach for nano CMOS wiring (2005) (0)
Shaping interconnect technology for an interconnected society (2010) (0)
Fault Isolation of Resistive/Open 3-D Wafer Bonding Interconnects by Thermal Laser Stimulation and Light-Induced Capacitance Alteration (2020) (0)
An optimized process for the production of advanced planar wire grid plates as detectors for high energy physics experiments (2001) (0)
Process and Material Requirements for Successful Heterogonous Passive Component Integration in RF System (2006) (0)
Efficient Backside Power Delivery for High-Performance Computing Systems (2022) (0)
Demonstrations of Wireless Autonomous Sensors for Aeronautical Applications (2010) (0)
Broadband Characterization of Polymers under Reliability Stresses and Impact of Capping Layer (2022) (0)
Area-Selective Electroless Deposition of Cu for Hybrid Bonding (2021) (0)
The electronic component module and process for its preparation (2002) (0)
Characterisation of IC Packages for RF Applications (2001) (0)
91.5%-Efficiency Fully Integrated Voltage Regulator with 86fF/μm2-High-Density 2.5D MIM Capacitor (2021) (0)
Modeling of Buck Converter with 3D Air-Core Inductor (2020) (0)
Trends in MEMS/MST packaging and system integration (2003) (0)
Chapter 3, Designing for interface reliability (2005) (0)
Area Optimized Thin Film Coupled Inductor Band Pass Filters with Integrated Baluns (2008) (0)
A study on IMC morphology and integration flow for low temperature and high throughput TCB down to $10\mu \mathrm{m}$ pitch microbumps (2021) (0)
Fundamental study of IMC grains at low anneal temperature (2022) (0)
Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs (2010) (0)
Void Formation Mechanism Related to Particles During Wafer-to-Wafer Direct Bonding (2022) (0)
Assembly Technology for Fine Pitch Bumps Using Photodefinable Wafer-Level Underfill (2017) (0)
Cost Comparison of Different TSV Implementation Options (2016) (0)
Electrochemical Deposition of Sn-Cu Alloys for Applications in 3D Stacking in Microelectronics Industry (2020) (0)
Handbook of 3D Integration: Design, Test, and Thermal Management, Volume 4 (2019) (0)
Investigation of Paramagnetic Defects in SiCN and SiCO-based Wafer Bonding (2020) (0)
Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration (2020) (0)
Integrated antennas in MCM-D: examples and new possibilities for integrated systems (1999) (0)
Performance prediction of printed lumped inductors on a multilayer medium (2000) (0)
Explicit finite element modelling of intermetallic layers (2005) (0)
From CMOS to microsystems: international collaboration with industry (2003) (0)
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails (2022) (0)
Evaluation of UBM oxidation through air exposure and heating and effectiveness of wet and plasma cleaning on solder joint formation during TCB (2020) (0)
Packaging and Assembly Challenges for 2.5D/3D Devices (2016) (0)
ELD NiB for microbumps passivation and wirebonding (2020) (0)
Advances in Photosensitive Polymer Based Damascene RDL Processes: Toward Submicrometer Pitches With More Metal Layers (2021) (0)
Fine pitch micro-bump Cu/Sn solid state diffusion bonding with and without surface planarization (2012) (0)
Investigation of the influence of UBM on lead free flip chip solder fatigue life by explicit finite element modeling of intermetallic layers (2005) (0)
Comparison of different interconnect technologies for high frequency applications (1989) (0)
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited) (2021) (0)
3DWaferLevelPackaging Approach TowardsCostEffective LowLossHighDensity 3DStacking (2006) (0)
Applications of plasma processes to microsystems (2006) (0)
External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options (2021) (0)
Design of test modules for the analysis of MCM interconnects (1996) (0)
Thermal management of future packaging systems: impact on design and requirements for passive/active cooling systems (2006) (0)
A novel method for characterization of Ultra Low Viscosity NCF layers using TCB for 3D Assembly (2020) (0)
Challenges and perspectives for millimeter and submillimeter wave applications (2003) (0)
Experimental thermal characterisation of electronic components by means of the submerged double jet impingement (SDJI) method (1997) (0)
Copper thick-film multilayer technology as a high frequency digital interconnection (1988) (0)
Cu-Cu insertion bonding technique using photosensitive polymer as WLUF (2014) (0)
Heterogeneous Integration of Passive Components for the Realization of RF-System-in-Packages (2008) (0)
3D Integration technology developments at IMEC (2007) (0)
Analysis of warpage of a flip-chip BGA package under thermal loading: Finite element modelling and experimental validation (2023) (0)
Impact of wafer thinning on ESD protection devices in 3D integrated systems (2016) (0)
Comparison of properties of thermo-compression bonded 3D stacks using a liquid and a dry-film wafer level underfills (2015) (0)
Process conditions anc characterization of high-Tc superconducting thick films (1989) (0)
Exploiting wiring hierarchy and system design to surpass the interconnect red brick wall (2002) (0)
Tbps/mm bandwidth for chip-to-chip communication using fine pitch damascene RDL (2020) (0)
Transmission line analysis of MCM interconnects (1993) (0)
Defect Identification in Bonding Surface Layers by Positron Annihilation Spectroscopy (2019) (0)
Simulation of Cu bulge-out by cyclic Cu surface diffusion FEM in Cu/SiCN hybrid bonding (2023) (0)
Probabilistic design approach for integrated passive devices in RF applications (2008) (0)
Grid matrix polymer projections. (1996) (0)
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper (2022) (0)
Accurate Extraction of Time domain performance through Windowless Transforms (2003) (0)
Measurement setup for coplanar fed antennas (1999) (0)
An alternative 3D packaging route through wafer reconstruction (2015) (0)
3D heterogeneous system integration: Application driver for 3D technology development (2011) (0)
(Why do we need) Wireless Heterogeneous Integration (anyway?) (2022) (0)
三次元積層LSIチップにおける基板ノイズの層間評価(3次元集積,低電圧/低消費電力技術,新デバイス・回路とその応用) (2012) (0)
DUALFREQUENCYWIDEBAND CUSPANTENNA FEDBY COPLANARWAVEGUIDE (1998) (0)
Prevention of thinned wafer deformation during thermocompression bonding and multi-die stacking supported by temporary bonding materials (2021) (0)
Parameter study for the reliability of underfilled flip chip and CSP assemblies (2002) (0)
IC-Package Interaction (2013) (0)
Low temperature zero-level packaging of MEMS (2004) (0)
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO (2022) (0)
Advances in system integration and MEMS packaging (2005) (0)
Analysis and Application of a Surface Admittance Operator for Combined Magnetic and Dielectric Contrast in Emerging Interconnect Topologies (2023) (0)
Handbook of 3D Integration: Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design, 4 (2019) (0)
Electromigration at gold–aluminium interfaces and in thin aluminium tracks (1992) (0)
Design and Technology Solutions for 3D Integrated High Performance Systems (2021) (0)
Extended global interconnect architecture for nano-CMOS technologies (2006) (0)
New approach to apply 1,2,3-benzotriazole as a capping layer on UBMs for 3D TCB stacking and investigation of oxidation protection and solder wetting (2019) (0)
RF-systems-in-a-package, RF-SIP (2005) (0)
A Novel Method for Characterization of Ultralow Viscosity NCF Layers Using TCB for 3D Assembly (2021) (0)
Factors involved in performance optimisation of GHz chip-package co-design (2004) (0)
Pre-bonding Characterization of SiCN Enabled Wafer Stacking (2019) (0)
Stacking Aspects in the View of Scaling. (2012) (0)
Analysis and optimization of circuit interconnect performance (1995) (0)
Improved Staggered Through Silicon Via Inductors for RF and Power Applications (2018) (0)
Advanced Technologies for In-Line and Post-Processed TSV Integration (2009) (0)
3D system integration research at IMEC (2015) (0)
The unique properties of SiCN as bonding material for hybrid bonding (2021) (0)
700nm pitch Cu/SiCN wafer-to-wafer hybrid bonding (2022) (0)
Advantage of In-situ over Ex-situ techniques as reliability tool: Aging kinetics of Imec's MCM-D discrete passives devices (2003) (0)
Use of Polymer Liners for 3D-WLP TSVs: Process, Reliability and Cost (2010) (0)
Challenges in BEOL design and materials coping with CPI stress issues for advanced packaging solutions (2013) (0)
Foundations for successful RF chip-package co-design: a packaging perspective (2002) (0)
Impact of the combination of stress buffer layer and wafer level underfill on 3D IC assembly using thermal compression bonding (2017) (0)
Analysis and design of two types of microwave baluns (2000) (0)
Polymeric hump-matrix-housing (1996) (0)
A multi-layer thin-film MCM-D modulator for VSAT applications (2001) (0)
Interconnect technologies for multi-chip modules: high frequency characterization and loss analysis (1992) (0)
Study on Process Induced out-of-plane deformation for Fan-Out Wafer Level Packaging (2020) (0)
MODELING, DESIGN AND FABRICATION OF A NOVEL ELECTROWETTING BASED IMPINGEMENT COOLER (2010) (0)
The kinetics of the early stages of electromigration and concurrent temperature induced processes in thin film metallisations studied by means of an in-situ high resolution resistometric technique (1999) (0)
Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method (2022) (0)
Thermal experimental and modeling analysis of high power 3D packages (2015) (0)
Low temperature SiCN as dielectric for hybrid bonding (2023) (0)
Fault Isolation Approaches for Nanoscale TSV Interconnects in 3D Heterogenous Integration (2021) (0)
Thermal Fatigue Reliability Optimisation of Flip Chip Assemblies (2000) (0)

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