Ernest S. Kuh
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Ernest S. Kuhengineering Degrees
Engineering
#788
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#1245
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Electrical Engineering
#160
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#187
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Applied Physics
#1771
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#1803
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Engineering
Ernest S. Kuh's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
Why Is Ernest S. Kuh Influential?
(Suggest an Edit or Addition)According to Wikipedia, Ernest Shiu-Jen Kuh was a Chinese-born American electrical engineer. He served as Dean of the College of Engineering of the University of California, Berkeley. Biography Kuh was born in Beijing on 2 October 1928 to Zone S. Keh and Tsai Chu. Kuh was the youngest son of six siblings; he also had a younger sister. His father was a Nationalist government official, and later worked for a bank. Ernest Kuh was raised in Shanghai and attended Nanyang Model High School before enrolling at Shanghai Jiao Tong University from 1945 to 1947 for electrical engineering.
Ernest S. Kuh's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Linear and nonlinear circuits (1987) (602)
- Basic Circuit Theory (1969) (583)
- Efficient Algorithms for Channel Routing (1982) (531)
- Transient simulation of lossy interconnects based on the recursive convolution formulation (1992) (248)
- Clock routing for high-performance ICs (1990) (230)
- The state-variable approach to network analysis (1965) (214)
- Module Placement Based on Resistive Network Optimization (1984) (192)
- Performance-Driven Placement of Cell Based IC's (1989) (166)
- Piecewise-Linear Theory of Nonlinear Networks (1972) (158)
- Passive multipoint moment matching model order reduction algorithm on multiport distributed interconnect networks (1999) (151)
- Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout (1987) (133)
- Solving nonlinear resistive networks using piecewise-linear analysis and simplicial subdivision (1977) (123)
- RITUAL: a performance driven placement algorithm for small cell ICs (1991) (122)
- PROUD: a sea-of-gates placement algorithm (1988) (120)
- One-dimensional logic gate assignment and interval graphs (1979) (106)
- Recent advances in VLSI layout (1990) (99)
- Routing Region Definition and Ordering Scheme for Building-Block Layout (1985) (98)
- Proud: a fast sea-of-gates placement algorithm (1988) (90)
- Sequence-pair based placement method for hard/soft/pre-placed modules (1998) (90)
- On optimum single row routing (1979) (88)
- Power and ground network topology optimization for cell based VLSIs (1992) (87)
- Glitter: A Gridless Variable-Width Channel Router (1986) (85)
- On projection-based algorithms for model-order reduction of interconnects (2002) (85)
- A spacing algorithm for performance enhancement and cross-talk reduction (1993) (81)
- The multilayer routing problem: Algorithms and necessary and sufficient conditions for the single-row, single-layer case (1976) (76)
- Theory of Linear Active Networks (1967) (76)
- RITUAL: a performance driven placement algorithm (1992) (74)
- A sparse matrix method for analysis of piecewise-linear resistive networks (1972) (74)
- Nonlinear circuit theory: Resistive networks (1971) (73)
- Fast simulation and sensitivity analysis of lossy transmission lines by the method of characteristics (1997) (72)
- Post global routing crosstalk risk estimation and reduction (1996) (71)
- Post global routing crosstalk synthesis (1997) (67)
- Performance-Driven Steiner Tree Algorithms for Global Routing (1993) (65)
- VLSI circuit layout : theory and design (1985) (65)
- Exact moment matching model of transmission lines and application to interconnect delay estimation (1995) (64)
- Transient simulation of lossy interconnect (1992) (64)
- Some results on existence and uniqueness of solutions of nonlinear networks (1971) (59)
- Delay and area optimization in standard-cell design (1990) (56)
- A unified approach to partitioning and placement (VLSI layout) (1991) (54)
- Design space exploration using the genetic algorithm (1996) (52)
- An Efficient Timing-Driven Global Routing Algorithm (1993) (49)
- Solving piecewise-linear equations for resistive networks (1976) (44)
- An algorithm for single-row routing with prescribed street congestions (1980) (42)
- Efficient and accurate eye diagram prediction for high speed signaling (2008) (40)
- An Efficient Single-Row Routing Algorithm (1984) (40)
- Quadratic Boolean Programming for Performance-Driven System Partitioning (1993) (38)
- TIGER: an efficient timing-driven global router for gate array and standard cell layout design (1997) (37)
- A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies (1996) (36)
- The bordered triangular matrix and minimum essential sets of a digraph (1974) (35)
- A fast algorithm for performance-driven placement (1990) (34)
- Performance-Oriented Fully Routable Dynamic Architecture for a Field (1993) (32)
- All approach to the two-dimensional placement problem in circuit layout (1978) (31)
- A Dynamic and Efficient Representation of Building-Block Layout (1987) (31)
- A General Matching Theory and Its Application to Tunnel Diode Amplifiers (1966) (31)
- Floorplanning with pin assignment (1990) (31)
- Floorplan sizing by linear programming approximation (2000) (31)
- Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation (2001) (30)
- Stepwise equivalent conductance circuit simulation technique (1993) (30)
- Principles of Circuit Synthesis (1959) (30)
- Performance-driven system partitioning on multi-chip modules (1992) (30)
- A unified approach to the via minimization problem (1989) (28)
- EXPLORER: an interactive floorplanner for design space exploration (1996) (28)
- Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's (1995) (28)
- Module placement for large chips based on sparse linear equations (1988) (26)
- Double-row planar routing and permutation layout (1982) (26)
- Hierarchical placement for macrocells: a 'meet in the middle' approach (1988) (25)
- Timing-driven placement for general cell layout (1990) (24)
- I/O pad assignment based on the circuit structure (1991) (24)
- SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits (1991) (23)
- The constrained via minimization problem for PCB and VLSI design (1988) (23)
- Design Theory of Optimum Negative-Resistance Amplifiers (1961) (22)
- Optimum Synthesis of Wide-Band Parametric Amplifiers and Converters (1961) (22)
- Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks (2000) (22)
- Performance-driven interconnect global routing (1996) (21)
- Nutcracker: An Efficient and Intelligent Channel Spacer (1987) (20)
- A new timing-driven multilayer MCM/IC routing algorithm (1997) (20)
- Sensitivity Invariants of Continuously Equivalent Networks (1968) (19)
- Multipoint multiport algorithm for passive reduced-order model of interconnect networks (1998) (19)
- Synthesis of Lumped Parameter Precision Delay Line (1957) (19)
- Post routing performance optimization via multi-link insertion and non-uniform wiresizing (1995) (18)
- Pade approximation applied to transient simulation of lossy coupled transmission lines (1992) (17)
- A sequential circuit test generation using threshold-value simulation (1988) (17)
- Via assignment problem in multilayer printed circuit board (1979) (17)
- FARM: an efficient feed-through pin assignment algorithm (1992) (16)
- Stability of Linear Time-Varying Networks-the State Space Approach (1965) (16)
- Transfer Function Synthesis of Active RC Networks (1960) (15)
- High performance on-chip differential signaling using passive compensation for global communication (2009) (15)
- On the Layering Problem of Multilayer PWB Wiring (1980) (14)
- Post routing performance optimization via tapered link insertion and wiresizing (1995) (14)
- Design methodology of high performance on-chip global interconnect using terminated transmission-line (2009) (14)
- Special Synthesis Techniques for Driving Point Impedance Functions (1955) (13)
- Circuit partitioning under capacity and I/O constraints (1994) (12)
- General channel-routing algorithm (1983) (12)
- Moment models of general transmission lines with application to interconnect analysis and optimization (1996) (12)
- Two-Stage Newton-Raphson Method for Transistor-Level Simulation (2007) (12)
- Moment models of general transmission lines with application to MCM interconnect analysis (1995) (11)
- An accurate time domain interconnect model of transmission line networks (1996) (11)
- A multiparameter sensitivity measure for linear systems (1971) (10)
- Multipoint moment matching model for multiport distributed interconnect networks (1998) (10)
- Coupled noise estimation for distributed RC interconnect model (1999) (9)
- Techniques for fast circuit simulation applied to power estimation of CMOS circuits (1995) (9)
- A Simulation-Based Method for Generating Tests for Sequential Circuits (1990) (9)
- Low power passive equalizer optimization using tritonic step response (2008) (9)
- Low Power Passive Equalizer Design for Computer Memory Links (2008) (9)
- Timing-driven system partitioning by constraints decoupling method (1993) (8)
- State Variables and Feedback Theory (1969) (8)
- Theory and Design of Wide-Band Parametric Converters (1962) (8)
- Maximum Gain Realization of an RC Ladder Network (1960) (8)
- Elementary Operations which Generate Network Matrices (1956) (8)
- Combining Technology Mapping With Layout (1997) (8)
- Geometric compaction of building-block layout (1989) (8)
- Estimating and optimizing RC interconnect delay during physical design (1990) (8)
- Pade approximation applied to lossy transmission line circuit simulation (1992) (8)
- The Chebyshev expansion based passive model for distributed interconnect networks (1999) (7)
- A performance-driven MCM router with special consideration of crosstalk reduction (1998) (7)
- Novel techniques for high performance field-programmable logic devices (1993) (7)
- Implementation of a parallel genetic algorithm for floorplan optimization on IBM SP2 (1997) (7)
- An unconditional stable general operator splitting method for transistor level transient analysis (2006) (7)
- Geometric approach to VLSI layout compaction (1990) (6)
- Synthesis of RC Grounded Two-Ports (1958) (6)
- Integer programming techniques for multiway system partitioning under timing and capacity constraints (1993) (6)
- Optimum synthesis of a class of multiple-loop feedback systems (1971) (6)
- BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING (1992) (6)
- Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Hierarchical Clustering (1997) (6)
- New efficient and accurate moment matching based model for crosstalk estimation in coupled RC trees (2001) (6)
- Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links (2011) (5)
- Professional Activities (1979) (5)
- A performance-driven IC/MCM placement algorithm featuring explicit design space exploration (1997) (5)
- Physical design: reminiscing and looking ahead (1997) (4)
- Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements (2001) (4)
- Simulation and sensitivity analysis of transmission line circuits by the characteristics method (1996) (4)
- Performance improvement of a genetic algorithm for floorplanning with parallel computing technology (1997) (4)
- On-chip bus signaling using passive compensation (2008) (4)
- New Algorithms For Two- and Three-Layer Channel Routin (1991) (4)
- A new general connectivity model and its applications to timing-driven Steiner tree routing (1998) (4)
- Insight versus Algorithms: A Leader's View (1971) (3)
- Regenerative Modes of Active Networks (1960) (3)
- Efficient transient simulation for transistor-level analysis (2005) (3)
- Transient simulation of lossy coupled transmission lines (1992) (3)
- Circuits with periodically-varying parameters (1965) (3)
- Accurate and simple time domain model of interconnects modeled as transmission line networks (1995) (2)
- Invertibility, reproducibility and decoupling of a class of nonlinear systems (1971) (2)
- An extended 1-D assignment problem: net assignment in gate matrix layout (1990) (2)
- The Stabilization of Digraphs of Variable Parameter Systems (1978) (2)
- A new performance-driven global routing algorithm for gate array (1993) (2)
- Circuit simulation for large interconnected IC networks (1993) (2)
- SWEC speeds VLSI simulation (1995) (2)
- SYMPHONY: a fast mixed signal simulator for BiMOS analog/digital circuits (1997) (2)
- Potential Analog Network Synthesis for Arbitrary Loss Functions (1953) (2)
- Compaction-based vlsi layout (1989) (2)
- MOLE-a sea-of-gates detailed router (1990) (2)
- A New Accurate and Efficient Timing Simulator (1992) (2)
- BOUNDS OF NATURAL FREQUENCIES OF LINEAR ACTIVE NETWORKS (1960) (1)
- Tiger: a timing-driven gate array and standard cell layout system (1995) (1)
- Editorial: Routing in Microelectronics (1983) (1)
- Basic Circuit Theory: Chapters 1 through 10 (1971) (1)
- Bear: a macrocell layout system for vlsi circuits (1988) (1)
- An array optimization algorithm for VLSI layout (1991) (1)
- sign Space Exploration (1996) (1)
- Passive model order reduction algorithrrl based on Chebyshev expansion of impulse response of interconnect networks (2000) (1)
- A new approach to routing of two-layer printed circuit board (1981) (0)
- Single-row routing and extensions (1979) (0)
- A Novel Approach to IC Performance (1990) (0)
- Commission 6: Progress in Radio Waves and Transmission of Information: 2. Information Theory, Circuit Theory, and Computer‐Aided Design (1969) (0)
- Analysis of the validity of the coefficient estimates and forecasting properties of the RDFOR (Regional Demand FORcasting) models: A summary report: Validation report (1982) (0)
- Two-stage newton–raphson method for transistor-level simulation (2007) (0)
- D. Minimum Cost Minimum Diameter A-tree Heuristic Iii. Minimum Diameter A-tree Algorithm for Pd-msr Problem A. Review of A-tree Algorithm Performance Driven Routing with Multiple Sources (1995) (0)
- Desig nMethodolog yo fHig hPerformanc eOn-Chi pGloba lInterconnect Using Terminated Transmission-Line (2009) (0)
- An IC/MCM Timing-Driven Placement Algorithm Featuring Explicit Design Space Exploration (2016) (0)
- SENSITIVITY OF AMPLIFIER INTERSTAGE NETWORKS TO CHANGES IN TERMINATING CAPACITIES (1957) (0)
- An unconditional stable general operator splitting method for transistor level (2006) (0)
- Circuit theory and interconnect analysis for DSM chip design (2000) (0)
- Recent Development in Interconnect Modeling (2000) (0)
- Module Placement Based on Resistive Net- Work Optimization. Ieee Transactions on 4.2 Normalizing the Weight Values (1997) (0)
- Inter American University of Puerto Rico Bayamon Campus School of Engineering Department of Electrical Engineering (1997) (0)
- A Graph Theoretical Approach to the Permutation Layout (Applied Combinatorial Theory and Algorithms) (1981) (0)
- Tance and Unit Wire Resistance. 3 (1993) (0)
- Professor Ernest Kuh's talk (2011) (0)
- ccurate Time omain Inter ode1 of Transmission Line Net (1996) (0)
- Multiparameter sensitivity in linear networks (1965) (0)
- BBL-2 USER`s Manual (1985) (0)
- Passive model order reduction algorithm for multipoint moment matching of multiport distributed interconnect networks (2017) (0)
- Physical Design Overview (2003) (0)
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What Schools Are Affiliated With Ernest S. Kuh?
Ernest S. Kuh is affiliated with the following schools:
