Fabrizio Lombardi

Fabrizio Lombardi's AcademicInfluence.com Rankings

Fabrizio Lombardi

Engineering

#3805

World Rank

#4932

Historical Rank

Applied Physics

#797

World Rank

#819

Historical Rank

Electrical Engineering

#900

World Rank

#973

Historical Rank

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Engineering

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Fabrizio Lombardi's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits (2011) (442)
New Metrics for the Reliability of Approximate and Probabilistic Adders (2013) (441)
Design and Analysis of Approximate Compressors for Multiplication (2015) (386)
A low-power, high-performance approximate multiplier with configurable partial error recovery (2014) (263)
Approximate XOR/XNOR-based adders for inexact computing (2013) (212)
Testing of quantum cellular automata (2004) (189)
Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing (2017) (166)
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits (2017) (166)
A novel CNTFET-based ternary logic gate design (2009) (156)
A Comparative Review and Evaluation of Approximate Adders (2015) (152)
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation (2016) (151)
Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation (2005) (148)
Defects and faults in quantum cellular automata at nano scale (2004) (145)
Protocol conformance testing using multiple UIO sequences (1989) (138)
Design of a Ternary Memory Cell Using CNTFETs (2012) (137)
A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation (2014) (134)
On the Repair of Redundant RAM's (1987) (120)
Modeling QCA defects at molecular-level in combinational circuits (2005) (117)
An approach for testing programmable/configurable field programmable gate arrays (1996) (115)
Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs (2014) (113)
Inexact designs for approximate low power addition by cell replacement (2016) (112)
Design of sequential circuits by quantum-dot cellular automata (2007) (108)
Testing configurable LUT-based FPGA's (1998) (107)
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA (2008) (106)
A novel design methodology to optimize the speed and power of the CNTFET circuits (2009) (103)
A line-based parallel memory for QCA implementation (2005) (102)
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement (1990) (102)
Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection (2010) (100)
Diagnosing Programmable Interconnect Systems for FPGAs (1996) (90)
A Serial Memory by Quantum-Dot Cellular Automata (QCA) (2008) (89)
Performance evaluation of CNFET-based logic gates (2009) (87)
Device Model for Ballistic CNFETs Using the First Conducting Band (2008) (84)
Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset (2012) (83)
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders (2015) (82)
A comparative evaluation of approximate multipliers (2016) (80)
On the defect tolerance of nano-scale two-dimensional crossbars (2004) (76)
Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications (2018) (75)
A new SRAM cell design using CNTFETs (2008) (73)
A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems (1995) (71)
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS (2011) (70)
HDLQ: A HDL environment for QCA design (2006) (69)
QCA Circuits for Robust Coplanar Crossing (2007) (68)
Transmission gate-based approximate adders for inexact computing (2015) (66)
On the diagnosis of programmable interconnect systems: Theory and application (1996) (63)
Defect characterization and tolerance of QCA sequential devices and circuits (2005) (62)
Design of a Hybrid Memory Cell Using Memristance and Ambipolarity (2013) (60)
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors (2011) (60)
Tile-based QCA design using majority-like logic primitives (2005) (58)
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability (2010) (56)
Approximate compressors for error-resilient multiplier design (2015) (55)
Approximate DCT Image Compression Using Inexact Computing (2018) (55)
Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation (2014) (53)
Clocking and Cell Placement for QCA (2006) (53)
Approaches for the repair of VLSI/WSI RRAMs by row/column deletion (1988) (52)
Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery (2019) (52)
A Stochastic Computational Multi-Layer Perceptron with Backward Propagation (2018) (51)
Soft-Error Hardening Designs of Nanoscale CMOS Latches (2009) (49)
Assessment of CNTFET based circuit performance and robustness to PVT variations (2009) (48)
Quantum cellular automata: new defects and faults for new devices (2004) (48)
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire (2007) (48)
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation (2004) (48)
A Retrospective and Prospective View of Approximate Computing [Point of View} (2020) (47)
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates (2009) (47)
A novel sort error hardened 10T SRAM cells for low voltage operation (2012) (46)
Design and evaluation of an approximate Wallace-Booth multiplier (2016) (45)
Defect characterization for scaling of QCA devices [quantum dot cellular automata ] (2004) (45)
VLSI algorithms, architectures, and implementation of a versatile GF(2/sup m/) processor (2000) (45)
Reconfiguration of VLSI arrays by covering (1989) (45)
A Survey of Stochastic Computing Neural Networks for Machine Learning Applications (2020) (45)
Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing (2015) (44)
A low power 8T SRAM cell design technique for CNFET (2008) (44)
Analysis of missing and additional cell defects in sequential quantum-dot cellular automata (2007) (43)
Synthesis of Tile Sets for DNA Self-Assembly (2008) (43)
Design and Analysis of Approximate Redundant Binary Multipliers (2019) (42)
On the Design of Approximate Restoring Dividers for Error-Tolerant Applications (2016) (40)
Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset (2014) (39)
Diagnosis of interconnects and FPICs using a structured walking-1 approach (1995) (38)
XOR-Based Low-Cost Reconfigurable PUFs for IoT Security (2019) (38)
Design and Analysis of Inexact Floating-Point Adders (2016) (36)
Reversible and Testable Circuits for Molecular QCA Design (2008) (36)
Testing Reversible 1D Arrays for Molecular QCA (2006) (35)
Partially Reversible Pipelined QCA Circuits: Combining Low Power With High Throughput (2011) (35)
A Design Approach for Compressor Based Approximate Multipliers (2015) (35)
Tile-based design of a serial memory in QCA (2005) (34)
An Overview of Nanoscale Devices and Circuits (2007) (34)
A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures (2015) (34)
A Highly-Stable Nanometer Memory for Low-Power Design (2008) (33)
A low leakage 9t sram cell for ultra-low power operation (2008) (33)
Analysis and measurement of fault coverage in a combined ATE and BIST environment (2004) (33)
A diagnosis method for interconnects in SRAM based FPGAs (1998) (32)
On an improved design approach for C-testable orthogonal iterative arrays (1988) (32)
Design and process variation analysis of CNTFET-based ternary memory cells (2016) (32)
Novel designs for thermally robust coplanar crossing in QCA (2006) (31)
Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers (2019) (31)
Evaluation and improvement of fault coverage of conformance testing by UIO sequences (1992) (31)
A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors (2015) (30)
Adaptive System-Level Diagnosis for Hypercube Multiprocessors (1996) (30)
Low-cost configurable ring oscillator PUF with improved uniqueness (2016) (30)
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits (2019) (29)
QCA memory with parallel read∕serial write: design and analysis (2006) (29)
A Modified Partial Product Generator for Redundant Binary Multipliers (2016) (28)
Detection of inter-port faults in multi-port static RAMs (2000) (28)
High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization (2021) (28)
An Approach for Detecting Multiple Faulty FPGA Logic Blocks (2000) (28)
A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation (2012) (28)
Defect Tolerance of QCA Tiles (2006) (28)
A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits (2011) (28)
On the evaluation of scaling of QCA devices in the presence of defects at manufacturing (2005) (27)
Fault Tolerant Schemes for QCA Systems (2008) (27)
A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect (2013) (27)
Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition (2019) (27)
On the design of a redundant programmable logic array (RPLA) (1987) (27)
A 32nm SRAM design for low power and high stability (2008) (27)
Fault tolerance of switch blocks and switch block arrays in FPGA (2005) (27)
A model for computing and energy dissipation of molecular QCA devices and circuits (2008) (27)
Design of a QCA memory with parallel read/serial write (2005) (27)
Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays (2016) (26)
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays (1995) (25)
Testing SRAM-Based Content Addressable Memories (2000) (25)
A XOR-tree based technique for constant testability of configurable FPGAs (1997) (24)
A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation (2019) (24)
Multiple fault detection in logic resources of FPGAs (1997) (23)
A memristor-based TCAM (Ternary Content Addressable Memory) cell (2014) (23)
A new diagnosis approach for short faults in interconnects (1995) (23)
Reliability and Criticality Analysis of Communication Networks by Stochastic Computation (2016) (23)
Detection of bridging faults in logic resources of configurable FPGAs using I/sub DDQ/ (1998) (23)
Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs (2007) (23)
Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC) (2017) (23)
Adaptive approximation in arithmetic circuits: A low-power unsigned divider design (2018) (23)
Markov models of fault-tolerant memory systems under SEU (2004) (23)
XOR gate based low-cost configurable RO PUF (2017) (23)
A row-based FPGA for single and multiple stuck-at fault detection (1995) (22)
A novel design of a memristor-based look-up table (LUT) for FPGA (2014) (22)
On the Constant Diagnosability of Baseline Interconnection Networks (1990) (22)
Low power 8T SRAM using 32nm independent gate FinFET technology (2008) (21)
Novel memory designs for QCA implementation (2005) (21)
Design, Evaluation and Application of Approximate High-Radix Dividers (2018) (21)
Application of arithmetic coding to compression of VLSI test data (2005) (20)
Modeling and analysis of fault tolerant multistage interconnection networks (2003) (20)
A memristor-based LUT for FPGAs (2014) (20)
Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation (2016) (20)
Energy Analysis of QCA Circuits for Reversible Computing (2006) (19)
Test time reduction in a manufacturing environment by combining BIST and ATE (2002) (19)
Design of majority logic based approximate arithmetic circuits (2017) (19)
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing (2019) (18)
Bridging fault detection in FPGA interconnects using IDDQ (1998) (18)
Macromodeling a phase change memory (PCM) cell by HSPICE (2012) (18)
Error-resilient test data compression using Tunstall codes (2004) (17)
Optimal spare utilization in repairable and reliable memory cores (2003) (17)
Inexact floating-point adder for dynamic image processing (2014) (17)
Detection and Location of Multiple Faults in Baseline Interconnection Networks (1992) (17)
Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition (2017) (17)
Design and Performance Evaluation of Approximate Floating-Point Multipliers (2016) (17)
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity (2017) (17)
Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM) (2015) (17)
An information-theoretic analysis of quantum-dot cellular automata for defect tolerance (2010) (17)
Concurrent error detection and fault location in an FFT architecture (1992) (16)
New SRAM Cell Design for Low Power and High Reliability Using 32nm Independent Gate FinFET Technology (2008) (16)
Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning (2020) (16)
Approximate Arithmetic Circuits: Design and Evaluation (2018) (16)
ATE-amenable test data compression with no cyclic scan registers (2003) (16)
FsmTest: Functional test generation for sequential circuits (1996) (15)
A memristor-based memory cell using ambipolar operation (2011) (15)
An energy-efficient stochastic computational deep belief network (2018) (15)
Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing (2014) (15)
Design of Majority Logic (ML) Based Approximate Full Adders (2018) (15)
Cell design and comparative evaluation of a novel 1T memristor-based memory (2012) (15)
Detection of defective media in disks (1993) (15)
Using data compression in automatic test equipment for system-on-chip testing (2004) (15)
A novel design technique for soft error hardening of Nanoscale CMOS memory (2009) (15)
Error Tolerance of DNA Self-Assembly by Monomer Concentration Control (2006) (14)
A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects (2011) (14)
Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation (2019) (14)
Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities (2020) (14)
Error Tolerance of DNA Self-Healing Assemblies by Puncturing (2007) (14)
Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer (2013) (14)
AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators (2021) (13)
I/sub DDQ/ testing of input/output resources of SRAM-based FPGAs (1999) (13)
On the modeling and analysis of jitter in ATE using Matlab (2005) (13)
Testing of quantum dot cellular automata based designs (2004) (13)
A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation (2019) (13)
Analysis of Error Masking and Restoring Properties of Sequential Circuits (2013) (13)
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications (2018) (13)
Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design (2018) (13)
An Efficient and Symbolic Model for Charge Densities in Ballistic Carbon Nanotube FETs (2006) (13)
Design of Approximate Logarithmic Multipliers (2017) (13)
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels (2008) (13)
Analysis and evaluation of multisite testing for VLSI (2005) (13)
Matrix multiplication by an inexact systolic array (2015) (13)
On the Computational Complexity of Tile Set Synthesis for DNA Self-Assembly (2009) (12)
Protocol Conformance Testing by Discriminating UIO Sequences (1991) (12)
ORTHOGONAL MAPPING: A RECONFIGURATION STRATEGY FOR FAULT TOLERANT VLSI/WSI 2-D ARRAYS+ (1989) (12)
Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs (2016) (12)
Modeling Undeposited CNTs for CNTFET Operation (2011) (12)
Design and evaluation of two MTJ-based content addressable non-volatile memory cells (2013) (12)
Routability and fault tolerance of FPGA interconnect architectures (2004) (12)
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs (2012) (12)
Sequential diagnosis of processor array systems (2004) (12)
Physical/biochemical inspired computing models for reliable nano-technology systems (2008) (12)
Reliability Evaluation of Repairable/Reconfigurable FPGAs (2006) (12)
Design and Implementation of an Approximate Softmax Layer for Deep Neural Networks (2020) (12)
Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers (2022) (12)
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays (1998) (12)
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes (2017) (12)
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories (2016) (12)
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation (2004) (12)
Protocol Conformance Testing Using Unique Input/Output Sequences (1997) (12)
Testing and diagnosis of VLSI and ULSI (1988) (12)
An efficient multi-way algorithm for balanced partitioning of VLSI circuits (1997) (11)
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints (2019) (11)
Constant testability of combinational cellular tree structures (1992) (11)
A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes (2014) (11)
Guest Editors’ Introduction (2004) (11)
Modeling the dependability of N-modular redundancy on demand under malicious agreement (2001) (11)
A New Comprehensive Model of a Phase Change Memory (PCM) Cell (2014) (11)
Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment (2003) (11)
Scalable Application-Dependent Diagnosisof Interconnects of SRAM-Based FPGAs (2014) (11)
On the yield of compiler-based eSRAMs (2004) (11)
On a new class of C-testable systolic arrays (1989) (11)
Modelling and extracting parameters of organic solar cells (2010) (10)
Fault Detection and Design Complextity in C-Testable VLSI Arrays (1990) (10)
F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments (2013) (10)
Analysis and Evaluations of Reliability of Reconfigurable FPGAs (2008) (10)
A novel and improved design of a ternary CNTFET-based cell (2013) (10)
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits (2009) (10)
A memristor-based memory cell with no refresh (2014) (10)
Parallel testing of multi-port static random access memories for BIST (2001) (10)
Two Approximate Voting Schemes for Reliable Computing (2017) (10)
Fault-tolerant embedded systems (2001) (10)
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders (2018) (10)
Design and Comparative Evaluation of a PCM-Based CAM (Content Addressable Memory) Cell (2017) (10)
A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes (2016) (10)
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance (2020) (10)
Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems (2002) (9)
On Functional Testing of Array Processors (1988) (9)
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale (2005) (9)
Logic-in-Memory With a Nonvolatile Programmable Metallization Cell (2016) (9)
Design of defect tolerant tile-based QCA circuits (2008) (9)
Data dependent jitter (DDJ) characterization methodology (2005) (9)
Concurrent Error Detection of Binary and Nonbinary OLS Parallel Decoders (2014) (9)
Minimizing the number of programming steps for diagnosis of interconnect faults in FPGAs (1999) (9)
On the operational features and performance of a memristor-based cell for a LUT of an FPGA (2013) (9)
High throughput and low power dissipation in QCA pipelines using Bennett clocking (2010) (9)
Extending Non-Volatile Operation to DRAM Cells (2013) (9)
Analysis of repair algorithms for mirrored-disk systems (1997) (9)
Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing (2007) (9)
A Sweeping Line Approach to Interconnect Testing (1996) (9)
Testing of programmable logic devices (PLD) with faulty resources (1997) (8)
Balanced redundancy utilization in embedded memory cores for dependable systems (2002) (8)
Evaluating the Yield of Repairable SRAMs for ATE (2006) (8)
Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets (2007) (8)
A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM) (2015) (8)
Modelling a CNTFET with Undeposited CNT Defects (2010) (8)
A novel write-scheme for data integrity in memristor-based crossbar memories (2012) (8)
Graph Algorithms for Conformance Testing Using the Rural Chinese Postman Tour (1996) (8)
An algorithm for functional reconfiguration of fixed-size arrays (1988) (8)
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset (2011) (8)
Measuring the timing jitter of ATE in the frequency domain (2006) (8)
Time/Temperature Degradation of Solar Cells under the Single Diode Model (2010) (8)
Yield analysis of compiler-based arrays of embedded SRAMs (2003) (8)
DC-LSTM: Deep Compressed LSTM with Low Bit-Width and Structured Matrices (2020) (8)
Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC) (2019) (7)
A coloring approach to the structural diagnosis of interconnects (1996) (7)
Error tolerant DNA self-assembly by link-fracturing (2009) (7)
HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design (2014) (7)
Design of Approximate FFT with Bit-width Selection Algorithms (2018) (7)
Evaluation of error-resilience for reliable compression of test data (2005) (7)
On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ (2015) (7)
Introduction to the Special Section on High Performance Memory Systems (2001) (7)
Evaluation and improvement of fault coverage for verification and validation of protocols (1990) (7)
Evaluation, analysis, and enhancement of error resilience for reliable compression of VLSI test data (2005) (7)
Approximate Computing: From Circuits to Applications [Scanning the Issue] (2020) (7)
Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming (2014) (7)
Quality-effective repair of multichip module systems (2000) (7)
Compression of VLSI test data by arithmetic coding (2004) (7)
A system-level scheme for resistance drift tolerance of a multilevel phase change memory (2014) (7)
Novel control pattern generators for interconnect testing with boundary scan (1999) (7)
AxSA: On the Design of High-Performance and Power-Efficient Approximate Systolic Arrays for Matrix Multiplication (2020) (7)
Double diode modeling of time/temperature induced degradation of solar cells (2010) (7)
Robust HSPICE modeling of a single electron turnstile (2014) (7)
Error Detection/Correction in DNA Algorithmic Self-Assembly (2008) (7)
Array partitioning: a methodology for reconfigurability and reconfiguration problems (1988) (7)
An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network (2018) (7)
Diagnosing single faults for interconnects in SRAM based FPGAs (1999) (7)
Stochastic Dividers for Low Latency Neural Networks (2021) (7)
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits (2018) (7)
Operational fault detection and monitoring of a memristor-based LUT (2015) (7)
Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling (2007) (7)
Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP) (2019) (7)
Availability modelling of ring microcomputer systems (1982) (7)
Data compression for system-on-chip testing using ATE (2002) (7)
Reconfiguration of one-time programmable FPGAs with faulty logic resources (1999) (6)
A novel fault tolerant approach for SRAM-based FPGAs (1999) (6)
Hybrid multisite testing at manufacturing (2003) (6)
Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders (2019) (6)
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 (2009) (6)
On the Reliable Performance of Sequential Adders for Soft Computing (2011) (6)
Testing IP cores with pseudo exhaustive test sets (2001) (6)
Off-device fault tolerance for digital imaging devices (2004) (6)
Simulating faults of combinational IP core-based SOCs in a PLI environment (2005) (6)
Evaluation of heuristic techniques for test vector ordering (2004) (6)
A Single and Adjacent Symbol Error-Correcting Parallel Decoder for Reed–Solomon Codes (2015) (6)
Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects (2013) (6)
Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning (2021) (6)
A parallel approach for testing multi-port static random access memories (2001) (6)
A Selective Trigger Scan Architecture for VLSI Testing (2008) (6)
Modeling quality reduction of multichip module systems due to uneven fault-coverage and imperfect diagnosis (1996) (6)
An Integrated Environment for Design Verification of ATE Systems (2007) (6)
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection (2012) (6)
Probabilistic analysis of fault tolerance of FPGA switch block array (2004) (6)
A routing algorithm for harvesting multipipeline arrays with small intercell and pipeline delays (1990) (6)
A Technique for Reconfiguring Two Dimensional VLSI Arrays (1987) (6)
Profile-Based Output Error Compensation for Approximate Arithmetic Circuits (2020) (6)
Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders (2017) (6)
Testing layered interconnection networks (2004) (6)
Design of a Non-Volatile 7 T 1 R SRAM Cell for Instanton Operation (2014) (6)
Design for testability techniques for CMOS combinational gates (1991) (6)
Spare cutting approaches for repairing memories (1996) (6)
Guest Editors' Introduction: Clockless VLSI Systems (2003) (6)
Soft error masking latch for sub-threshold voltage operation (2012) (6)
Read-out schemes for a CNTFET-based crossbar memory (2010) (6)
Layout-driven detection of bridge faults in interconnects (1996) (6)
High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets (2021) (5)
Parallel Decodable Two-Level Unequal Burst Error Correcting Codes (2015) (5)
On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements (1993) (5)
Adaptive Filter Design Using Stochastic Circuits (2016) (5)
Modeling Open Defects in Nanometric Scale CMOS (2010) (5)
Simulation of reconfigurable memory core yield (2004) (5)
Reliability measurement of mass storage system for onboard instrumentation (2005) (5)
An approach for UIO generation for FSM verification and validation (1994) (5)
Approximate reliability of multi-state two-terminal networks by stochastic analysis (2017) (5)
Quality enhancement of reconfigurable multichip module systems by redundant utilization (2001) (5)
Healing assessment of tile sets for error tolerance in DNA self-assembly. (2008) (5)
Maximal diagnosis of interconnects of random access memories (1999) (5)
State of the Journal (2008) (5)
Timing requirement for reliable latch-based circuit design (2004) (5)
A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies (2008) (5)
Design of approximate Redundant Binary multipliers (2016) (5)
An Architecture and an Interconnection Scheme for Time-Sliced Buses (1987) (5)
Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications (2022) (5)
A Comparative Evaluation of Designs for Reliable Memory Systems (2005) (5)
Adaptive Fault Detection and Diagnosis of RAM Interconnects (1999) (5)
Robust self-assembly of interconnects by parallel DNA growth (2007) (5)
Invited Paper A C-testability approach for two dimensional iterative arrays† (1988) (5)
Approach for the reconfiguration of multipipeline arrays (1991) (5)
Minimizing the cost of repairing WSI memories (1989) (5)
Substrate Testing on a Multi-Site/Multi-Probe ATE (2008) (5)
A fully parallel approximate CORDIC design (2016) (5)
Timing Verification of QCA Memory Architectures (2006) (5)
On the testability of array structures for FFT computation (1990) (5)
Design Verification of FPGA Implementations (1999) (5)
Structural diagnosis of interconnects by coloring (1998) (5)
Two-step algorithms for maximal diagnosis of wiring interconnects (1999) (5)
Repairability/unrepairability detection technique for yield enhancement of VLSI memories with redundancy (1990) (5)
Estimating the manufacturing yield of compiler-based embedded SRAMs (2005) (5)
A hybrid memory cell using Single-Electron transfer (2011) (5)
Testing programmable interconnect systems: an algorithmic approach (2000) (5)
A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory (2021) (5)
Delay analysis of gate-adjusted CNTFETs for undeposited CNT defect-tolerance (2011) (4)
Novel approaches for fault detection in two-dimensional combinational arrays (2001) (4)
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1993) (4)
Testing a Nanocrossbar for Multiple Fault Detection (2013) (4)
Modeling magnetic quantum-dot cellular automata by HDL (2011) (4)
Reliability modeling and assurance of clockless wave pipeline (2004) (4)
Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects (2003) (4)
Hardening a memory cell for low power operation by gate leakage reduction (2012) (4)
Error-Tolerant Computation for Voting Classifiers With Multiple Classes (2020) (4)
Dependability under malicious agreement in N-modular redundancy-on-demand systems (2001) (4)
Yield evaluation methods of SRAM arrays: a comparative study (2004) (4)
Embedded Fault-Tolerant Systems (1998) (4)
FDSOI SRAM cells for low power design at 22nm technology node (2014) (4)
A Novel Hardened Design of a CMOS Memory Cell at 32nm (2009) (4)
An Adaptive System-Level Diagnosis Approach for Mesh Connected Multiprocessors (1993) (4)
Spare Line Borrowing Technique for Distributed Memory Cores in SoC (2005) (4)
High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes (2016) (4)
Analysis of stratified testing for multichip module systems (2002) (4)
Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation (1991) (4)
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance (2014) (4)
Welcome (2016) (4)
Estimation of total errors in software (1982) (4)
Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication (2019) (4)
A novel hybrid design of a memory cell using a memristor and ambipolar transistors (2011) (4)
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction (2014) (4)
On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells (2015) (4)
Reconfiguring one-time programmable FPGAs (1999) (4)
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction (2017) (4)
Checkpointing of Rectilinear Growth in DNA Self-Assembly (2008) (4)
Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement (1989) (4)
A novel scheme for concurrent error detection of OLS parallel decoders (2013) (4)
Error Tolerant DNA Self-Assembly Using ( $\hbox{2}k-\hbox{1}$)$\times$( $\hbox{2}k-\hbox{1}$) Snake Tile Sets (2008) (4)
Detecting latent sector faults in modern SCSI disks (1994) (4)
Diagnosis of interconnects using a structured walking-1 approach (1995) (4)
HSPICE macromodel of a PMA racetrack memory (2015) (3)
A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks (2007) (3)
Stratified testing of multichip module systems under uneven known-good-yield (1999) (3)
Analysis of Punctures in DNA Self-Assembly Under Forward Growth (2008) (3)
A New Method for Testing EEPLA's (1998) (3)
Multi-Site and Multi-Probe Substrate Testing on an ATE (2006) (3)
An approximate voting scheme for reliable computing (2015) (3)
Hardware-software Co-reliability in field reconfigurable multi-processor-memory systems (2002) (3)
Design of Dynamic Range Approximate Logarithmic Multipliers (2018) (3)
Fault detection in a tristate system environment (1998) (3)
Fault detection and diagnosis of interconnects of random access memories (1998) (3)
Fault tolerant memory design for HW/SW co-reliability in massively parallel computing systems (2003) (3)
Design and comparative evaluation of a hybrid Cache memory at architectural level (2016) (3)
Error Tolerant DNA Self-Assembly Using (2k − 1)×(2k − 1) Snake Tile Sets (2008) (3)
A data path approach for testing microprocessors with a fault bound: the MC68000 case (1992) (3)
Comparison-based diagnosis with faulty comparators (1986) (3)
Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly (2006) (3)
Error Tolerant DNA Self-Assembly Using ( ) ( ) Snake Tile Sets (2008) (3)
On the Delay Analysis of Defective CNTFETs with Undeposited CNTs (2011) (3)
A VPI-based combinational IP core module-based mixed level serial fault simulation and test generation methodology (2003) (3)
Modeling intermediate tests for fault-tolerant multichip module systems (1995) (3)
A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning (2021) (3)
Scheduling policies for fault tolerance in a VLSI processor (1994) (3)
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories (2020) (3)
Evaluation and Analysis of Heuristic Techniques for Vector Ordering of VLSI Test Sets (2008) (3)
Fault-tolerant rank order filtering for image enhancement (1999) (3)
On a Novel Self-Test Approach to Digital Testing (1987) (3)
On a tapered floating point system (1989) (3)
Information-Theoretic Modeling and Analysis of Stochastic Behaviors in Quantum-Dot Cellular Automata (2011) (3)
A technique for low power dynamic circuit design in 32nm double-gate FinFET technology (2008) (3)
Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog (2022) (3)
Reliability study of duplex-hybrid systems (1982) (3)
A scan-BIST environment for testing embedded memories (2002) (3)
On the reconfigurable operation of arrays with defects for image processing (1993) (3)
Low overhead DFT using CDFG by modifying controller (2007) (3)
C-testability of two-dimensional sequential arrays (1990) (3)
A Graph Model for Tile Sets in DNA Self-Assembly (2008) (3)
Fault tolerant clockless wave pipeline design (2004) (3)
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC) (2006) (3)
Fault tolerance of programmable switch blocks (2004) (3)
A Flow Graph Technique for DFT Controller Modification (2005) (3)
Locating faults in application-dependent interconnects of SRAM based FPGAs (2012) (3)
Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool (2018) (3)
Repair of redundant memories by reduced covering (1988) (3)
Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems (2007) (3)
Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits (2020) (3)
A compared evaluation of classes of reconfiguration strategies for fault tolerance in VLSI array processor architectures (1990) (3)
On the drift behaviors of a phase change memory (PCM) cell (2013) (3)
PROTOCOL CONFORMANCE TESTING (1997) (3)
On the Methods to Detect Sector Faults of a Disk Subsystem (1993) (3)
The evolution of the approach to Scientific Computing: a Survey (2014) (3)
Emulating Reconfigurable Arrays for Image Processing Using the MasPar Architecture (1993) (3)
Power Supply Network Aware Timing Analysis Using S-parameter In Nanometer Digital Circuits (2006) (3)
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction (2016) (3)
Software implemented fault tolerance: A methodology (1982) (2)
Random testing of multi-port static random access memories (2002) (2)
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor (1995) (2)
Approximate computing using frequency upscaling (2019) (2)
Reconfiguration of hexagonal arrays by diagonal deletion (1988) (2)
8Gb/s capacitive low power and high speed 4-PWAM transceiver design (2010) (2)
A PCM-based TCAM cell using NDR (2013) (2)
Counting by DNA Self-Assembly in the Presence of Rotated Tiles (2011) (2)
A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems (2016) (2)
A scan-BIST environment for testing embedded memories (2002) (2)
Testing Reversible One-Dimensional QCA Arrays for Multiple F (2007) (2)
A defect/error-tolerant nanosystem architecture for DSP (2009) (2)
Modeling a single electron turnstile in HSPICE (2012) (2)
Yield optimization of clockless wave pipeline with intra/inter-wave faults (2004) (2)
Constant testability for single fault detection in two-dimensional systolic array structures for matrix multiplication (1990) (2)
Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers (2022) (2)
Templated-Based Asynchronous Design for Testable and Fail-Safe Operation (2011) (2)
Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory (2015) (2)
DRAM Architecture and Testing (1999) (2)
Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment (2003) (2)
Balanced dual-stage repair for dependable embedded memory cores (2004) (2)
Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection (1990) (2)
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems (2016) (2)
Design and analysis of an approximate 2D convolver (2016) (2)
Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates (2010) (2)
On the design of two single event tolerant slave latches for scan delay testing (2012) (2)
Probabilistic balancing of fault coverage and test cost in combined built-in self-test/automated test equipment testing environment (2004) (2)
Modeling facet roughening errors in self-assembly by snake tile sets (2007) (2)
Analysis of series deviance in a parallel state transition diagram and applications to fault tolerant computing (1983) (2)
Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design (2021) (2)
Selective Neuron Re-Computation (SNRC) for Error-Tolerant Neural Networks (2021) (2)
Healing DNA Self-Assemblies Using Punctures (2009) (2)
Logic-in-Memory ( LiM ) with a Non-Volatile Programmable Metallization Cell ( PMC ) (2015) (2)
Frequency domain measurement of timing jitter in ATE (2004) (2)
Accurate communication models for task scheduling in multicomputers (1995) (2)
Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes (2019) (2)
Result-Based Re-computation for Error-Tolerant Classification by a Support Vector Machine (2020) (2)
On a Multiprocessor System with Dynamic Redundancy (1985) (2)
Multiple stuck-at faults detection in CMOS combinational gates (1991) (2)
Testing and evaluating the quality-level of stratified multichip module instrumentation (2000) (2)
On the design for testability of sequential circuits (1993) (2)
Combinatorial Optimization Problem in Designing DNA Self-Assembly Tile Sets (2008) (2)
Coded DNA Self-Assembly for Error Detection/Location (2009) (2)
Designs of PMC-based non-volatile memory circuits for data restoring (2016) (2)
Errors in DNA Self-Assembly by Synthesized Tile Sets (2009) (2)
A Structured Walking-1 Approach for the Diagnosis of Interconnects and FPICs (1996) (2)
Proceedings of the 20th symposium on Great lakes symposium on VLSI (2010) (2)
Concurrent Error Detection and Fault Location in an (1992) (2)
A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD (1999) (2)
A Probabilistic Error Model and Framework for Approximate Booth Multipliers (2018) (2)
Repair algorithms for mirrored disk systems (1995) (2)
Compression of partially specified test vectors in an ATE environment (2003) (2)
A probabilistic analysis of fault tolerance for switch block array in FPGAs (2005) (1)
Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models (2000) (1)
On the verification and validation of protocols with high fault coverage using UIO sequences (1992) (1)
Testing the configurability of dynamic FPGAs (2000) (1)
Parallel/series dependency and equivalence in generalized Markov's chains (1983) (1)
Good processor identification in two-dimensional grids (1999) (1)
AOI-based data-centric circuits for near-memory processing (2017) (1)
Diagnosis by comparison with faulty comparators (1986) (1)
Enhancing error resilience for reliable compression of VLSI test data (2005) (1)
Generating non-standard random distributions for discrete event simulation systems (1994) (1)
Clock Grid Simulation using Transient S-parameter Modeling (2006) (1)
On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment (2013) (1)
Fault-tolerant tree architecture with improved reconfiguration capabilities (1990) (1)
Reconfiguration in microprocessor schemes (1984) (1)
Reduced Precision Redundancy for Reliable Processing of Data (2019) (1)
Generalised modelling of centralised and distributed restructuring for different classes of faults: performance and profits and analysis (1983) (1)
Message from the New Editor-in-Chief (2007) (1)
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping (2000) (1)
Non-memoryless simulation approach for the evaluation of computer networks (1995) (1)
Editors' Note (2006) (1)
Scheme for periodical concurrent fault detection in parallel CRC circuits (2020) (1)
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits (2015) (1)
Message from the Editor-in-Chief (2017) (1)
Fault-tolerant sorting in SIMD hypercubes (1995) (1)
Analysis of Comparison-Based Diagnosable Systems Using Temporal Criteria (1988) (1)
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes (2019) (1)
Design and operational assessment of an intra-cell hybrid L2 cache (2017) (1)
Design, evaluation and application of approximate-truncated Booth multipliers (2020) (1)
Modeling Gross Damage in Tile-Based Nanomanufacturing by DNA Self-Assembly (2010) (1)
Hybrid designs for non-volatile embedded memory cells (2015) (1)
On the complexity of sequential testing in configurable FPGAs (1998) (1)
Investigation and design of a controller of an asynchronous system for fault-tolerant aircraft control using hybrid voting techniques (1984) (1)
IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices (2016) (1)
On the fault coverage of interconnect diagnosis (1997) (1)
New 4T-based DRAM cell designs (2014) (1)
An HDL model of magnetic quantum-dot cellular automata devices and circuits (2013) (1)
A design of a non-volatile PMC-based (programmable metallization cell) register file (2016) (1)
An adaptive system-level diagnosis approach for hypercube multiprocessors (1993) (1)
Test methodology for low power VLSI neural oscillator circuit (2004) (1)
Detection of multiple faults in CMOS circuits using a behavioral approach (1992) (1)
A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering (2018) (1)
Microcomputer real time software reliability and fault recovery (1982) (1)
A non-volatile low-power TCAM design using racetrack memories (2016) (1)
On the reduction of the programming cost of soft switches for reconfigurable two-dimensional arrays (1992) (1)
On the test and diagnosis of the perfect shuffle (2003) (1)
Two dimensional reordering of functional test data for compression by ATE (2005) (1)
Testing of inter-word coupling faults in word-oriented SRAMs (2004) (1)
Design for Testability Techniques for CMOS (1991) (1)
Test generation and scheduling for layout-based detection of bridge faults in interconnects (1999) (1)
Connectivity-based multichip module repair (2001) (1)
On the analysis of Reed Solomon coding for resilience to transient/permanent faults in highly reliable memories (2005) (1)
Algorithms for fault identification in a diagnosable multiprocessor system (1985) (1)
Fault-tolerant Sorting in Simd Hypercubes 1 (1)
On the complexity of switch programming in fault-tolerant configurable chips (2000) (1)
Monomer Control for Error Tolerance in DNA Self-Assembly (2008) (1)
An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior (2014) (1)
Interconnect diagnosis of bus-connected multi-RAM systems (1999) (1)
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells (2019) (1)
Tile-based QCA design (2007) (1)
A coding framework for DNA self-assembly (2009) (1)
Field Programmable Gate-Arrays (1998) (1)
New approaches for the reconfiguration of two-dimensional VLSI arrays using time-redundancy (1988) (1)
Statistical Characterization of Partially-Depleted SOI Gates (2006) (1)
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT (2016) (1)
A Defect Model for Metallic Carbon Nanotubes in Cell-based Logic Circuits (2006) (0)
A 13 T CMOS Memory Cell for Multiple Node Upset Hardening at 32 nm (2010) (0)
Associate Editor-in-Chief (also Editor) (2015) (0)
GENERATION OF CHARACTERIZING SEQUENCE (1997) (0)
Less-is-Better Protection (LBP) for memory errors in kNNs classifiers (2021) (0)
Rank Order Filtering on an Array with Faulty Processors (1994) (0)
Adaptive fault diagnosis for multiprocessor architectures (1995) (0)
Scan test of IP cores in an ATE environment (2004) (0)
Guest Editorial (2003) (0)
Editor-in-Chief's Note (2008) (0)
Hardening Approaches at Different Design Levels (2017) (0)
A performance analysis for single-walled metallic Carbon Nanotubes as global and intermediate on-chip interconnects (2007) (0)
A Serial Memory by (2008) (0)
Optimum coding framework for error detection in the self-assembly of the Sierpinski triangle. (2011) (0)
Old and New Approaches for the Repair of Redundant Memories (1988) (0)
A new method for testing EEPLAs (1998) (0)
Introduction to the Special Section on Nano Systems and Computing (2007) (0)
Design and Analysis of an Approximate 2 D Convolver (2016) (0)
2012 JETTA Reviewers (2013) (0)
A Universal Gate for Combinational Design of QCA Circuits (2009) (0)
Defect tolerance in VLSI systems (1997) (0)
Partially universal modules for high performance logic circuit design (2017) (0)
Invited paper. Algorithms for functional testing of digital systems (1987) (0)
A Tile-Based Error Model for Forward Growth of DNA Self-Assembly (2008) (0)
A Circuit Model for Fault Tolerance in the Reliable Assembly of Nano-systems (2008) (0)
Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems (2001) (0)
Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations (2006) (0)
Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays (1998) (0)
FFT architecture for WSI with concurrent error detection and fault location (1992) (0)
Proceedings : International Workshop on Memory Technology, Design, and Testing (1997) (0)
Editor's Note (2005) (0)
Message From the Editor-in-Chief (2016) (0)
Session details: CAD and Circuits I (2015) (0)
Test Solution Selection Using Multiple-Objective Decision Models and Analyses (2005) (0)
Implementing universal logic in QCA (2007) (0)
DETECTION OF THE EXTRA STATE FAULT (1997) (0)
Multiple Fault Detection in Nano Programmable Logic Arrays (2018) (0)
Commutative Approximate Adders: Analysis and Evaluation (2021) (0)
Computer-aided testing of switching and interconnect resources of fpgas (1999) (0)
Minimal area homogeneous logic circuits using nano-wires (2005) (0)
Using virtual links for reliable information retrieval across point-to-point networks (1997) (0)
A fault-counting algorithm for repairing redundant memories (1988) (0)
On the multiple fault detection of a nano crossbar (2012) (0)
Fault detection in a testable PLA with low overhead for production testing (1989) (0)
A low complexity approach for fault detection in C-testable orthogonal VLSI arrays (1988) (0)
An Efficient Framework for Scalable Defect Isolation in Large Scale Networks of DNA Self-Assembly (2009) (0)
Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems (2016) (0)
Guest Editors' Introduction: The State of the Art in Nanoscale CAD (2007) (0)
An Inexact Newton Method For Unconstrained Total Variation-Based Image Denoising by Approximate Addition (2022) (0)
Repairing VLSI/WSI redundant memories with minimum cost (1990) (0)
Robust Self-Assembly of Interconnects by Parallel (2008) (0)
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings (1993) (0)
Improving Error Resilience for Compressed Test Sets by Don't Care Assignment (2005) (0)
Functional testing and verification of array systems (1989) (0)
Balancing the Redundancy in Embedded Memory Cores for Dependable Systems (2005) (0)
Reliability analysis of fault tolerant pipeline ring networks (1983) (0)
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010 (2010) (0)
Guest Editors' Introduction: DRAM Architecture and Testing (1999) (0)
On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS (2011) (0)
Testing and testable designs for one-time programmable FPGAs (2000) (0)
Submesh Allocation in a Multitasking Distributed Shared Memory Multiprocessor (2001) (0)
A Gate Layout Technique for Area Reduction in Nano-Wire Circuit Design (2005) (0)
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates (2004) (0)
On a new approach for enhancing the fault coverage of conformance testing of protocols (1991) (0)
EIC Message (1994) (0)
A divide-and-conquer methodology for system-level diagnosis of processor arrays (1994) (0)
Security for Approximate Computing, Approximate Computing for Security (2020) (0)
RT level reliability enhancement by constructing dynamic TMRS (2007) (0)
Fault diagnosis for a multistage Banyan interconnection network (1985) (0)
DETECTABILITY OF TEST SEQUENCES (1997) (0)
Evaluating the data integrity of memory systems by configurable Markov models (2005) (0)
Detecting latent sector faults in SCSI disks (1993) (0)
Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependabilit (2013) (0)
On soft switch programming for reconfigurable array systems (1994) (0)
Multiple Error Detection in DNA Self-Assembly Using Coded Tiles (2010) (0)
A Novel Methodology for Functional Test Data Compression (2006) (0)
Scholars' Mine Scholars' Mine Testing Layered Interconnection Networks Testing Layered Interconnection Networks (2020) (0)
Evaluating the repair of system-on-chip (soc) using connectivity (2003) (0)
Performance evaluation of a deferred write technique as a recovery technique in client-server DBMS (1996) (0)
Self-testing approaches for VLSI arrays (1993) (0)
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT (2016) (0)
TESTABLE REDUNDANT PLAS FOR YIELD ENHANCEMENT (1989) (0)
Diagnosing Multiple Bridge Faults in Baseline Multistage Interconnection Networks (1995) (0)
Testing layered interconnection networks (2002) (0)
Modeling errors in synthesized tile sets for template manufacturing by DNA self-assembly (2011) (0)
Diagnosability for fault tolerant parallel systems (1985) (0)
Algorithms for functional testing of digital systems (1987) (0)
Matrix multiplication on the MasPar using distance insensitive communication schemes (1994) (0)
Interconnect testing of embedded memories at chip and system level (1999) (0)
Editor's Note (2007) (0)
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM) (2019) (0)
Design and Analysis of Inexact (2016) (0)
Fault detection in TFCMOS/DFCMOS combinational gates (1993) (0)
Conformance testing of time-dependent protocols (1996) (0)
An Analytical Error Model for Pattern Clipping in DNA Self-Assembly (2010) (0)
Design and Application of an Approximate 2-D Convolver with Error Compensation (2018) (0)
Welcome message from the chairs (2021) (0)
On the minimal test set for single fault location (1993) (0)
Session details: Networks (2004) (0)
A digital and wide power bandwidth H-field generator for automatic test equipment (2003) (0)
1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, November 4-6, 1992, Dallas, Texas : proceedings (1992) (0)
CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems (2018) (0)
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits (2017) (0)
Session details: Session 5A: Testing and Resilient Circuits (2008) (0)
A software testbed for the design and evaluation of distributed computer systems (1987) (0)
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012 (2012) (0)
Hardware/software co-reliability of configurable digital systems (2002) (0)
CONFORMANCE TESTING USING MUIO SEQUENCES (1997) (0)
Protection of Associative Memories Using Combined Tag and Data Parity (CTDP) (2021) (0)
BISTDesign forCCD basedDigital Imaging System (2007) (0)
Introduction to the Special Section on Nanocircuits and Systems (2009) (0)
CAPTIONALS: A computer aided testing environment for the verification and validation of communication protocols (1992) (0)
IMPROVEMENT OF FAULT COVERAGE (1997) (0)
Evaluating the impact of spike and flicker noise in phase change memories (2015) (0)
On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model (1997) (0)
Reconfiguration of Orthogonal Arrays by Front Deletion (1988) (0)
Repairability evaluation of embedded multiple region DRAMs (2002) (0)
Availability analysis of a N modules parallel system with common memory, central controller and distributed software (1982) (0)
Parallel growth and healing of DNA self-assembly for interconnects. (2010) (0)
CONFORMANCE TESTING BY ADAPTIVE UIOS (1997) (0)
A Novel Hardened Design of a Memory Cell in Nanoscale CMOS (0)
Analysis andSimulation ofJitter forHighSpeedChannels inVLSISystems (2007) (0)
On the imperfection of replacement (1983) (0)
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI: Foreword (2010) (0)
Fault detection and identification for reliable large-scale computing (1985) (0)
Dna self-assembly for efficient error-tolerant nanomanufacturing (2008) (0)
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders (2017) (0)
An Emulation Technique for Diagnosis and Failure Analysis of ATE (2006) (0)
Majority Logic-based Approximate Recording Adders for High-radix Booth Multipliers (2022) (0)
CMOS circuits for cell-level design of a racetrack memory (2015) (0)
Evaluating the Yield of Repairable (2006) (0)
A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates (2009) (0)
On the Multiple Bridge Fault Diagnosis of Baseline Multistage Interconnection Networks (1996) (0)
Design for Reuse Guest Editors' Introduction: Clockless Vlsi Systems (0)

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