Fujio Masuoka
#3,596
Most Influential Person Now
Japanese inventor
Fujio Masuoka's AcademicInfluence.com Rankings
Fujio Masuokaengineering Degrees
Engineering
#323
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#583
Historical Rank
Electrical Engineering
#2795
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#2938
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Applied Physics
#3333
World Rank
#3420
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Engineering
Fujio Masuoka's Degrees
- Bachelors Electrical Engineering Tohoku University
- Masters Electrical Engineering Tohoku University
- PhD Electrical Engineering Tohoku University
Why Is Fujio Masuoka Influential?
(Suggest an Edit or Addition)According to Wikipedia, is a Japanese engineer, who has worked for Toshiba and Tohoku University, and is currently chief technical officer of Unisantis Electronics. He is best known as the inventor of flash memory, including the development of both the NOR flash and NAND flash types in the 1980s. He also invented the first gate-all-around MOSFET transistor, an early non-planar 3D transistor, in 1988.
Fujio Masuoka's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Reliability issues of flash memory cells (1993) (209)
- 0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation (2001) (150)
- New ultra high density EPROM and flash EEPROM with NAND structure cell (1987) (150)
- Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's (1991) (145)
- A new flash E2PROM cell using triple polysilicon technology (1984) (106)
- High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs (1988) (92)
- Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits (1991) (88)
- A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory (1994) (75)
- Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA) (1992) (74)
- Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell (2001) (66)
- Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure (1976) (62)
- An accurate model of subbreakdown due to band-to-band tunneling and some applications (1988) (50)
- A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs (1989) (47)
- A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's (1995) (44)
- An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell (1989) (41)
- A reliable bi-polarity write/erase technology in flash EEPROMs (1990) (40)
- An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) (1997) (33)
- A 256K flash EEPROM using triple polysilicon technology (1985) (29)
- Homoepitaxial growth of non-polar ZnO (112¯0) films on off-angle ZnO substrates by MOCVD (2007) (29)
- An Experimental 16mb Cmos dram Chip with a 100mhz Serial Read/Write Mode (1988) (29)
- Applicability of ZnO single crystals for ultraviolet sensors (2006) (28)
- An analysis of the concave MOSFET (1978) (28)
- A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM (1990) (27)
- A new static memory cell based on the reverse base current effect of bipolar transistors (1989) (27)
- An on-chip 96.5% current efficiency CMOS linear regulator (2001) (26)
- An accurate model of subbreakdown due to band-to-band tunneling and its application (1988) (25)
- A 0.67μm^2 self-aligned shallow trench isolation cell (SA-STI cell) for 3V-only 256Mbit NAND EEP-ROMs (1994) (24)
- A quick intelligent program architecture for 3 V-only NAND-EEPROMs (1992) (24)
- Sub-half-micrometer concave MOSFET with double LDD structure (1992) (24)
- Comparison of non-polar ZnO (112¯0) films deposited on single crystal ZnO (112¯0) and sapphire (011¯2) substrates (2007) (24)
- A new write/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for flash memories (1998) (23)
- A 33-ns 64-Mb DRAM (1991) (23)
- A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution (1991) (22)
- An experimental DRAM with a NAND-structured cell (1993) (22)
- 2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM (2001) (20)
- An experimental 4 Mb CMOS EEPROM with a NAND structured cell (1989) (18)
- An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) (1997) (18)
- A quantitative analysis of stress-induced leakage currents and extraction of trap properties in 6.8 nm ultrathin silicon dioxide films (1999) (18)
- A 33ns 64Mb DRAM (1991) (18)
- A 10 Gb/s demultiplexer IC in 0.18 /spl mu/m CMOS using current mode logic with tolerance to the threshold voltage fluctuation (2000) (17)
- New three-dimensional memory array architecture for future ultrahigh-density DRAM (1999) (16)
- A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology (1987) (15)
- A new static memory cell based on reverse base current (RBC) effect of bipolar transistor (1988) (15)
- A Surrounding Gate Transistor (SGT) Gain Cell For Ultra High Density Drams (1993) (15)
- A 4-Mbit NAND-EEPROM with tight programmed Vt distribution (1990) (14)
- Stacked-Gate Avalanche-Injection Type MOS (SAMOS) Memory (1972) (13)
- Extended data retention characteristics after more than 10/sup 4/ write and erase cycles in EEPROMs (1990) (13)
- A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs (1994) (13)
- Process technologies for high density, high speed 16 megabit dynamic RAM (1987) (12)
- New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell (1988) (12)
- Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell (1990) (12)
- Photoluminescence properties of nitrogen-doped ZnO films deposited on ZnO single crystal substrates by the plasma-assisted reactive evaporation method (2007) (11)
- Reviews and Prospects of Non-Volatile Semiconductor Memories (1991) (11)
- Technology trend of flash-EEPROM-Can flash-EEPROM overcome DRAM? (1992) (11)
- A high-density NAND EEPROM with block-page programming for microcomputer applications (1990) (11)
- A 2/3-inch 2M-pixel STACK-CCD imager (1994) (11)
- Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering (2006) (9)
- A 17ns 64K CMOS RAM with a schmitt trigger sense amplifier (1985) (8)
- Analytical modeling of stress-induced leakage currents in 5.1–9.6-nm-thick silicon-dioxide films based on two-step inelastic trap-assisted tunneling (2000) (8)
- New write/erase operation technology for flash EEPROM cells to improve the read disturb characteristics (1997) (8)
- An 80 ns 1 Mbit MASK ROM with a new memory cell (1984) (7)
- Data Retention Characteristics of Flash Memory Cells after Write and Erase Cycling (Special Section on High Speed and High Density Multi Functional LSI Memories) (1994) (7)
- A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs (1990) (7)
- High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices (2004) (7)
- New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond (2004) (7)
- Double LDD concave (DLC) structure for sub-half micron MOSFET (1988) (6)
- A New Reverse Base Current (RBC) of the Bipolar Transistor Induced by Impact Ionization (1989) (6)
- The Analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the High Speed and Low Voltage Operation (1998) (6)
- A new cell structure with a spread source/drain (SSD) MOSFET and a cylindrical capacitor for 64-Mb DRAM's (1991) (6)
- Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cell (2003) (6)
- 12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices (2019) (6)
- A spread stacked capacitor (SSC) cell for 64 Mbit DRAMs (1989) (6)
- A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories (1994) (6)
- "A fully-decoded 2048-bit avalanche-injection type, electrically alterable ROM" (1972) (6)
- A 1Mb DRAM with a folded capacitor cell structure (1985) (6)
- A high density NAND EEPROM with block-page programming for microcomputer applications (1989) (6)
- Role of the external n-p-n base region on the switching speed of integrated injection logic (I/sup 2/L) (1977) (6)
- New three dimensional (3D) memory array architecture for future ultra high density DRAM (2000) (6)
- A New Architecture for High-Density High-Performance SGT nor Flash Memory (2008) (5)
- A new write/erase method for the reduction of the stress-induced leakage current based on the deactivation of step tunneling sites for flash memories (1994) (5)
- A 2/3-in 2 million pixel STACK-CCD HDTV imager (1995) (5)
- A Study of High-Performance NAND Structured EEPROMS (1992) (5)
- NAND-type DRAM-on-SGT (2005) (5)
- Device design guidelines for FC-SGT DRAM cells with high soft-error immunity (2005) (5)
- Spread source/drain (SSD) MOSFET using selective silicon growth for 64 Mbit DRAMs (1989) (5)
- An analysis of program and erase operation for FC-SGT flash memory cells (2000) (4)
- Influence of Retarding Hydrogen Diffusion in Boron Phosphosilicate Glass on Annealing Damage of Metal‐Oxide Semiconductor Transistors (1999) (4)
- Bit by bit erasable E2PROM with single transistor per bit (1981) (4)
- New design technology for EEPROM memory cells with 10 million write/erase cycling endurance (1989) (4)
- A High Performance Voltage Down Converter (VDC) Using New Flexible Control Technology of Driving Current (1998) (3)
- Characteristics of silicon n/sup +/-n/sup -/-n/sup +/ diode with sub-micrometer n/sup -/ region (1996) (3)
- Impact of the minority carrier outflow (MCO) effect on the /spl alpha/-particle-induced soft error of scaled DRAMs (1994) (3)
- New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell (1995) (3)
- A Staggered Nand Dram Array Architecture For A Gbit Scale Integration (1994) (3)
- A new high density full CMOS SRAM cell using polysilicon interconnection structure (1985) (3)
- A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process (1980) (2)
- An analysis of program and erase mechanisms for Floating Channel type Surrounding Gate Transistor Flash memory cells (2004) (2)
- A high-performance 1-Mbit dynamic RAM with a folded capacitor cell (1986) (2)
- Evaluation of the Voltage Down Converter (VDC) with Low Ratio of Consuming Current to Load Current in DC/AC Operation Mode (1998) (2)
- New NAND cell for ultra high density 5v-only EEPROMs. (1988) (2)
- Analysis of the NAND-type DRAM-on-SGT for high-density and low-voltage memory (2005) (2)
- The 2.4F2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM (2000) (2)
- Are you ready for next-generation dynamic RAM chips? (1990) (2)
- A novel tri-control gate surrounding gate transistor (TCG-SGT) nonvolatile memory cell for flash memory (2006) (2)
- An 80ns 1Mb ROM (1984) (2)
- The Stacked-SGT DRAM using 3D-building memory array technology (1999) (2)
- An Accurate Model of the C-V Characteristic due to Quantum Mechanical Effects for the Surrounding Gate Transistor (2005) (1)
- DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM (2018) (1)
- Influence of Silicon Wafer Loading Ambient on Chemical Composition and Thickness Uniformity of Sub-5-nm-Thick Oxide Films (2001) (1)
- A new mask ROM cell programmed by through-hole using double polysilicon technology (1983) (1)
- A high signal swing pass-transistor logic using surrounding gate transistor (2000) (1)
- Great Encounters Leading Me to the Inventions of Flash Memories and Surrounding Gate Transistor Technology (2013) (1)
- Sub-Halfmicron Flash Memory Technologies (Special Section on High Speed and High Density Multi Functional LSI Memories) (1994) (1)
- A Surrounding Gate Transistor(SGT): A Promising Candidate for an Ultrasmall MOSFET. (1994) (1)
- Technology Trend of Flash EEPROM (1993) (1)
- A 70ns 2Mb mask ROM with a programmed memory cell (1986) (1)
- Proposal of fabrication process for Floating Channel type SGT (FC-SGT) Flash Memory (2000) (1)
- A Novel High Capacitive-Coupling Ratio Surrounding Gate Transistor (HiCR-SGT) Flash Memory Cell (2006) (0)
- The new Shielded Bitline Sensing Method for FC-SGT Flash memory (2006) (0)
- A non-volatile semiconductor memory and methods of making. (1989) (0)
- A novel bit‐line direct‐sense circuit that uses a feedback system for high‐speed Flash memory (2006) (0)
- Special Issue on New Concept Device and Novel Architecture LSIs (1997) (0)
- Field-controlled semiconductor device and process for their preparation (1989) (0)
- Nichtfluechtige dynamic semiconductor memory device with nand-cell structure (1988) (0)
- A 18ns 8KW × 9b NMOS RAM (1986) (0)
- Memoire a semi-conducteurs remanente et procede de production (1989) (0)
- New Three Dimensional High Density S-SGT Flash Memory Architecture using Self-Aligned Interconnection Fabricating Technology without Photo Lithography Process for Tera Bits and Beyond (2003) (0)
- Drive Current Enhancement in the Surrounding Gate Transistor (2006) (0)
- Analysis of crosstalk between diffusions for GHz operation (2000) (0)
- Fabrication of Nanometer Silicon Pillars for Buried-Gate-Type Surrounding Gate Transistor by Silicon Quasi-Isotropic Etching (2006) (0)
- The Sprit of Invention; (2). Invention of Flash Memory. (1996) (0)
- Numerical analysis for the structure dependence on the subthreshold slope of Floating Channel type SGT(FC-SGT) Flash memory (2004) (0)
- Analysis of soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cells (2003) (0)
- Proposal of Analytical Method of Lower Diffusion Layer for Three Dimensional Structured Surrounding Gate Transistor (SGT) (2003) (0)
- Vertical Si Pillar Fabricated by ECR Plasma Etching with Precise Control of O2 Flow Rate in Cl2/O2 Mixtures (2004) (0)
- A Two-Terminal (T2) Cell for Ultra High Density DRAMs (1993) (0)
- Fabrication Process of Field Induced Source Line Surrounding Gate Transistor Flash Memory Cells (2006) (0)
- High Performance Buried Gate Surrounding Gate Transistor (BG-SGT) for Future Three-Dimensional Devices (2003) (0)
- NEW WRITWERASE OPERATION TECIINOLOGY FOR msn EEPROM CELLS TO IMPROVE TIIE RW DISTURD CIIARACll?RISTICS (1992) (0)
- An accurate model for threshold voltage and S-factor of partially-depleted surrounding gate transistor (PD-SGT) (2003) (0)
- 0.2 /spl mu/m nMOSFET using EB exposure for all lithography processes (2000) (0)
- Numerical Analysis of a Cylindrical Thin-Pillar (1992) (0)
- 積層サラウンディングゲートトランジスタ(S-SGT)構造セルを持つ新規超高密度フラッシュメモリ (2001) (0)
- The 1.44F/sup 2/ memory cell technology with the stacked-surrounding gate transistor (S-SGT) DRAM (2000) (0)
- How should Laboratory be Managed in the University. (1995) (0)
- The nonvolatile semiconductor memory (1989) (0)
- Influence of Silicon Wafer Loading Conditions on Thickness Uniformity of Sub-5nm-Thick Oxide Films (2001) (0)
- A 2.3uma MEMORY CELL STRUCTURE FOR 16Mb NAND EEPROMs (1990) (0)
- Cutting edge of the Information Storage Technologies. Technology of Flash Memory. (2002) (0)
- An Analysis of the Effect of Surrounding Gate Structure on Soft Error Immuniy (2004) (0)
- Electrically erasable and programmable semiconductor memory device (1988) (0)
- Numerical Analysis of the Erase Characteristics in Field Induced Source Line Surrounding Gate Transistor Flash Memory (2006) (0)
- Dependence of Coupling Ratio of High Capacitive-Coupling Ratio Surrounding Gate Transistor (HiCR-SGT) Flash Memory Cell on Structural Parameters (2006) (0)
- A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs (Special Issue on ULSI Memory Technology) (1996) (0)
- A non-volatile programmable semiconductor memory device (1988) (0)
- Endurance characteristics of flash EEPROMs (1997) (0)
- Reduction of pass-gate leakage by silicon-thickness thinning in double-gate MOSFETs (2003) (0)
- High speed and compact CMOS circuits with multi-pillar surrounding gate transistors (1989) (0)
- A33-ns64-MbDRAM (1991) (0)
- Novel structure and fabrication process for Double Gate MOSFET (2001) (0)
- New three dimensional (3D) memory array architecture for future ultra high density DRAM (invited) (2002) (0)
- Design Technology to Lower Resistance of Source Line for SGT NOR Flash Memory (2007) (0)
- Silicon Pillar Fabricated for SGT with Varying the Content of O2 in Cl2/O2 Gases by Using ECR Plasma Etching (2006) (0)
- Flash memories, their status and trends (1995) (0)
- Ideal storage technology for the ever-shrinking computer (1993) (0)
- Analytical Modeling of Short-Channel Multi-Gate SOI MOSFETs with Special Emphasis on the Partially-Depleted and Fully-Depleted Surrounding Gate Transistor (2005) (0)
- 1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar (2021) (0)
- The Fabrication of Nanometer Silicon Pillar Channel for Buried Gate Type Surrounding Gate Transistor by Silicon Isotropic Etching (2004) (0)
- Novel NAND DRAM with surrounding gate transistor (SGT)‐type gain cell (2004) (0)
- Analysis of the subthreshold characteristics for the FC-SGT flash memory cell (2006) (0)
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