Gaetano Palumbo

Gaetano Palumbo's AcademicInfluence.com Rankings

Gaetano Palumbo

Engineering

#7310

Historical Rank

Electrical Engineering

#1835

Historical Rank

engineering Degrees

Download Badge

Engineering

Gaetano Palumbo's Degrees

PhD Electrical Engineering University of California, Berkeley
Masters Electrical Engineering University of California, Berkeley
Bachelors Electrical Engineering University of California, Berkeley

Why Is Gaetano Palumbo Influential?

(Suggest an Edit or Addition)

(See a Problem?)

Gaetano Palumbo's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A low-voltage low-power voltage reference based on subthreshold MOSFETs (2003) (299)
Charge Pump Circuits: An Overview on Design Strategies and Topologies (2010) (290)
Charge-pump circuits: power-consumption optimization (2002) (228)
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic (2010) (196)
Advances in Reversed Nested Miller Compensation (2007) (167)
Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (1991) (166)
Design methodology and advances in nested-Miller compensation (2002) (151)
IEEE Transactions on Circuits and Systems II: Express Briefs (2004) (147)
Analysis and comparison on full adder block in submicron technology (2002) (138)
CMOS current amplifiers (1999) (127)
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies (2011) (125)
Design guidelines for reversed nested Miller compensation in three-stage amplifiers (2003) (123)
Design Procedure for Two-Stage CMOS Transconductance Operational Amplifiers: A Tutorial (2001) (117)
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space (2010) (116)
Design strategies for source coupled logic gates (2003) (112)
A compensation strategy for two-stage CMOS opamps based on current buffer (1997) (112)
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit (2011) (106)
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation (2007) (97)
Analytical comparison of frequency compensation techniques in three‐stage amplifiers (2008) (93)
Feedback Amplifiers: Theory and Design (2002) (92)
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor (2007) (88)
Current-feedback amplifiers versus voltage operational amplifiers (2001) (85)
Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme (2006) (85)
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison (2006) (80)
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS (2012) (78)
High-frequency harmonic distortion in feedback amplifiers: analysis and applications (2003) (78)
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design (2010) (78)
Double and triple charge pump for power IC: dynamic models which take parasitic effects into account (1993) (73)
A schmitt trigger by means of a ccii+ (1995) (71)
Mixed Full Adder topologies for high-performance low-power arithmetic circuits (2007) (71)
Design of an nth order Dickson voltage multiplier (1996) (70)
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers (2006) (68)
Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing (2015) (68)
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability (2015) (67)
Efficiency model of boost dc–dc PWM converters (2005) (66)
Oscillation frequency in CML and ESCL ring oscillators (2001) (65)
Feature - Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework (2006) (62)
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads (2015) (60)
Analytical comparison of reversed nested Miller frequency compensation techniques (2010) (60)
A Review of Charge Pump Topologies for the Power Management of IoT Nodes (2019) (60)
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates (2012) (58)
Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation (2019) (56)
A detailed analysis of power-supply noise attenuation in bandgap voltage references (2003) (56)
Evaluation on power reduction applying gated clock approaches (2002) (54)
Charge pump circuits with only capacitive loads: optimized design (2006) (52)
A high-performance very low-voltage current sense amplifier for nonvolatile memories (2005) (51)
A simple strategy for optimized design of one-level carry-skip adders (2003) (49)
High performance CMOS current comparator design (1996) (49)
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators (2012) (49)
Distortion analysis of Miller-compensated three-stage amplifiers (2006) (48)
1.5-V CMOS CCII+ with high current-driving capability (2003) (46)
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs (2016) (46)
Behavioral modeling of statistical phenomena of single‐photon avalanche diodes (2012) (45)
Harmonic distortion on class AB CMOS current output stages (1998) (44)
High-drive CMOS current amplifier (1998) (42)
Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers (2007) (41)
Improved behavioral and design model of an Nth-order charge pump (2000) (40)
Design methodology of Miller frequency compensation with current buffer/amplifier (2008) (40)
Modeling and optimized design of current mode MUX/XOR and D flip-flop (2000) (39)
Low-voltage high-drive CMOS current feedback op-amp (2005) (39)
High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes (2008) (39)
High linearity CMOS current output stage (1995) (39)
CMOS output stages for low-voltage power supplies (2000) (38)
Accurate model for single-photon avalanche diodes (2008) (38)
An optimized compensation strategy for two-stage CMOS op amps (1995) (37)
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs (2008) (37)
Effects of nonlinear feedback in the frequency domain (2006) (36)
CML and ECL: optimized design and comparison (1999) (34)
Power estimation in adiabatic circuits: a simple and accurate model (2001) (34)
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers (2014) (34)
An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits (2012) (33)
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of ${C}_{L}$ (2018) (31)
Design Strategies for Class A CMOS CCIIS (1999) (30)
A New Compact Low-Power High-Speed Rail-to-Rail Class-B Buffer for LCD Applications (2010) (30)
Evaluation of energy consumption in RC ladder circuits driven by a ramp input (2004) (29)
A novel pseudo random bit generator for cryptography applications (2002) (28)
Propagation Delay of an RC-Chain With a Ramp Input (2007) (27)
Accurate estimation of high-frequency harmonic distortion in two-stage Miller OTAs (2005) (27)
Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches (2014) (27)
Charge pump with adaptive stages for non-volatile memories (2006) (26)
Active reversed nested Miller compensation for three-stage amplifiers (2006) (25)
An approach to test the open-loop parameters of feedback amplifiers (2002) (25)
Analysis and Comparison on Full Adder Block in (2002) (25)
A 1.5-V high drive capability CMOS op-amp (1999) (25)
Design and comparison of very low-voltage CMOS output stages (2005) (25)
An approach to model high‐frequency distortion in negative‐feedback amplifiers (2008) (24)
Very efficient CMOS low-voltage output stage (1995) (24)
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies (2017) (24)
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops (2012) (24)
Highly accurate and simple models for CML and ECL gates (1999) (24)
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area (2019) (22)
CMRR frequency response of CMOS operational transconductance amplifiers (2000) (22)
Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth (2014) (22)
Exploiting the high-frequency performance of low-voltage low-power SC filters (2004) (21)
Modelling of source‐coupled logic gates (2002) (21)
Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations (2015) (21)
Solutions for CMOS current amplifiers with high-drive output stages (2000) (21)
From energy‐delay metrics to constraints on the design of digital circuits (2012) (20)
Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier (2008) (20)
Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS (2020) (19)
Performance evaluation of adiabatic gates (2000) (19)
1 V CMOS output stage with excellent linearity (2002) (19)
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time (2015) (19)
High-performance and simple CMOS unity-gain amplifier (2000) (19)
A high-performance CMOS voltage follower (1998) (19)
Reversed Double Pole-Zero Cancellation Frequency Compensation Technique for Three-Stage Amplifiers (2006) (18)
A 50‐mA 1‐nF Low‐Voltage Low‐Dropout Voltage Regulator for SoC Applications (2010) (18)
Energy consumption in RC tree circuits (2006) (18)
A simple and effective design strategy to increase power conversion efficiency of linear charge pumps (2019) (18)
Bipolar Current Feedback Amplifier: Compensation Guidelines (1999) (18)
Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads (2010) (17)
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes (2015) (17)
On the use of neural networks for Hamming coding (1991) (17)
Dynamic-biased capacitor-free NMOS LDO (2009) (17)
Resolution of a current-mode algorithmic analog-to-digital converter (2002) (17)
Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging (2020) (17)
A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start (2020) (16)
A High-Performance Charge Pump Topology for Very-Low-Voltage Applications (2020) (16)
Power-Aware Design of Nanometer MCML Tapered Buffers (2008) (16)
Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays (2018) (16)
Analysis and comparison of class AB current mirror OTAs (2011) (16)
Pseudorandom bit generator based on dynamic linear feedback topology (2002) (16)
Performance evaluation of the low-voltage CML D-latch topology (2003) (16)
Improved single-miller passive compensation network for three-stage CMOS OTAs (2016) (16)
Design guidelines for high-speed Transmission-gate latches: Analysis and comparison (2008) (15)
Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node (2018) (15)
Low-voltage class AB CMOS current output stage (1999) (15)
Linear distribution of capacitance in Dickson charge pumps to reduce rise time (2020) (15)
Pseudo-random sequence generators with improved inviolability performance (2006) (15)
DET FF topologies: A detailed investigation in the energy-delay-area domain (2011) (15)
A high-accuracy high-speed CMOS current comparator (1994) (15)
Robust design of CMOS amplifiers oriented to settling‐time specification (2017) (15)
Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications (2010) (15)
A novel representation for two-pole feedback amplifiers (1998) (14)
NAND/NOR adiabatic gates: power consumption evaluation and comparison versus the fan-in (2002) (14)
A gate-level strategy to design Carry Select Adders (2004) (14)
A novel 1-V class-AB transconductor for improving speed performance in SC applications (2003) (14)
Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control (2010) (14)
Analysis and compensation of two-pole amplifiers with a pole-zero doublet (1999) (14)
1.2 V CMOS output stage with improved drive capability (1999) (14)
Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion (2008) (14)
Detailed frequency analysis of power supply rejection in Brokaw bandgap (2001) (14)
Offset-compensated low power current comparator (1994) (14)
An Overview of Analog Feedback Part I: Basic Theory (1998) (13)
Analysis and optimization of gain-boosted telescopic amplifiers (2002) (13)
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering (2020) (13)
A novel CMOS voltage squarer (1997) (13)
New CMOS current mirrors with improved high-frequency response (1993) (13)
Power‐delay optimization of D‐latch/MUX source coupled logic gates (2005) (12)
A fast active quenching and recharging circuit for single-photon avalanche diodes (2005) (12)
Reversed nested Miller compensation with voltage follower (2002) (12)
Current-mode A/D fuzzy converter (2002) (12)
LDO compensation strategy based on current buffer/amplifiers (2007) (12)
Modeling and minimization of power consumption in charge pump circuits (2001) (12)
Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy (2014) (12)
Double and triple charge pump for power IC: ideal dynamical models to an optimised design (1993) (12)
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers (2013) (11)
Harmonic distortion in single-stage amplifiers (2002) (11)
Approach to the design of low-voltage SC filters (2000) (11)
1.5 V power supply CMOS voltage squarer (1997) (11)
Verilog-A modeling of SPAD statistical phenomena (2011) (11)
High-drive CMOS current-feedback opamp (1997) (11)
Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers (2007) (11)
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison (2008) (11)
A CMOS operational floating conveyor (1994) (11)
Approach to analyse and design nearly sinusoidal oscillators (2009) (10)
Current‐mode body‐biased switch to increase performance of linear charge pumps (2020) (10)
A high‐performance CMOS CCII (2001) (10)
Compensation strategy for high-speed three-stage switched-capacitor amplifiers (2016) (10)
Propagation delay model of a current driven RC chain for an optimized design (2003) (10)
Analysis and comparison of variations in double edge triggered flip-flops (2014) (10)
Well-defined design procedure for a three-stage CMOS OTA (2005) (10)
Clock boosters for 1.2-V SC circuits (1997) (10)
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers (2019) (9)
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions (2021) (9)
Low-voltage LDO Compensation Strategy based on Current Amplifiers (2008) (9)
Reversed nested Miller compensation with current follower (2001) (9)
Modeling of analog blocks by using standard hardware description language (2006) (9)
Nonidealities of Tow-Thomas biquads Using VOA- and CFOA-based Miller integrators (2005) (9)
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior (2021) (9)
Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders (2007) (9)
Optimized design of parallel carry-select adders (2011) (9)
A class AB CMOS current mirror with low-voltage capability (1999) (9)
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology (2007) (9)
Power-delay trade-offs in SCL gates (2002) (9)
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders (2007) (9)
A new method for harmonic distortion analysis in class-AB stages (2003) (8)
An Overview of Analog Feedback Part II: Amplifier Configurations in Generic Device Technologies (1998) (8)
Optimised design of Wilson and improved Wilson CMOS current mirrors (1993) (8)
Design of CMOS three-stage amplifiers for near-to-minimum settling-time (2021) (8)
High-performance frequency compensation topology for four-stage OTAs (2014) (8)
Analysis and Comparison in the Energy-Delay-Area Domain (2015) (8)
On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique (2009) (8)
Double and triple charge pump design (1991) (8)
Analysis and comparison of low-voltage CML D-latch (2002) (8)
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies (2019) (7)
Design guidelines of CMOS class-AB output stages: a tutorial (2008) (7)
A general HDL-A model of a DC-DC switching regulator core (1999) (7)
Bessel‐like compensation of three‐stage operational transconductance amplifiers (2018) (7)
Filter circuits synthesis with CFOA-based differentiators (1999) (7)
Nanometer MCML gates: models and design considerations (2006) (7)
A technique for the reduction of the input resistance of current-mode circuits (1998) (7)
NMOS Low Drop-Out Regulator with Dynamic Biasing (2006) (7)
Optimized design of high fan-in multiplexers using tri-state buffers (2002) (7)
Delay estimation of SCL gates with output buffer (2001) (7)
Design guidelines for optimized nested Miller compensation (2000) (7)
A Novel Very Low Voltage Topology to implement MCML XOR Gates (2018) (7)
Harmonic distortion in three-stage nested-Miller-compensated amplifiers (2004) (7)
Behavioral Model of Analog Circuits for Nonvolatile Memories with VHDL-AMS (2002) (7)
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops (2021) (7)
An efficient fuzzy controller architecture in SC technique (2002) (7)
Design of MUX, XOR and D-latch SCL gates (2003) (7)
New CMOS current Schmitt triggers (1992) (7)
Analysis and evaluation of harmonic distortion in the tunnel diode oscillator (2006) (7)
Flip-Flop Design in Nanometer CMOS (2015) (6)
A novel fully adjustable cmos current schmitt trigger with a 1.5 V power supply (1998) (6)
Metrics and design considerations on the energy-delay tradeoff of digital circuits (2009) (6)
Power-delay optimization of D-latch/MUX source coupled logic gates: Research Articles (2005) (6)
The noise performance of CMOS Miller operational transconductance amplifiers with embedded current‐buffer frequency compensation (2017) (6)
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders (2006) (6)
Optimized design of 4 stage Dickson voltage multiplier (1994) (6)
Offset compensation technique for CMOS current comparators (1994) (6)
A new advanced RNMC technique with dual-active current and voltage buffers for low-power high-load three-stage amplifiers (2009) (6)
A simple keeper topology to reduce delay variations in nanometer domino logic (2012) (6)
A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route (2021) (6)
A theoretical approach to the design of A/D converter by means of Schmitt triggers (1992) (6)
Analysis of Harmonic Distortion in the Colpitts Oscillator (2006) (6)
A CMOS transresistance current amplifier (1997) (6)
Distortion analysis in the frequency domain of a Gm-C biquad (2007) (6)
An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs (2009) (5)
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads (2021) (5)
Delay models and design guidelines for MCML gates with resistor or PMOS load (2020) (5)
A novel CMOS current-mode power amplifier (1997) (5)
Understanding Delta- Sigma Data Converters [Book Review] (2006) (5)
Optimized Design of Carry-Bypass Adders (2001) (5)
Feedback amplifiers: a simplified analysis of harmonic distortion in the frequency domain (2001) (5)
Analysis and Modeling of Energy Consumption in RLC Tree Circuits (2009) (5)
On the high-frequency response of CMOS cascode current mirror (1994) (5)
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates (2000) (5)
VLSI implementation of a double-layer single cell RD-CNN for motion control (2000) (5)
Delay uncertainty due to supply variations in static and dynamic full adders (2006) (5)
Resistance of Feedback Amplifiers: A Novel Representation (2007) (5)
Evaluation of power consumption in adiabatic circuits (2000) (5)
Dynamic analysis of 3 stage Dickson voltage multiplier for an optimized design (1994) (5)
Analysis of the impact of process variations on static logic circuits versus fan-in (2008) (5)
Harmonic distortion in non‐linear amplifier with non‐linear feedback (1998) (5)
An accurate offset-compensated current comparator (1994) (5)
A 'neural' A/D converter utilizing Schmitt trigger (1990) (5)
Harmonic distortion in non-linear amplifier with non-linear feedback (1998) (5)
Effect of CFOA nonidealities in Miller integrator cells (2004) (5)
A new voltage reference topology based on subthreshold MOSFETs (2002) (5)
A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers (2022) (5)
A novel fully adjustable CMOS current Schmitt trigger with a 1·5 V power supply (1998) (4)
A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes (2021) (4)
CMOS class-AB tunable voltage-feedback current operational amplifier (2014) (4)
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects (2007) (4)
CML ring oscillators: oscillation frequency (2001) (4)
An optimized Miller compensation based on voltage buffer (1995) (4)
Low power strategy for a TFT controller (2002) (4)
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications (2011) (4)
Charge pump circuits: power consumption optimization - a summary (2004) (4)
A fuzzy controller for step-up DC/DC converters (2001) (4)
Behavioral model of charge pumps with VHDL (2005) (4)
Analysis, modelling and optimization of a gain boosted telescopic amplifier (2003) (4)
Modeling of Feedback Analog Circuits with VHDL (2006) (4)
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering (2018) (4)
Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior (2021) (4)
Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers (2010) (4)
A 1.35-V sense amplifier for non volatile memories based on current mode approach (2004) (4)
Hybrid nested Miller compensation with nulling resistors (2002) (4)
Frequency behaviour of the Wilson and improved Wilson MOS current mirrors: analysis and design strategies (1996) (4)
A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors (2015) (4)
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps (2022) (3)
Improved dynamic model of double and triple charge pumps to take current leakage into account (1994) (3)
New sample-and-hold for high frequency applications (1994) (3)
Figures of merit for class AB input stages (2011) (3)
An approach to model high-frequency distortion in negative-feedback amplifiers: Research Articles (2008) (3)
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency (2010) (3)
Propagation delay of an RC‐circuit with a ramp input: An analytical very accurate and simple model (2009) (3)
Signal Amplification by Means of a Dickson Charge Pump: Analysis and Experimental Validation (2022) (3)
The Design of CMOS Radiofrequency Integrated Circuits, 2nd Edition [Book Review] (2006) (3)
Double and triple charge pumps with mos diodes: Dynamic models to an optimized design (1994) (3)
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic (2021) (3)
Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems [Book Review] (2005) (3)
Built in self test for low cost testing of a 60MHz synchronous flash memory (2001) (3)
The Design of CMOS Radiofrequency Integrated Circuits, 2nd ED - [Book Review] (2006) (3)
A high-drive high-gain CMOS current operational amplifier (1998) (3)
Voltage regulator based on an high-efficiency adaptive charge pump (2002) (3)
A fuzzy membership function circuit in SC technique (2000) (3)
New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers (2005) (3)
Design of the Wilson and improved Wilson MOS current mirrors reach the best settling time (1994) (3)
Optimized design of high fan-in multiplexers using switches with driving capability (2001) (3)
Switched capacitor compatible minimum-maximum function (2000) (3)
Design guidelines for bipolar frequency dividers (2002) (3)
Techniques for evaluating harmonic distortion in class-AB output stages: A tutorial (2006) (3)
II-245 ECCTD ’ 01-European Conference on Circuit Theory and Design , August 28-31 , 2001 , Espoo , Finland Optimized Design of Carry-Bypass Adders (2001) (3)
A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS (2020) (3)
The Dickson Charge Pump as a Signal Amplifier (2022) (3)
Very fast carry energy efficient computation based on mixed dynamic=transmission-gate full adders (2007) (3)
Statistical modelling and design guidelines of CMOS current references (2006) (3)
Modelling and design considerations on CML gates under high‐current effects (2005) (3)
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits (1996) (3)
An approach to the design of low-voltage SC filters (1998) (3)
Distortion analysis of three-stage amplifiers with reversed nested-Miller compensation (2005) (3)
A new accurate analytical expression for the SiPM transient response to single photons (2014) (3)
High-speed voltage buffers for the experimental characterization of CMOS transconductance operational amplifiers (1999) (3)
A fast driver circuit for single-photon sensors (2006) (3)
Voltage references: from diodes to precision high-order bandgap circuits [Book Review] (2002) (3)
A switched-capacitor compatible membership function block (2000) (3)
Performance parameters of current operational amplifiers (1999) (3)
Low Area Accurate CMOS Current Schmitt Trigger. (1993) (3)
1.5–V high–drive second generation current conveyor (2002) (2)
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates (2002) (2)
Verilog-a modeling of Silicon Photo-Multipliers (2016) (2)
Design strategies of cascaded CML gates (2006) (2)
Compact and simple output transition time model in nanometer CMOS gates (2008) (2)
A high accuracy CMOS CCII+ (1996) (2)
Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs (2010) (2)
Physical design aware selection of energy-efficient and low-energy nanometer flip-flops (2010) (2)
Low-voltage linear voltage regulator suitable for memories (2004) (2)
Design guidelines for minimum harmonic distortion in a wien oscillator with automatic amplitude control system (2008) (2)
Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio (2022) (2)
Optimised design of ECL gates with power constraint (2004) (2)
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic (2009) (2)
Step-response optimization techniques for low-power three-stage operational amplifiers for large capacitive load applications (2009) (2)
Analysis of the impact of random process variations in CMOS tapered buffers (2009) (2)
Comparison between Miller integrator cells using VOAs and CFOAs (2002) (2)
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads (2018) (2)
High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications (2013) (2)
Design of low-power high-speed bipolar frequency dividers (2002) (2)
ECCTD ’ 01-European Conference on Circuit Theory and Design , August 28-31 , 2001 , Espoo , Finland Predicting Propagation Delay in SCL Gates (2001) (2)
A Clock Boosted Charge Pump with Reduced Rise Time (2018) (2)
Comparative analysis of the robustness of master-slave flip-flops against variations (2015) (2)
Miller Compensation: Optimization with Current Buffer/Amplifier (2007) (2)
A high-speed low-power output buffer amplifier for large-size LCD applications (2009) (2)
Analytical comparison of frequency compensation techniques in three-stage amplifiers: Research Articles (2008) (2)
Simple and accurate modeling of the output transition time in nanometer CMOS gates (2010) (2)
Mixed Logic Styles for High-Speed Low-Power Arithmetic Circuits (2)
Design of low-voltage low-power SC filters for high-frequency applications (2003) (2)
Current feedback amplifier: stability and compensation (1997) (2)
Energy consumption in RLC tree circuits (2007) (2)
Design techniques for low-power cascaded CML gates (2005) (2)
An Approach to Energy Consumption Modeling in RC Ladder Circuits (2002) (2)
Cmos current comparator: Simplified analysis of the delay time (1994) (2)
Efficient and Accurate Models of Output Transition Time in CMOS Logic (2007) (2)
Propagation delay model of current driven RC chain (2002) (1)
Nonidealities of Tow-Thomas Biquads Using (2005) (1)
Optimized frequency compensation topology for low-power three-stage OTAs (2013) (1)
An ultra-compact MOS model in nanometer technologies (2011) (1)
VHDL-based description of biquad filters (2005) (1)
Current leakage and parasitic capacitance in transient second and triple order Cockcroft-Walton voltage multiplier (1992) (1)
Power-delay optimization in MCML tapered buffers (2008) (1)
II-125 ECCTD ’ 01-European Conference on Circuit Theory and Design , August 28-31 , 2001 , Espoo , Finland VHDL-AMS Model of Sense Amplifier for Flash Memories (2001) (1)
Dickson Charge Pump: Design Strategy for Optimum Efficiency (2021) (1)
A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW (2016) (1)
High-speed bipolar MUX modeling and design (2000) (1)
Design Through Verilog HDL [Book Review] (2006) (1)
Low-Drive Current Amplifiers (1999) (1)
PVT variations in differential flip-flops: A comparative analysis (2015) (1)
Design of cascaded ECL gates with power constraint (2006) (1)
Dickson Voltage Multiplier: Beyond the Switching Limits (2020) (1)
Simplified model of an amplifier with two poles and a pole-zero doublet (1996) (1)
A 1-V CMOS output stage with high linearity (2003) (1)
A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers (2010) (1)
A Design Methodology for High-Speed Low-Power MCML Frequency Dividers (2006) (1)
VHDL-based modeling of a DC-DC boost converter (2005) (1)
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders (2022) (1)
Guidelines for designing class-AB output stages (2005) (1)
Analysis of the noise characteristics of current-feedback operational amplifier (2000) (1)
Gain-compensated sample-and-hold circuit for high frequency application (1993) (1)
Modular Low-Power, High-Speed CMOS Analog-Todigital Converter for Embedded Systems [Book Review] (2005) (1)
A modified Hopfield neural network to allow a speed A/D conversion (1991) (1)
Single-miller all-passive compensation network for three-stage OTAs (2015) (1)
Statistical analysis of the resolution in a current-mode ADC (2002) (1)
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW (2018) (1)
A high-frequency differential sc integrator with highly accurate gain compensation (1994) (1)
Modelling and design considerations on CML gates under high-current effects: Research Articles (2005) (1)
A 1.5 V CMOS voltage multiplier (1998) (1)
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review (2022) (1)
Settling-time oriented OTA design through the approximation of the ideal delay (2018) (1)
Analysis and optimization of a novel CMOS multiplier (2001) (1)
Propagation delay of an RC-circuit with a ramp input: An analytical very accurate and simple model (2009) (1)
A novel 1.5-V CMOS mixer (1998) (1)
Analysis of power supply noise attenuation in a PTAT current source (2002) (1)
Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs (2003) (0)
RC-Chain: a Simple Model of Delay with a Ramp Input (2006) (0)
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits (2010) (0)
DelayUncertainty DuetoSupply Variations inStatic andDynamic Full Adders (2006) (0)
The Logical Effort Method (2015) (0)
A novel 1.5-V CMOS operational amplifier (1997) (0)
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML (2021) (0)
Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers (2009) (0)
Energy Efficiency Versus Clock Slope (2015) (0)
Hold Time Issues and Impact of Variations on Flip-Flop Topologies (2015) (0)
Silicon Nanoelectronics - [Book Review] (2006) (0)
Design of CML gate with the best propagation delay (1998) (0)
Gain-compensated switched-capacitor integrator based on a four-input operational amplifier (1993) (0)
Design and Comparison of Very Low-Voltage (2005) (0)
Explicit energy evaluation in RLC tree circuits with ramp inputs (2008) (0)
195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4–10−3 mm2 (2015) (0)
Microprocessor design using hardware description language (2008) (0)
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017 (2018) (0)
Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach (2022) (0)
A generalization of Miller formulae for nonlinear feedback networks (2007) (0)
Signal Ampliﬁcation by Means of a Dickson Charge Pump: Analysis and Experimental Validation (2022) (0)
ULSI Semiconductor Technology Atlas [Book Review] (2005) (0)
Comparison of methods for predicting distortion in class-AB stages (2005) (0)
Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity (2009) (0)
Behavioral Model of Silicon Photo-Multipliers Suitable for Transistor-Level Circuit Simulation (2021) (0)
Variability budgetin pulsed flip-flops (2015) (0)
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits (2009) (0)
The semi-flash A/D converter (1991) (0)
Novel simple models of CML propagation delay (1998) (0)
ReversedDouble Pole-ZeroCancellation Frequency Compensation TechniqueforThree-StageAmplifiers (2006) (0)
Highly-accurate propagation delay analytical model of an RC-circuit with a ramp input (2007) (0)
er All-Passive Compen rk for Three-Stage OTA (2015) (0)
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model (2005) (0)
A General Behavioral Model of Charge Pump DC-DC converters (2020) (0)
Book Reviews (1881) (0)
0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison (2021) (0)
27MHzのGBWを用いた0.003mm~mW3段増幅器駆動10nF【Powered by NICT】 (2016) (0)
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs (2006) (0)
Optimized design of source coupled logic gates in GaAs HEMT technology (2005) (0)
A new method for evaluating harmonic distortion in push-pull output stages (2003) (0)
Sigma-Delta A/D fuzzy converter (2004) (0)
Nano-CMOS Circuit and Physical Design [Book Review] (2006) (0)
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input (2002) (0)
Distortion Analysis of Nonlinear Amplifiers (2003) (0)
Dependence of Differential flip-flops performance on clock slope and relaxation of clock network design (2009) (0)
Logic gates dynamic modeling by means of an ultra-compact MOS model (2012) (0)
TG Master-Slave FFs: High-speed optimization (2011) (0)
An offset compensated fully differential CMOS current comparator (1995) (0)
Low harmonic distortion class AB CMOS current output stage (1996) (0)
Improved single-miller passive compensation network for three-stage CMOS OTAs (2016) (0)
1 DESIGN IN THE ENERGY – DELAY SPACE (2012) (0)
Rosenstark-like Representation of Feedback Amplifier Resistance (2007) (0)
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints (2021) (0)
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers (2022) (0)
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design (2009) (0)
Design of CML gate propagation with the best delay (1998) (0)
Energy evaluation in RLC tree circuits with exponential input (2008) (0)
Flip-Flop Optimized Design (2015) (0)
Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers (2021) (0)
Design of current limiter for a smart power IC (1994) (0)
Analysis and optimization of a low-voltage class-AB output stage (2005) (0)
A delay model of CML gates valid under high-current effects (2003) (0)
Design in the Energy-Delay Space (2015) (0)
Design of CMOS OTAs with Settling-Time Constraints (2018) (0)
A comparison between amoled poly-TFT driver circuits (2005) (0)
A high-performance buffer for non-volatile memories (2002) (0)
Very-Low-Voltage Charge Pump Topologies for IoT Applications (2023) (0)
A novel model for single photon detectors (2005) (0)
Optimum clock slope for flip-flops within a clock domain: Analysis and a case study (2009) (0)
A novel method for determining open-loop parameters in feedback amplifiers (1999) (0)
Design strategy to minimize rise time and silicon area of charge pump with only capacitive loads (2005) (0)
MODELING OF DELAY VARIABILITYDUE TO SUPPLYVARIATIONSIN PASS-TRANSISTORAND STATICFULLADDERS (2006) (0)
Ultra-Fast and Energy-Efficient Pulsed Latch Topologies (2015) (0)
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model (2011) (0)
Clocked Storage Elements (2015) (0)
An Area Efficient Current limiter for Automotive IC: Analysis and Design (1995) (0)
Monolithic quenching-and-reset circuit for single-photon avalanche diodes (2014) (0)
Statistical analysis of CMOS current reference (2005) (0)
Power-Delay Optimized Design of Cascaded ECL Gates (2006) (0)
Nanometer flip-flops design in the E-D space (2010) (0)
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers (2022) (0)
Hardware implementation of a fault recovery protocol compliant with interbus-S standard (2004) (0)
Optimized design of ECL gates with a power constraint (2005) (0)
1.5–V high–drive second generation current conveyor (2002) (0)
High-Drive Current Amplifiers (1999) (0)

This paper list is powered by the following services:

What Schools Are Affiliated With Gaetano Palumbo?

Gaetano Palumbo is affiliated with the following schools:

University of Catania