Giovanni De Micheli

Giovanni De Micheli's AcademicInfluence.com Rankings

Giovanni De Micheli

Engineering

#497

World Rank

#844

Historical Rank

Electrical Engineering

#84

World Rank

#97

Historical Rank

engineering Degrees

Download Badge

Engineering

Giovanni De Micheli's Degrees

PhD Electrical Engineering Stanford University

Why Is Giovanni De Micheli Influential?

(Suggest an Edit or Addition)

According to Wikipedia, Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at École Polytechnique Fédérale de Lausanne , Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University. He holds a Nuclear Engineer degree , a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science under Alberto Sangiovanni-Vincentelli.

(See a Problem?)

Giovanni De Micheli's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Networks on Chips: A New SoC Paradigm (2002) (3954)
Synthesis and Optimization of Digital Circuits (1994) (2467)
A survey of design techniques for system-level dynamic power management (2000) (1334)
Bandwidth-constrained mapping of cores onto NoC architectures (2004) (727)
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005) (619)
Hardware-software cosynthesis for digital systems (1993) (609)
Policy optimization for dynamic power management (1998) (535)
Networks on chips - technology and tools (2006) (494)
Analysis of power consumption on switch fabrics in network routers (2002) (463)
Networks on chip: a new paradigm for systems on chip design (2002) (374)
Dynamic power management - design techniques and CAD tools (1997) (365)
System-level power optimization: techniques and tools (2000) (353)
Analysis of error recovery schemes for networks on chips (2005) (352)
SUNMAP: a tool for automatic topology selection and generation for NoCs (2004) (349)
Optimal State Assignment for Finite State Machines (1985) (342)
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems (1997) (313)
Synchronous versus asynchronous modeling of gene regulatory networks (2008) (276)
Error control schemes for on-chip communication links: the energy-reliability tradeoff (2005) (248)
/spl times/pipesCompiler: a tool for instantiating application specific networks on chip (2004) (246)
Dynamic power management for portable systems (2000) (241)
Readings in hardware / software co-design (2001) (237)
Dynamic power management for nonstationary service requests (1999) (232)
Cycle-accurate simulation of energy consumption in embedded systems (1999) (231)
Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs (2012) (229)
Dynamic voltage scaling and power management for portable systems (2001) (229)
Designing Application-Specific Networks on Chips with Floorplan Information (2006) (211)
Circuit and architecture trade-offs for high-speed multiplication (1991) (206)
Event-driven power management (2001) (203)
State assignment for low power dissipation (1994) (199)
Low power error resilient encoding for on-chip data buses (2002) (197)
Comparing System-Level Power Management Policies (2001) (196)
Synthesis and simulation of digital systems containing interacting hardware and software components (1992) (194)
Design, synthesis, and test of networks on chips (2005) (193)
The EPFL Combinational Benchmark Suite (2015) (188)
Automatic synthesis of low-power gated-clock finite-state machines (1996) (187)
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips (2006) (186)
System-level synthesis using re-programmable components (1992) (178)
Dynamic power management using adaptive learning tree (1999) (175)
On-Chip Communication Architectures: System on Chip Interconnect (2008) (169)
Quantitative comparison of power management algorithms (2000) (168)
Dynamic Power Management (1998) (168)
Powering networks on chips (2001) (164)
High Level Synthesis of ASlCs un - der Timing and Synchronization Constraints (1992) (162)
Energy Harvesting and Remote Powering for Implantable Biosensors (2011) (161)
Energy-efficient design of battery-powered embedded systems (1999) (160)
Designing low-power circuits: practical recipes (2001) (157)
A complete network-on-chip emulation framework (2005) (156)
Dynamic simulation of regulatory networks using SQUAD (2007) (155)
Saving power by synthesizing gated clocks for sequential circuits (1994) (155)
Address bus encoding techniques for system-level power optimization (1998) (153)
Majority-Inverter Graph: A novel data-structure and algorithms for efficient logic optimization (2014) (152)
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (2009) (149)
/spl times/pipes Lite: a synthesis oriented design library for networks on chips (2005) (149)
The Olympus synthesis system (1990) (148)
Prediction of regulatory modules comprising microRNAs and target genes (2005) (147)
System-level power optimization: techniques and tools (1999) (145)
Packetization and routing analysis of on-chip multiprocessor networks (2004) (144)
Operating-system directed power reduction (2000) (143)
Network-on-Chip design and synthesis outlook (2008) (141)
Majority-Inverter Graph: A New Paradigm for Logic Optimization (2016) (140)
Synchronous logic synthesis: algorithms for cycle-time minimization (1991) (138)
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees (2005) (136)
The Programmable Logic-in-Memory (PLiM) computer (2016) (135)
Temperature-aware processor frequency assignment for MPSoCs using convex optimization (2007) (127)
Advances, challenges and opportunities in 3D CMOS sequential integration (2011) (123)
Adaptive hard disk power management on personal computers (1999) (115)
Power optimization of core-based systems by address bus encoding (1998) (114)
Clock Skew Optimization for Peak Current Reduction (1996) (113)
Program implementation schemes for hardware-software systems (1994) (113)
Synthesis of networks on chips for 3D systems on chips (2009) (111)
Algorithms for technology mapping based on binary decision diagrams and on Boolean operations (1993) (109)
Memristive-Biosensors: A New Detection Method by Using Nanofabricated Memristors (2012) (108)
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization (2008) (105)
Power-aware operating systems for interactive systems (2002) (103)
Mapping and configuration methods for multi-use-case networks on chips (2006) (103)
System-level power optimization of special purpose applications: the Beach Solution (1997) (101)
Low-power task scheduling for multiple devices (2000) (101)
Source code optimization and profiling of energy consumption in embedded systems (2000) (101)
An adaptive low-power transmission scheme for on-chip networks (2002) (100)
A survey of Boolean matching techniques for library binding (1997) (100)
Transformation and synthesis of FSMs for low-power gated-clock implementation (1995) (98)
Technology mapping using Boolean matching and don't care sets (1990) (98)
Partitioning of functional models of synchronous digital systems (1990) (97)
HERCULES-a system for high-level synthesis (1988) (97)
Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros (1986) (95)
Packetized on-chip interconnect communication analysis for MPSoC (2003) (94)
Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits (1992) (94)
Regression-based RTL power modeling (2000) (93)
Computer-aided hardware-software codesign (1994) (92)
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences (1993) (91)
An Efficient Gate Library for Ambipolar CNTFET Logic (2011) (90)
Relative scheduling under timing constraints (1990) (90)
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research (2005) (90)
Synthesis of hardware models in C with pointers and complex data structures (2001) (90)
SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C (1998) (90)
An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments (2007) (88)
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip (2006) (88)
Multi-panel drugs detection in human serum for personalized therapy. (2011) (87)
A robust self-calibrating transmission scheme for on-chip networks (2005) (86)
Power and Reliability Management of SoCs (2007) (85)
Automatic instruction set extension and utilization for embedded processors (2003) (85)
The Olympus Synthesis System for Digital Design (1990) (85)
Telescopic units: a new paradigm for performance optimization of VLSI designs (1998) (84)
Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors. (2018) (82)
An Application-Specific Design Methodology for STbus Crossbar Generation (2005) (82)
Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity (2014) (82)
Software controlled power management (1999) (82)
Electrochemical Detection of Anti-Breast-Cancer Agents in Human Serum by Cytochrome P450-Coated Carbon Nanotubes (2012) (81)
Analysis and Optimization of MPSoC Reliability (2006) (81)
Hardware Synthesis from C/C++ Models (1999) (81)
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control (2006) (80)
Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs (2014) (80)
Glitch power minimization by selective gate freezing (2000) (80)
Label-Free Ultrasensitive Memristive Aptasensor. (2016) (80)
Thermal Balancing Policy for Multiprocessor Stream Computing Platforms (2009) (78)
Hardware C - A Language for Hardware Design (1988) (78)
Event-driven power management of portable systems (1999) (77)
Multicore thermal management with model predictive control (2009) (74)
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers (1999) (73)
Interface optimization for concurrent systems under timing constraints (1993) (73)
Fully Integrated Biochip Platforms for Advanced Healthcare (2012) (72)
Computer-Oriented Formulation of Transition-Rate Matrices via Kronecker Algebra (1981) (71)
Bringing NoCs to 65 nm (2007) (71)
Networks on Chips: From research to products (2010) (70)
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (2009) (70)
Energy efficient design of portable wireless systems (2000) (70)
Polarity control in WSe2 double-gate transistors (2016) (68)
Automated composition of hardware components (1998) (67)
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits (2011) (66)
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs (2014) (66)
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (2006) (65)
Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages (2014) (65)
Dynamic frequency scaling with buffer insertion for mixed workloads (2002) (65)
Processor Speed Control With Thermal Constraints (2009) (65)
Regression Models for Behavioral Power Estimation (1998) (64)
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers (2012) (63)
NoC Design and Implementation in 65nm Technology (2007) (63)
Emerging Technology-Based Design of Primitives for Hardware Security (2016) (62)
A co-synthesis approach to embedded system design automation (1996) (61)
Comparison of two Different Carbon Nanotube-Based Surfaces with Respect to Potassium Ferricyanide Electrochemistry (2012) (60)
An Application-Specific Design Methodology for On-Chip Crossbar Generation (2007) (60)
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures (2008) (60)
Aptamer-based Field-Effect Biosensor for Tenofovir Detection (2017) (59)
Technology mapping for electrically programmable gate arrays (1991) (59)
Modeling stochasticity and robustness in gene regulatory networks (2009) (59)
Lookup table power macro-models for behavioral library components (1999) (59)
Discovering coherent biclusters from gene expression data using zero-suppressed binary decision diagrams (2005) (59)
The EPFL Logic Synthesis Libraries (2018) (59)
Technology mapping for a two-output RAM-based field programmable gate array (1991) (58)
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design (2014) (58)
Exact Synthesis of Majority-Inverter Graphs and Its Applications (2017) (57)
Fast synthesis of platinum nanopetals and nanospheres for highly-sensitive non-enzymatic detection of glucose and selective sensing of ions (2015) (57)
Don't care set specifications in combinational and synchronous logic circuits (1993) (57)
Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs (1993) (56)
Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications (1983) (55)
Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement (2010) (54)
Contents provider-assisted dynamic voltage scaling for low energy multimedia applications (2002) (54)
Bubble electrodeposition of gold porous nanocorals for the enzymatic and non-enzymatic detection of glucose. (2016) (54)
A Schottky-barrier silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 decades of current (2014) (54)
Gate-level power and current simulation of CMOS integrated circuits (1997) (53)
xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips (2005) (53)
Application of symbolic computer algebra in high-level data-flow synthesis (2003) (53)
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees (2007) (53)
Co-Synthesis of Hardware and Software for Digital Embedded Systems (2008) (52)
On the use of inexact, pruned hardware in atmospheric modelling (2014) (51)
Crosstalk delay analysis using relative window method (1999) (51)
Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs (2013) (51)
A control theory approach for thermal balancing of MPSoC (2009) (51)
Highly-stable Li+ ion-selective electrodes based on noble metal nanostructured layers as solid-contacts. (2018) (50)
Continuous monitoring of Naproxen by a cytochrome P450-based electrochemical sensor. (2014) (50)
Using symbolic algebra in algorithmic level DSP synthesis (2001) (49)
Reducing switching activity on datapath buses with control-signal gating (1998) (49)
New Insight on Bio-sensing by Nano-fabricated Memristors (2011) (48)
Requester-aware power reduction (2000) (48)
New Logic Synthesis as Nanotechnology Enabler (2015) (47)
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware (1998) (47)
Proceedings of the Conference on Design, Automation and Test in Europe (2010) (47)
HW-SW emulation framework for temperature-aware design in MPSoCs (2007) (47)
An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation (2009) (47)
A high-performance low-power near-Vt RRAM-based FPGA (2014) (46)
Polynomial methods for component matching and verification (1998) (46)
Developing Synthesis Flows Without Human Knowledge (2018) (46)
Networks on Chips: A New Paradigm for Component-Based MPSoC Design (2005) (46)
Stochastic modeling and analysis for environmentally powered wireless sensor nodes (2008) (45)
Component selection and matching for IP-based design (2001) (45)
Inserting active delay elements to achieve wave pipelining (1989) (45)
GMS: Generic memristive structure for non-volatile FPGAs (2012) (44)
Deep Learning for Logic Optimization Algorithms (2018) (44)
Do Carbon Nanotubes Contribute to Electrochemical Biosensing (2014) (43)
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors (2007) (43)
Applications of Multi-Terminal Memristive Devices: A Review (2013) (42)
Performance driven reliable link design for networks on chips (2005) (42)
Observability don't care sets and Boolean relations (1990) (42)
Polynomial circuit models for component matching in high-level synthesis (2001) (42)
Heterogeneous Wireless Network Management (2003) (41)
Design systems for VLSI circuits : logic synthesis and silicon compilation (1987) (41)
A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency (1992) (41)
A Study on the Programming Structures for RRAM-Based FPGA Architectures (2016) (41)
Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS (2015) (40)
Finding all simple disjunctive decompositions using irredundant sum-of-products forms (1998) (40)
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication (2008) (40)
Recent advances in Third Generation Biosensors based on Au and Pt Nanostructured Electrodes (2016) (39)
Computing Accurate Performance Bounds for Best Effort Networks-on-Chip (2013) (39)
Physical planning for on-chip multiprocessor networks and switch fabrics (2003) (39)
Low power embedded software optimization using symbolic algebra (2002) (39)
Highly Sensitive Carbon Nanotube-Based Sensing for Lactate and Glucose Monitoring in Cell Culture (2011) (39)
Constrained software generation for hardware-software systems (1994) (38)
Reliability-aware design for nanometer-scale devices (2008) (38)
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (1997) (38)
A module selection algorithm for high-level synthesis (1991) (38)
Source code transformation based on software cost analysis (2001) (38)
Comparative study of three lactate oxidases from Aerococcus viridans for biosensing applications (2013) (38)
Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review (2012) (37)
Adaptive least mean square behavioral power modeling (1997) (37)
Biconditional BDD: A novel canonical BDD for logic synthesis targeting XOR-rich circuits (2013) (37)
Reliability and power management of integrated systems (2004) (37)
An Integrated Control and Readout Circuit for Implantable Multi-Target Electrochemical Biosensing (2014) (37)
Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits (1987) (37)
Feature - NoC emulation: a tool and design flow for MPSoC (2007) (36)
Hardware-software Co-synthesis for Digital Systems (2001) (36)
Full Fabrication and Packaging of an Implantable Multi-Panel Device for Monitoring of Metabolites in Small Animals (2014) (36)
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting (1999) (36)
An MIG-based compiler for programmable logic-in-memory architectures (2016) (36)
Advanced system on a chip design based on controllable-polarity FETs (2014) (36)
Computer-aided synthesis of PLA-based finite-state machines (1983) (36)
Decomposition Methods For Library Binding Of Speed-independent Asynchronous Designs (1994) (35)
Design Systems for VLSI Circuits (1987) (35)
Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs (2013) (35)
Analytical heat transfer model for thermal through-silicon vias (2011) (35)
A novel basis for logic rewriting (2017) (34)
A novel approach for network on chip emulation (2005) (34)
Dynamic power management of electronic systems (1998) (34)
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (2009) (34)
Design Space Exploration (1992) (34)
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips (2006) (33)
Femto-molar sensitive field effect transistor biosensors based on silicon nanowires and antibodies (2013) (33)
BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition (2013) (33)
Online convex optimization-based algorithm for thermal management of MPSoCs (2010) (33)
Bringing NoCs to 65nm (2007) (32)
A Differential Electrochemical Readout ASIC With Heterogeneous Integration of Bio-Nano Sensors for Amperometric Sensing (2017) (32)
Resolution of dynamic memory allocation and pointers for the behavioral synthesis from C (2000) (32)
Memristive Biosensors Under Varying Humidity Conditions (2014) (32)
An Outlook on Design Technologies for Future Integrated Systems (2009) (32)
Wearable multifunctional sweat-sensing system for efficient healthcare monitoring (2021) (32)
Programmable logic circuits based on ambipolar CNFET (2008) (32)
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip (2007) (31)
Boolean logic optimization in Majority-Inverter Graphs (2015) (31)
Design for testability of gated-clock FSMs (1996) (31)
Clustering protein environments for function prediction: finding PROSITE motifs in 3D (2007) (31)
Dynamic Scheduling And Synchronization Synthesis Of Concurrent Digital Systems Under System-level Constraints (1994) (31)
Specification and analysis of power-managed systems (2004) (31)
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (2012) (30)
Nanowire systems: technology and design (2014) (30)
Reducing power consumption of dedicated processors through instruction set encoding (1998) (30)
Design, development, and validation of an in-situ biosensor array for metabolite monitoring of cell cultures. (2014) (30)
Smile: a computer program for partitioning of programmed logic arrays (1983) (29)
Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C (2001) (29)
Optimization of Reliability and Power Consumption in Systems on a Chip (2005) (29)
A method for calculating hard QoS guarantees for Networks-on-Chip (2009) (29)
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework (2006) (29)
Approaching a nanosecond: a 32 bit adder (1988) (29)
Modeling hierarchical combinational circuits (1993) (29)
Reliability Support for On-Chip Memories Using Networks-on-Chip (2006) (28)
NoC topology synthesis for supporting shutdown of voltage islands in SoCs (2009) (28)
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write (2013) (28)
Superior sensing performance of multi-walled carbon nanotube-based electrodes to detect unconjugated bilirubin (2013) (28)
Memristive devices fabricated with silicon nanowire schottky barrier transistors (2010) (28)
Multiplexing pH and temperature in a molecular biosensor (2010) (27)
Dynamic power management of laptop hard disk (2000) (27)
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control (2010) (27)
A novel multi-working electrode potentiostat for electrochemical detection of metabolites (2010) (27)
LUT-Based Hierarchical Reversible Logic Synthesis (2019) (26)
Computational identification of microRNAs and their targets. (2006) (26)
Design automation and design space exploration for quantum computers (2016) (26)
Resistive Programmable Through-Silicon Vias for Reconfigurable 3-D Fabrics (2012) (26)
MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits (2013) (26)
A System for Wireless Power Transfer and Data Communication of Long-Term Bio-Monitoring (2015) (25)
A simulation methodology for reliability analysis in multi-core SoCs (2006) (25)
Specification and analysis of timing constraints for embedded systems (1997) (25)
System-level dynamic power management (1999) (25)
Polynomial methods for allocating complex components (1999) (25)
High-level synthesis and optimization strategies in Hercules and Hebe (1990) (25)
Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget (2011) (25)
On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis (2019) (25)
A Sound and Complete Axiomatization of Majority-n Logic (2015) (25)
Hardware synthesis from C/C++ models (1999) (25)
Design, fabrication, and test of a sensor array for perspective biosensing in chronic pathologies (2012) (25)
Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices (2013) (25)
Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications (2019) (25)
A Study of Multi-Layer Spiral Inductors for Remote Powering of Implantable Sensors (2013) (25)
A Subcutaneous Biochip for Remote Monitoring of Human Metabolism: Packaging and Biocompatibility Assessment (2015) (24)
Timing-Error-Tolerant Network-on-Chip Design Methodology (2007) (24)
Ambipolar Gate-Controllable SiNW FETs for Configurable Logic Circuits With Improved Expressive Capability (2012) (24)
Logic Synthesis for Established and Emerging Computing (2019) (24)
Hardware/Software Co-Design: Application Domains and Design Technologies (1996) (24)
An integrated platform for advanced diagnostics (2011) (24)
Optimizing Majority-Inverter Graphs with functional hashing (2016) (23)
Characterization-free behavioral power modeling (1998) (23)
Spintronic majority gates (2015) (23)
AdaptHD: Adaptive Efficient Training for Brain-Inspired Hyperdimensional Computing (2019) (23)
Memristive sensors for pH measure in dry conditions (2014) (23)
Symbolic algebra and timing driven data-flow synthesis (2001) (23)
SiNW-FET in-Air Biosensors for High Sensitive and Specific Detection in Breast Tumor Extract (2016) (22)
Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system (1997) (22)
Memristor-based devices for sensing (2014) (22)
Run-time scheduler synthesis for hardware-software systems and application to robot control design (1997) (22)
Analysis and synthesis of concurrent digital circuits using control-flow expressions (1996) (22)
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands (2010) (22)
Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation (2007) (22)
Reversible Pebbling Game for Quantum Memory Management (2019) (22)
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism (2020) (22)
Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics (2007) (22)
Physically clustered forward body biasing for variability compensation in nanometer CMOS design (2009) (22)
Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling (2011) (21)
IronIC patch: A wearable device for the remote powering and connectivity of implantable systems (2012) (21)
Scalable Generic Logic Synthesis: One Approach to Rule Them All (2019) (21)
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks (2008) (21)
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors (2013) (21)
High-Level Synthesis of Digital Circuits (1993) (21)
Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros (1986) (21)
Comparing Sensitivities of Differently Oriented Multi-walled Carbon Nanotubes Integrated on Silicon Wafer for Electrochemical Biosensors (2011) (21)
Distributed EDA tool integration: the PPP paradigm (1996) (21)
SAT-based {CNOT, T} Quantum Circuit Synthesis (2018) (21)
Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems (2000) (21)
The memristive effect as a novelty in drug monitoring. (2017) (21)
SAT Based Exact Synthesis using DAG Topology Families (2018) (21)
New Approaches for Carbon Nanotubes-Based Biosensors and Their Application to Cell Culture Monitoring (2012) (21)
Busy man's synthesis: Combinational delay optimization with SAT (2017) (21)
An IoT Solution for Online Monitoring of Anesthetics in Human Serum Based on an Integrated Fluidic Bioelectronic System (2018) (20)
Hierarchical reversible logic synthesis using LUTs (2017) (20)
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells (2015) (20)
QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs (2013) (20)
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays (2007) (20)
Multicore thermal management using approximate explicit model predictive control (2010) (20)
IEEE/ACM TRANSACTIONS ON (2004) (20)
Fabrication of memristors with poly-crystalline silicon nanowires (2009) (20)
Sensitivity enhancement by carbon nanotubes: Applications to stem cell cultures monitoring (2009) (20)
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking (2016) (20)
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems (2019) (20)
TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs (2014) (19)
High-performance multipanel biosensors based on a selective integration of nanographite petals. (2014) (19)
Efficient voltammetric discrimination of free bilirubin from uric acid and ascorbic acid by a CVD nanographite-based microelectrode. (2014) (19)
Early wire characterization for predictable network-on-chip global interconnects (2007) (19)
Targeting of multiple metabolites in neural cells monitored by using protein-based carbon nanotubes (2011) (19)
Cleaning strategy for carbon-based electrodes: Long-term propofol monitoring in human serum (2018) (19)
Simulated Biological Cells for Receptor Counting in Fluorescence Imaging (2012) (19)
Remote System for Monitoring Animal Models With Single-Metabolite Bio-Nano-Sensors (2013) (19)
The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits (2019) (19)
Power distribution paths in 3-D ICS (2009) (19)
The combined effect of process variations and power supply noise on clock skew and jitter (2012) (18)
Inversion optimization in Majority-Inverter Graphs (2016) (18)
Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework (2006) (18)
Comparison of Three Methods of Biocompatible Multi-Walled Carbon Nanotubes Confinement for the Development of Implantable Amperometric Adenosine-5′-Triphosphate Biosensors (2011) (18)
Automatic layout and optimization of static CMOS cells (1988) (18)
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors (2012) (18)
Computational Study on the Electrical Behavior of Silicon Nanowire Memristive Biosensors (2015) (18)
Recurrence equations and the optimization of synchronous logic circuits (1992) (18)
Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging (2017) (18)
Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET (2013) (18)
Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form (2014) (17)
Constrained resource sharing and conflict resolution in Hebe (1991) (17)
Temperature sensor placement in thermal management systems for MPSoCs (2010) (17)
NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration (2005) (17)
Synthesis of low-power selectively-clocked systems from high-level specification (1996) (17)
Example-based support vector machine for drug concentration analysis (2011) (17)
Synthesis of power-managed sequential components based oncomputational kernel extraction (2001) (17)
Dynamic Voltage Scaling for Portable Systems (2007) (17)
A CMOS Amperometric System for Multi-Neurotransmitter Detection (2016) (17)
Energy Efficient Source Code Transformation based on Value Profiling (2000) (17)
Modeling of printed spiral inductors for remote powering of implantable biosensors (2011) (17)
Electrochemical nanostructured biosensors: carbon nanotubes versus conductive and semi-conductive nanoparticles (2014) (17)
Routing Aware Switch Hardware Customization for Networks on Chips (2006) (17)
Vertically-stacked double-gate nanowire FETs with controllable polarity: From devices to regular ASICs (2013) (17)
Graphene nanowalls for high-performance chemotherapeutic drug sensing and anti-fouling properties (2018) (16)
Efficient arithmetic logic gates using double-gate silicon nanowire FETs (2013) (16)
Power consumption of logic circuits in ambipolar carbon nanotube technology (2010) (16)
Endurance management for resistive Logic-In-Memory computing architectures (2017) (16)
Wireless Monitoring of Endogenous and Exogenous Biomolecules on an Android Interface (2016) (16)
Optimizing the control-unit through the resynchronization of operations (1992) (16)
Tackling the bottleneck of delay tables in 3D ultrasound imaging (2015) (16)
Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications (2012) (16)
Online thermal control methods for multiprocessor systems (2013) (16)
Interface Layering Phenomena in Capacitance Detection of DNA with Biochips (2007) (16)
Fast power estimation for deterministic input streams (1997) (16)
Dynamical spot queries to improve specificity in P450s based multi-drugs monitoring (2009) (16)
Energy efficient system design and utilization (2001) (16)
Surface trap mediated electronic transport in biofunctionalized silicon nanowires (2016) (16)
On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET (2015) (16)
Study on the bio-functionalization of memristive nanowires for optimum memristive biosensors. (2016) (16)
Automatic source code specialization for energy reduction (2001) (16)
Glucose and lactate monitoring in cell cultures with a wireless android interface (2014) (16)
Prospects for logic-on-a-wire (2008) (16)
Cache-efficient memory layout of aggregate data structures (2001) (16)
Data path placement with regularity (2000) (16)
Physical synthesis for ASIC datapath circuits (2002) (15)
A Flexible Front-End for Wearable Electrochemical Sensing (2018) (15)
Circuit design for human metabolites biochip (2011) (15)
Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip (2011) (15)
Cell transformations and physical design techniques for 3D monolithic integrated circuits (2013) (15)
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks (2020) (15)
Fault modeling in controllable polarity silicon nanowire circuits (2015) (15)
A Survey on Low-Power Techniques with Emerging Technologies (2015) (15)
Ambipolar silicon nanowire FETs with stenciled-deposited metal gate (2011) (15)
Logic Synthesis for Quantum Computing (2017) (15)
Design of digital audio input output chip (1989) (15)
Simultaneous monitoring of anesthetics and therapeutic compounds with a portable multichannel potentiostat (2016) (15)
Micro-fabrication of high-thickness spiral inductors for the remote powering of implantable biosensors (2014) (15)
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements (2014) (15)
Enzymatic and Nonenzymatic Electrochemical Interaction of Abiraterone (Antiprostate Cancer Drug) with Multiwalled Carbon Nanotube Bioelectrodes (2016) (14)
Fast hierarchical NPN classification (2016) (14)
Reversible Logic Synthesis via Biconditional Binary Decision Diagrams (2015) (14)
Scheduling and control generation with environmental constraints based on automata representations (1996) (14)
Optimization of Combinational Logic Circuits Based on Compatible Gates (1993) (14)
Biofuel Cells and Inductive Powering as Energy Harvesting Techniques for Implantable Sensors (2011) (14)
Accurate power analysis for near-Vt RRAM-based FPGA (2015) (14)
Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure (2017) (14)
Memristive Biosensors for PSA-IgM Detection (2015) (14)
Platinum nanopetal-based potassium sensors for acute cell death monitoring (2016) (14)
Effect of process variations in 3D global clock distribution networks (2012) (14)
Wave pipelining for majority-based beyond-CMOS technologies (2017) (14)
Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images (2006) (14)
Implicit methods for qualitative modeling of gene regulatory networks. (2012) (14)
Direct growth of nanotubes and graphene nanoflowers on electrochemical platinum electrodes. (2013) (14)
Enumeration of Reversible Functions and Its Application to Circuit Complexity (2016) (14)
Pleasure: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays (1983) (14)
Self-calibrating networks-on-chip (2005) (14)
A PLiM Computer for the Internet of Things (2017) (14)
A current-mode potentiostat for multi-target detection tested with different lactate biosensors (2012) (13)
FPGA-SPICE: A simulation-based power estimation framework for FPGAs (2015) (13)
Image thresholding techniques for localization of sub‐resolution fluorescent biomarkers (2013) (13)
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT (2016) (13)
Decoding nanowire arrays fabricated with the Multi-Spacer Patterning Technique (2009) (13)
P450-Based Nano-Bio-Sensors for Personalized Medicine (2011) (13)
Process-induced skew variation for scaled 2-D and 3-D ICs (2010) (13)
Designing Robust Systems with Uncertain Information (2003) (13)
An application of zero-suppressed binary decision diagrams to clustering analysis of DNA microarray data (2004) (13)
Extending CAD tools and techniques (1993) (13)
Scheduling with environmental constraints based on automata representations (1994) (13)
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications (2010) (13)
An implantable bio-micro-system for drug monitoring (2013) (13)
Value-sensitive automatic code specialization for embedded software (2002) (13)
Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies (2017) (13)
Long-Term Monitoring of Propofol and Fouling Effect on Pencil Graphite Electrodes (2018) (13)
Reliability-Aware Design for Nanometer-Scale Devices, January 2008 (2008) (13)
Networks on Chips: 15 Years Later (2017) (13)
Paradigm-Shifting Players for IoT: Smart-Watches for Intensive Care Monitoring (2016) (13)
A combined sensor placement and convex optimization approach for thermal management in 3D-MPSoC with liquid cooling (2013) (12)
A new ethylene glycol-silane monolayer for highly-specific DNA detection on Silicon Chips (2010) (12)
Performance analysis of 3-D monolithic integrated circuits (2010) (12)
Robust system design with uncertain information (2003) (12)
Improvements to boolean resynthesis (2018) (12)
Hardware/software co-design of run-time systems (1998) (12)
Computational kernels and their application to sequential power optimization (1998) (12)
Single-metabolite Bio-Nano-Sensors and system for remote monitoring in animal models (2011) (12)
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs (2019) (12)
Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs (2017) (12)
Improving the Fault Tolerance of Nanometric PLA Designs (2007) (12)
Practical exact synthesis (2018) (12)
Fast generation of lexicographic satisfiable assignments: Enabling canonicity in SAT-based applications (2016) (12)
Size Optimization of MIGs with an Application to QCA and STMG Technologies (2018) (12)
Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing (2009) (12)
Low-cost, CMOS compatible, Ta2O5-based hemi-memristor for neuromorphic circuits (2012) (12)
Nonsilicon, Non-von Neumann Computing - Part I [Scanning the Issue] (2019) (12)
Optimized electrochemical detection of anti-cancer drug by carbon nanotubes or gold nanoparticles (2015) (12)
Performance of Carbon Nano-Scale Allotropes in Detecting Midazolam and Paracetamol in Undiluted Human Serum (2018) (12)
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise (2013) (12)
Glitch power minimization by gate freezing (1999) (12)
Managing heterogeneous wireless environments via Hotspot servers (2005) (12)
Complex instruction and software library mapping for embedded software using symbolic algebra (2003) (11)
Energy-Reliability trade-Off for NoCs (2003) (11)
Computer-aided design and optimization of control units for VLSI processors (1988) (11)
New technologies for nanobiosensing and their applications to real-time monitoring (2011) (11)
Computer-aided synthesis of pla-based systems (1983) (11)
An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores (2013) (11)
TAT-based formal representation of medical guidelines: Imatinib case-study (2012) (11)
Synthesis of low-power selectively-clocked systems from high-level specification (2000) (11)
Enhanced pClustering and its applications to gene expression data (2004) (11)
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits (2021) (11)
Majority Logic Synthesis for Spin Wave Technology (2014) (11)
Enabling exact delay synthesis (2017) (11)
Structural rewriting in XOR-majority graphs (2019) (11)
Multichannel Front-End for Electrochemical Sensing of Metabolites, Drugs, and Electrolytes (2020) (11)
Reliable communication in systems on chips (2004) (11)
Synthesis of Control Systems (1987) (11)
Logic transformations for synchronous logic synthesis (1990) (11)
Nano-sensor and circuit design for anti-cancer drug detection (2011) (11)
Network Interface Architecture and Design Issues (2006) (11)
Finite-state machine partitioning for low power (1998) (11)
LUT Mapping and Optimization for Majority-Inverter Graphs (2016) (11)
Nanosized optoelectronic devices based on photoactivated proteins. (2012) (11)
Optimal synthesis of control logic from behavioral specifications (1991) (11)
1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA (2017) (11)
Algorithms for synchronous logic synthesis (1989) (11)
Gate-level current waveform simulation of CMOS integrated circuits (1996) (10)
Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits (1983) (10)
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology (2016) (10)
Synthesis and optimization of synchronous logic circuits from recurrence equations (1992) (10)
Majority-based synthesis for nanotechnologies (2016) (10)
The Programmable Logic-in-Memory (PLiM) Computer (Invited) (2016) (10)
“Bio-functionalization study of Memristive-Biosensors for early detection of prostate cancer” (2015) (10)
VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France (2007) (10)
Optimal frequencies for inductive powering of fully implantable biosensors for chronic and elderly patients (2010) (10)
Flexible sweat sensors for non-invasive optimization of lithium dose in psychiatric disorders (2019) (10)
An efficient manipulation package for Biconditional Binary Decision Diagrams (2014) (10)
Encoding of Pointers for Hardware Synthesis (1998) (10)
Ambipolar Si nanowire field effect transistors for low current and temperature sensing (2011) (10)
Characterization of integration algorithms for the timing analysis of mos vlsi circuits (1982) (10)
Complex library mapping for embedded software using symbolic algebra (2002) (10)
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers (2017) (10)
A lightweight cryptographic system for implantable biosensors (2014) (10)
A ultra-low-power FPGA based on monolithically integrated RRAMs (2015) (10)
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories (2008) (10)
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits (2014) (10)
Physical design tradeoffs in power distribution networks for 3-D ICs (2010) (10)
Notes on Majority Boolean Algebra (2016) (10)
Memristive Biosensors Integration With Microfluidic Platform (2016) (10)
Nanosystems Design and Technology (2009) (9)
End-to-End Industrial Study of Retiming (2018) (9)
A Drug Administration Decision Support System (2012) (9)
Efficient switching activity computation during high-level synthesis of control-dominated designs (1999) (9)
Iterative remapping for logic circuits (1998) (9)
Fast Procedures for the Electrodeposition of Platinum Nanostructures on Miniaturized Electrodes for Improved Ion Sensing (2019) (9)
FPGA Design with Double-Gate Carbon Nanotube Transistors (2011) (9)
Multiple Independent Gate FETs: How many gates do we need? (2015) (9)
Exploring programming model-driven QoS support for NoC-based platforms (2010) (9)
Applying pointer analysis to the synthesis of hardware from C (2001) (9)
The Data-Link Layer in NoC Design (2006) (9)
Heterogeneous integration of ReRAM crossbars in 180nm CMOS BEoL process (2015) (9)
Classifying Functions with Exact Synthesis (2017) (9)
A Simulation Based Buffer Sizing Algorithm for Network on Chips (2011) (9)
Post-P&R Performance and Power Analysis for RRAM-Based FPGAs (2018) (9)
Memristive biosensors based on full-size antibodies and antibody fragments (2019) (9)
An opportunistic reconfiguration strategy for environmentally powered devices (2006) (9)
A configurable IC to contol, readout, and calibrate an array of biosensors (2013) (9)
Compiling Permutations for Superconducting QPUs (2019) (9)
Wireless monitoring in intensive care units by a 3D-printed system with embedded electronic (2015) (9)
Optimal multi-processor SoC thermal simulation via adaptive differential equation solvers (2009) (9)
On-chip self-calibrating communication techniques robust to electrical parameter variations (2004) (9)
Developing highly-integrated subcutaneous biochips for remote monitoring of human metabolism (2012) (9)
Empirical study of noise dependence in electrochemical sensors (2013) (8)
Computationally Efficient Multiple-Independent-Gate Device Model (2016) (8)
Synthesis of ASICs with Hercules and Hebe (1991) (8)
Computer-aided synthesis of a bi-dimensional discrete cosine transform chip (1989) (8)
Exact Synthesis of ESOP Forms (2018) (8)
New probe immobilizations by lipoate-diethalonamines or ethylene-glycol molecules for capacitance DNA chip (2009) (8)
Implantable devices: the future of blood monitoring? (2013) (8)
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips (2006) (8)
Synthesis from mixed specifications (1996) (8)
Evaluating ESOP Optimization Methods in Quantum Compilation Flows (2019) (8)
Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache (2014) (8)
Guest Editorial: High-Level Synthesis of Digital Circuits (1990) (8)
A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis (2018) (8)
Prediction and Analysis of Human microRNA Regulatory Modules (2005) (8)
A synthesis framework based on trace and automata theory (1994) (8)
Silicon Nanowires for Biosensing (2018) (8)
Synchronous logic synthesis: circuit specifications and optimization algorithms (1990) (8)
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits (2011) (8)
CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips (2011) (8)
QoS-ocMPI: QoS-aware on-chip Message Passing Library for NoC-based Many-Core MPSoCs (2010) (8)
Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging (2018) (8)
Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform (2016) (8)
Sub-mW reconfigurable interface IC for electrochemical sensing (2014) (8)
A bimetallic nanocoral Au decorated with Pt nanoflowers (bio)sensor for H2O2 detection at low potential. (2017) (8)
Control optimization based on resynchronization of operations (1991) (8)
All-Solid-State Ion-Selective Electrodes: A Tutorial for Correct Practice (2021) (7)
MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip (2007) (7)
Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies (2021) (7)
Capacitance DNA bio-chips improved by new probe immobilization strategies (2010) (7)
pH sensing with temperature compensation in a Molecular Biosensor for drugs detection (2011) (7)
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique (2009) (7)
Faradic Peaks Enhanced by Carbon Nanotubes in Microsomal Cytochrome P450 Electrodes (2015) (7)
Fabrication and packaging of a fully implantable biosensor array (2013) (7)
Advanced Functional Decomposition Using Majority and Its Applications (2020) (7)
HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs (2011) (7)
RANSAC-based Enhancement in Drug Concentration Prediction Using Support Vector Machine (2012) (7)
Mapping Monotone Boolean Functions into Majority (2019) (7)
A Self-Contained System With CNTs-Based Biosensors for Cell Culture Monitoring (2012) (7)
Proceedings of the 37th Annual Design Automation Conference (1997) (7)
Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics (2018) (7)
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks (2011) (7)
Scalable Boolean Methods in a Modern Synthesis Flow (2019) (7)
Re-mapping for low power under tight timing constraints (1997) (7)
Representation of Medical Guidelines with a Computer Interpretable Model (2014) (7)
Network-on-Chip Design for Gigascale Systems-on-Chip (2005) (7)
Full system for translational studies of personalized medicine with free-moving mice (2015) (7)
Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture (2015) (7)
A novel electrochemical sensor for non-invasive monitoring of lithium levels in mood disorders (2018) (7)
Finding Co-Clusters of Genes and Clinical Parameters (2005) (7)
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study (2013) (7)
Boolean satisfiability in quantum compilation (2019) (7)
In-Vivo Validation of Fully Implantable Multi-Panel Devices for Remote Monitoring of Metabolism (2016) (7)
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors (2010) (7)
Implementation of an automated ECG-based diagnosis for a wireless body sensor platform (2009) (7)
Three-Input Gates for Logic Synthesis (2021) (7)
A Wearable Electrochemical Sensing System for Non-Invasive Monitoring of Lithium Drug in Bipolar Disorder (2021) (6)
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation (2016) (6)
Highly Sensitive Enzymatic MWCNTs-Based Biosensors for Detection of Abiraterone in Human Serum (2018) (6)
Operation regimes and electrical transport of steep slope Schottky Si-FinFETS (2017) (6)
Embedded Systems Handbook - CONTENTS (2005) (6)
Quantitative estimation of biological cell surface receptors by segmenting conventional fluorescence microscopy images (2014) (6)
Electronic implants: Power delivery and management (2013) (6)
Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis (2019) (6)
P450-mediated electrochemical sensing of drugs in human plasma for personalized therapy (2010) (6)
Design Methods and Tools for 3D Integration (2011) (6)
A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands (2012) (6)
Compiler-Driven Leakage Energy Reduction in Banked Register Files (2006) (6)
Continuous monitoring of propofol in human serum with fouling compensation by support vector classifier. (2020) (6)
Efficient Boolean Methods for Preparing Uniform Quantum States (2021) (6)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors (2018) (6)
Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique (2011) (6)
Apodization scheme for hardware-efficient beamformer (2016) (6)
Personalized modeling for drug concentration prediction using Support Vector Machine (2011) (6)
Data compression via logic synthesis (2014) (6)
Skew variability in 3-D ICs with multiple clock domains (2011) (6)
A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory (2012) (6)
From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires (2015) (6)
A DRAM Centric NoC Architecture and Topology Design Approach (2011) (6)
Enumerating Optimal Quantum Circuits using Spectral Classification (2020) (6)
Vertically-stacked gate-all-around polysilicon nanowire FETs with sub- µ m gates patterned by nanostencil lithography (2012) (6)
Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer (2016) (6)
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures (2008) (6)
Chapter 1 – Networks on Chip (2006) (6)
Multi-Target Electrolyte Sensing Front-End for Wearable Physical Monitoring (2019) (6)
Design of Networks on Chips for 3D ICs (2010) (6)
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms (1999) (6)
A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory (2012) (6)
Parameterized SVM for personalized drug concentration prediction (2013) (6)
Introduction to Introduction (2002) (6)
Medical guidelines reconciling medical software and electronic devices: Imatinib case-study (2012) (6)
Functional decomposition using majority (2018) (6)
Long-term Biosensors for Metabolite Monitoring by using Carbon Nanotubes (2011) (6)
Implicit methods for probabilistic modeling of Gene Regulatory Networks (2008) (6)
A study on buffer distribution for RRAM-based FPGA routing structures (2015) (6)
Exact Synthesis for Logic Synthesis Applications with Complex Constraints (2017) (5)
Circuits design and nano-structured electrodes for drugs monitoring in personalized therapy (2008) (5)
Carbon nanotubes-based electrochemical sensing for cell culture monitoring (2010) (5)
Multi-electrode amperometric biosensor for neurotransmitters detection (2013) (5)
Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory (2015) (5)
Novel readout circuit for memristive biosensors in cancer detection (2014) (5)
Designing best effort networks-on-chip to meet hard latency constraints (2013) (5)
Inter-Plane Communication Methods for 3-D ICs (2012) (5)
Physical design and synthesis (panel): merge or die! (1997) (5)
A fast TCAD-based methodology for Variation analysis of emerging nano-devices (2013) (5)
Application of FPGA Emulation to SoC Floorplan and Packaging Exploration (2007) (5)
Majority-Inverter Graph for FPGA Synthesis (2015) (5)
Voltage propagation method for 3-D power grid analysis (2012) (5)
Cyber-Medical Systems: Requirements, Components and Design Examples (2017) (5)
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory (2012) (5)
Multi-level logic benchmarks: An exactness study (2017) (5)
Redesigning hardware-software systems (1994) (5)
SAT-Based Combinational and Sequential Dependency Computation (2016) (5)
Timing Constraint Analysis for Embedded Systems (1994) (5)
A Versatile Mapping Approach for Technology Mapping and Graph Optimization (2022) (5)
Raspberry Pi driven flow-injection system for electrochemical continuous monitoring platforms (2017) (5)
Generalized matching from theory to application (1997) (5)
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization (2015) (5)
A Linear Approach to Multi-Panel Sensing in Personalized Therapy for Cancer Treatment (2013) (5)
Synthesis of regular computational fabrics with ambipolar CNTFET technology (2010) (5)
Data path placement with regularity (2000) (5)
Accurate logic-level power estimation (1995) (5)
Physical Design Considerations of One-level RRAM-based Routing Multiplexers (2017) (5)
Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications (2011) (5)
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits (2009) (4)
Integrated biosensors for personalized medicine (2012) (4)
Symbolic Algorithms for Token Swapping (2020) (4)
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection (2014) (4)
ROS: Resource-constrained Oracle Synthesis for Quantum Computers (2019) (4)
Memristive Biosensors for Ultrasensitive Diagnostics and Therapeutics (2019) (4)
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors (2007) (4)
Joint co-clustering: Co-clustering of genomic and clinical bioimaging data (2008) (4)
Effect of O2- migration in Pt/HfO2/Ti/Pt structure (2017) (4)
Carbon Nanotubes With Different Orientations for Electrochemical Biodevices (2012) (4)
Synthesis of Predictable Networks-on-Chip-Based (2007) (4)
Single-FPGA complete 3D and 2D medical ultrasound imager (2017) (4)
Xor-And-Inverter Graphs for Quantum Compilation (2022) (4)
An Innovative System of Membranes for the Monitoring of Endogenous and Exogenous Metabolites (2016) (4)
A Survey of Problems and Methods for Computer-Aided Hardware/Software Co-design (1995) (4)
Nanoelectronics: challenges and opportunities (2006) (4)
A Generalized Scharfetter-Gummel Method to Eliminate Crosswind Effects (1991) (4)
A surface potential and current model for polarity-controllable silicon nanowire FETs (2015) (4)
Towards structured ASICs using polarity-tunable Si nanowire transistors (2013) (4)
High sensitive detection in tumor extracts with SiNW-FET in-air biosensors (2014) (4)
Majority Logic Representation and Satisfiability (2014) (4)
A distributed interleaving scheme for efficient access to WideIO DRAM memory (2012) (4)
Network Architecture: Principles and Examples (2006) (4)
Majority Logic Synthesis (2018) (4)
Feature - Circuits and systems for high-throughput biology (2006) (4)
A fast pruning technique for low-power inexact Circuit design (2015) (4)
System-Level Design for Nano-Electronics (2007) (4)
Personalized Drug Administrations Using Support Vector Machine (2013) (4)
Logic synthesis for low power (2001) (4)
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits (2021) (4)
Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors (2016) (4)
Towards high-performance polarity-controllable FETs with 2D materials (2018) (4)
A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis (2006) (4)
All-solid-state Reference Electrodes for analytical applications (2019) (4)
Comparing the enhanced sensing interfaces of differently oriented carbon nanotubes onto silicon for bio-chip applications (2011) (4)
Panel: "will 3D-IC remain a technology of the future... even in the future?" (2013) (4)
Configurable Low-Latency Interconnect for Multi-core Clusters (2012) (4)
Energy-Efficient System-Level Design (2002) (4)
Generalized Matching : a new approach to concurrent logic optimization and library binding (1995) (4)
Multiwalled Carbon Nanotubes for Amperometric Array-Based Biosensors (2012) (4)
SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT (2013) (4)
An integrated platform for differential electrochemical and ISFET sensing (2016) (3)
Memory Representation and Hardware Synthesis of C Code with Pointers and Complex Data Structures (2003) (3)
Live demonstration: An IoT smartwatch-based system for intensive care monitoring (2017) (3)
Exact Synthesis of Boolean Functions in Majority-of-Five Forms (2019) (3)
Towards functionality-enhanced devices: Controlling the modes of operation in three-independent-gate transistors (2015) (3)
Nano-Tera.ch (2018) (3)
Nonsilicon, Non-von Neumann Computing - Part II (2020) (3)
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains (2017) (3)
Hardware/Software Co-Design Manuscript received February 1, 1996; revised December 2, 1996. This work was supported in part by DARPA, under Contract DABT 63-95-C-0049, and in part by NSF CAREER Award MIP 95-01615. Publisher Item Identifier S 0018-9219(97)02017-3 (2001) (3)
NEM relay design with biconditional binary decision diagrams (2015) (3)
Mixed Gold and Platinum Nanostructured Layers for All-Solid-State Ion Sensors (2018) (3)
Multi-Ion-Sensing Emulator and Multivariate Calibration Optimization by Machine Learning Models (2021) (3)
Designing reliable systems with unreliable components (2005) (3)
QubitHD: A Stochastic Acceleration Method for HD Computing-Based Machine Learning (2019) (3)
Quick generation of temporal power waveforms for RT-level hard macros (1997) (3)
Real-time high-sensitivity impedance measurement interface for tethered BLM biosensor arrays (2008) (3)
Electrochemical biochip for applications to wireless and batteryless monitoring of free-moving mice (2014) (3)
3D architecture and replaceable layers for label-free DNA biochips (2009) (3)
Optimized Slowdown in Real-Time Task Systems via Geometric Programming (2007) (3)
Technology mapping of digital circuits (1991) (3)
Automatic Uniform Quantum State Preparation Using Decision Diagrams (2020) (3)
Acceleration of Satissability Algorithms by Reconngurable Hardware (1998) (3)
A Simulation Model for Wireless Sensor Networks Based on TOSSIM (2007) (3)
Synchronization and power integrity issues in 3-D ICs (2010) (3)
Power Management for Systems (1998) (3)
Quantification of sub-resolution sized targets in cell fluorescent imaging (2012) (3)
In-Vivo Validation of Fully Implantable Multi-Panel Devices for Remote Monitoring of Metabolism. (2016) (3)
Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database (2021) (3)
Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice (2018) (3)
A Circuit Synthesis Flow for Controllable-Polarity Transistors (2014) (3)
Resistance impact by long connections on electrical behavior of integrated Memristive Biosensors (2016) (3)
Biochips for Regenerative Medicine: Real-time Stem Cell Continuous Monitoring as Inferred by High-Throughput Gene Analysis (2011) (3)
Memory Representation and Hardware Synthesis of C Code with Pointers and Complex Data Structures (2003) (3)
Comparative Performance of Different Nanostructured Electrochemical Sensors on Insulin Detection (2013) (3)
A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache (2016) (2)
Design and Optimization of a Lactate Amperometric Biosensor based on Lactate Oxidase and Multi Walled-Carbon Nanotubes (2008) (2)
Compilation flow for classically defined quantum operations (2021) (2)
Majority-based Design Flow for AQFP Superconducting Family (2022) (2)
Low-Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach. (2017) (2)
Energy-Efficient Network-On-Chip Design (2004) (2)
Characterization of memristive Poly-Si Nanowires via empirical physical modelling (2010) (2)
PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status (2011) (2)
tweedledum: A Compiler Companion for Quantum Computing (2022) (2)
Designing Routing and Message-Dependent Deadlock Free Networks on Chips (2006) (2)
MAL ENCODING OF CONTROL LOGIC (2003) (2)
Power Distribution Paths for 3-D IC (2009) (2)
Beyond local optimality of buffer and splitter insertion for AQFP circuits (2022) (2)
An FPGA-Based Test System for RRAM Technology Characterization (2018) (2)
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors (2015) (2)
Keynote Talk: NoCs: A Short History of Success and a Long Future (2018) (2)
Carbon Nanomaterials for Electrochemical and Electrochemiluminescent Medical Sensors (2015) (2)
Chip Challenge (2010) (2)
Guest Editor's Introduction: Hardware-Software Codesign (1994) (2)
Scaling-up ESOP Synthesis for Quantum Compilation (2019) (2)
Pairs of majority-decomposing functions (2018) (2)
Reliability and Reliable Design (2005) (2)
RM3 based logic synthesis (Special session paper) (2017) (2)
Highly sensitive electrodic materials based on Pt nanoflowers grown on Pt nanospheres for biosensor development (2015) (2)
Cell-based logic optimization (2000) (2)
An efficient electronic measurement interface for memristive biosensors (2017) (2)
Mining Gene Sets for Measuring Similarities (2006) (2)
Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis (2014) (2)
A multilevel engine for fast power simulation of realistic inputstreams (2000) (2)
Design of a CNFET array for sensing and control in P450 based biochips for multiple drug detection (2010) (2)
Genomic data mining enhanced by symbolic manipulation of Boolean functions (2005) (2)
Optimization opportunities in RRAM-based FPGA architectures (2017) (2)
Conformal Deposition of Conductive Single-Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach (2018) (2)
An Enhanced Design Methodology for Resonant Clock Trees (2013) (2)
Biocompatible packagings for fully implantable multi-panel devices for remote monitoring of metabolism (2015) (2)
Empowering Low-Cost CMOS Cameras by Image Processing to Reach Comparable Results with Costly CCDs (2013) (2)
Modeling And Synthesis of Synchronous System-Level Specifications (1997) (2)
Inexpensive 1024-channel 3D telesonography system on FPGA (2017) (2)
SAT-Sweeping Enhanced for Logic Synthesis (2020) (2)
Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration (2014) (2)
Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs (2016) (2)
Nano-Tera.ch: Engineering Complex Systems for Health, Security, and the Environment [IEEE News] (2010) (2)
3D serial TSV link for low-power chip-to-chip communication (2014) (2)
A Simulation-Guided Paradigm for Logic Synthesis and Verification (2022) (2)
Nano-fabricated memristive biosensors for biomedical applications with liquid and dried samples (2016) (2)
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis (2022) (2)
Designing micro/nano systems for a safer and healthier tomorrow (2008) (1)
CNT and proteins for bioelectronics in personalized medicine (2015) (1)
Integrating Logic-Level Power Management Techniques (1997) (1)
Resource constrained oracle synthesis for quantum circuits (2019) (1)
E-health: From sensors to systems (2015) (1)
Reconfiguration Strategies for Environmentally Powered (2007) (1)
Functionality-Enhanced Devices: From Transistors to Circuit-Level Opportunities (2018) (1)
Emulator Design and Generation of Synthetic Dataset in Multi-Ion Sensing (2020) (1)
The future of electronics, semiconductors, and design in Europe: panel (2015) (1)
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories (2009) (1)
LUT-Based Optimization For ASIC Design Flow (2021) (1)
Pattern-based FPGA logic block and clustering algorithm (2014) (1)
Assessment of Image Quality vs. Computation Cost for Different Parameterizations of Ultrasound Imaging Pipelines (2015) (1)
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper) (2020) (1)
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs (2011) (1)
Optimal Synthesis of Gated Clocks for Low-Power Finite-State Machines (1995) (1)
Heterogeneous Integration of ReRAM Crossbars in a CMOS Foundry Chip (2014) (1)
Logic synthesis and physical design: Quo vadis? (2011) (1)
Prospects for logic-ona-wire (2009) (1)
Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling (2011) (1)
Networks on Chips: Energy-Efficient Design of SoC Interconnect (2004) (1)
Carbon Nanotubes-Based Biosensors for Metabolite Monitoring in Cell Culture Medium (2012) (1)
A Stream Compaction Technique Based on Multi-Level Power Simulation (1998) (1)
- Low-Power FPGAs Based on Resistive Memories (2018) (1)
The Emerging Majority: Technology and Design for Superconducting Electronics (2021) (1)
A Full-Capacity Local Routing Architecture for FPGAs (2015) (1)
Direct and selective synthesis of a wide range of carbon nanomaterials by CVD at CMOS compatible temperatures (2014) (1)
Efficient Preparation of Cyclic Quantum States (2022) (1)
Computer-aided circuit design (2014) (1)
OP11MAL ENCODING OF CONTROL LOGIC (1984) (1)
From Logic to Gates: A Versatile Mapping Approach to Restructure Logic (2021) (1)
1024-Channel 3 D Ultrasound Digital Beamformer in a Single 5 W FPGA (2017) (1)
Single-FPGA 3D ultrasound beamformer (2016) (1)
Engineering complex systems for health, security and the environment (2012) (1)
Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads? (2014) (1)
A neural approach to drugs monitoring for personalized medicine (2015) (1)
Parallel vs. serial inter-plane communication using TSVs (2014) (1)
Integrated ESOP Refactoring for Industrial Designs (2018) (1)
Runtime 3-D stacked cache management for chip-multiprocessors (2013) (1)
A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only) (2016) (1)
Design Technologies for Networks on Chips (2007) (1)
Cyber-Medical Systems: Requirements, Components and Design (2016) (1)
Design Technologies for Networks-on-Chip (2007) (1)
A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks (2012) (1)
VHDL-AMS model of an electrochemical cell to design VLSI bio-chips (2011) (1)
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions (2022) (1)
(Invited) Control of Resistive Switching in Mott Memories Based on TiN/AM 4 Q 8 /TiN MIM Devices (2017) (1)
Reliable redundancy with memristive-biosensors to achieve statistical significance in immunosensing (2015) (1)
Novel configurable logic block architecture exploiting controllable-polarity transistors (2014) (1)
Digest of Papers PhD Forum at 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC) (2006) (1)
Extending Boolean Methods for Scalable Logic Synthesis (2020) (1)
Exploiting Binary Abstractions in Deciphering Gene Interactions (2006) (1)
Live demonstration: A smart camera for real-time monitoring of fluorescent cell biomarkers (2014) (1)
Efficient Deterministic Preparation of Quantum States Using Decision Diagrams (2022) (1)
Low-power clock distribution networks for 3-D ICs (2012) (1)
Live demonstration: In-situ biosensors array for cell culture monitoring (2014) (1)
Exploiting Circuit Duality to Speed up SAT (2015) (1)
"Modeling memristive biosensors" (2015) (1)
An event-detection high dynamic range CMOS image sensor (2013) (1)
Trip report for the IEEE logic synthesis workshop (1987) (1)
E-health: From sensors to systems (2015) (1)
Efficient method for generating minimal intervention sets in Gene Regulatory Networks (2010) (1)
A Non-Invasive Approach for Molecular Characterization of Glioblastoma Multiforme: Magnetic Resonance Imaging Correlation with cDNA Microarray Expression Profiles (2004) (1)
Methods for Designing Reliable Probe Arrays (2010) (1)
What is a 3D Network-on-Chip? (2009) (1)
Alternative design methodologies for the next generation logic switch (2011) (1)
Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS (2009) (1)
A new basic logic structure for data-path computation (abstract only) (2014) (1)
Constrained software synthesis for embedded applications (1997) (1)
Dynamic Power Management of Electronic Circuits and Systems (2003) (1)
Empowering Low-Cost CMOS Cameras by Image Processing to Reach Comparable Results with Costly CCDs (2013) (0)
Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13μm Adder for Image Processing Applications (2016) (0)
One-step rapid synthesis of Au-Pt nanofems for electrochemical sensing and biosensing (2016) (0)
Practical Exact Synthesis (Invited executive session) (2018) (0)
Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective (2022) (0)
Nano-tera.CH: Nano-technologies for tera-scale problems (2009) (0)
Power Management for Control Units (1998) (0)
On-Going Research on Address Bus Encoding for Low Power: A Status Report (1997) (0)
Nanosystems: Sensors and electronics for rational health monitoring (2011) (0)
Complete Tool Flow for Designing Networks-on-Chips Based Communication Architectures for Application-Specific Systems-on-Chips (2007) (0)
Towards High-Performance Polarity-Controllable FETs with 2 D Materials (2018) (0)
Introduction to System-Level Partitioning, Synthesis, and Interfacing (2002) (0)
Emerging Technologies in Computing Systems (2012) (0)
Simulation-Guided Boolean Resubstitution (2020) (0)
Multi-Panel, On-Single-Chip Memristive Biosensing (2019) (0)
The Complexity of Self-Dual Monotone 7-Input Functions (2019) (0)
Synthesis using Re-programmable Components (2004) (0)
Nano-tera.CH: Nano-technologies for tera-scale problems (2009) (0)
Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow (2008) (0)
Synergic effect of carbon nanotubes and microsomes containing cytochrome P450 in improving drug sensing (2016) (0)
Integrated biosensing for diagnosis and therapy (2011) (0)
Silicon Nanowire-Based Memristive Devices (2014) (0)
DATE Executive Committee (2005) (0)
Designs and Implementations of NoC-Based SoCs (2006) (0)
Network and Transport Layers in Networks on Chip (2006) (0)
Empowering Low-Cost CMOSCameras by Image Processing to ReachComparableResultswithCostlyCCDs (2013) (0)
Systems and Networks on Chip - Challenges and Solutions (2006) (0)
Amperometric biosensor with nanostructured electrodes by using multi-alled carbon nanotubes for glucose detection in cell culture medium (2009) (0)
Majority Logic Synthesis ( Invited Paper ) (2018) (0)
E-Health: Devices, Circuits and Systems (2015) (0)
Networking chip subsystems (2004) (0)
Nano-Tera.ch: Information Technology for Health, Environment, and Energy (2017) (0)
Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III. (1998) (0)
Lab-on-a-chip implants: a mini lab under the skin (2013) (0)
Keynote Talk: NoCs: A Short History of Success and a Long Future (2018) (0)
Panel: The future of electronics, semiconductors, and design in Europe (2015) (0)
From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++ (2021) (0)
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only) (2015) (0)
Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited (2013) (0)
Session details: Low-power system design (2002) (0)
Drug concentration prediction and delivery (2014) (0)
With my warmest regards. (2006) (0)
Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate (2010) (0)
Impact Analysis (2018) (0)
CMOS compatible and selective carbon nanomaterial growth for array-based electrochemical biosensors (2014) (0)
Simulated Biological Cells for Receptor Counting in Fluorescence Imaging (2012) (0)
Environmental Monitoring (2018) (0)
An Innovative System of Membranes for the Monitoring of Endogenous and Exogenous Metabolites (2016) (0)
Session details: New tools and methods for future embedded SoC (2004) (0)
An electrochemical sensor for quantitative analysis of Rhesus D antibodies in blood (2017) (0)
First commandment: at least, do nothing well! (2010) (0)
FRAME: Fast and Realistic Attacker Modeling and Evaluation for Temporal Logical Correlation in Static Noise (2015) (0)
Nanosystems: Sensors and electronics for rational health monitoring (2011) (0)
with Stenciled sub-μm Metal Gate (2009) (0)
Power Management for Functional Units (1998) (0)
System-level design technologies for heterogeneous distributed systems (2008) (0)
Demo: Efficient delay and apodization for on-FPGA 3D ultrasound (2016) (0)
Generic Logic Synthesis meets RTL Synthesis (2019) (0)
Multiwalled Carbon Nanotubes for Amperometric Array-Based Biosensors (2012) (0)
Mixed measurement and model-based dose recommending control flow with fixed sample library size (2014) (0)
Carbon Nanotubes contribute to Electrochemical Biosensing ? andro Carrara (2014) (0)
nano-tera.ch: Electronic Technology for Health Management (2015) (0)
Panel: First commandment at least, do nothing well! (2010) (0)
Technology mapping of digital circuits (1991) (0)
Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model (2018) (0)
We hope that the readers will enjoy this special issue and that the contributions presented here will stimulate their interests in the forthcoming technologies for circuits and systems. (2012) (0)
Session details: Low-power system design (2002) (0)
Resource Management in MPSoCs - Is our software ready for it? (2007) (0)
Physical Network Layer (2006) (0)
Comparative Performance of Different Nanostructured Electrochemical Sensors on Insulin Detection (2013) (0)
Projects (2018) (0)
Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication (2014) (0)
Majority-based Synthesis for Digital Nano-Technologies (2015) (0)
Physical design of polarity controllable transistors (2018) (0)
A CLUSTERING ALGORITHM FOR PARTITIONING OF PROGRAMMED LOGIC ARRAYS (0)
Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams (2014) (0)
Personalized Drug Administrations Using Support Vector Machine (2013) (0)
Smart Energy I (2018) (0)
IEEE council for electronic design automation: a new beginning (2005) (0)
CHARAcrERIZA nON OF INTEGRA nON ALGORITHMS FOR THE 11 MING ANALYSIS OF MOS VLSI CIRCUITS (2002) (0)
Multiple-Independent-Gate Nanowire Transistors: From Technology to Advanced SoC Design (2015) (0)
Designing Low-Power Circuits : Practical Recipes by Luca Benini (2001) (0)
Scheduling and Control Generation with Environmental Gonstr Based on Automata epresentati (1996) (0)
Don 't Care Set Specifications in Combinational and (1993) (0)
Reducing Coding Style E ects in High-Level Speci cations (1997) (0)
Plenary lecture [Second page is blank] (2005) (0)
Nanogap-based enzymatic-free electrochemical detection of glucose (2013) (0)
Memristive Aptasensors for Theranostics (2017) (0)
Genes, Circuits and Systems (2005) (0)
A pr 2 01 9 Reversible Pebbling Game for Quantum Memory Management (2019) (0)
Tutorial And Panel Session Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? (2006) (0)
Jerome Fron (2003) (0)
Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework (2005) (0)
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition (2021) (0)
A Multiple-level Logic Optimization System. Ieee Transactions on Com- Karon] Kevin Karplus. Using If-then-else Dags for Multi-levellogic Minimization. Ieee Trans- Actions on Computer-aided Design of Integrated Circuits and Systems, in Preparation. Km90] Kevin Karplus and Dipen Moitra. Using Dominato (1989) (0)
Wse2 polarity-controllable devices (2018) (0)
Real-Time Multi-Ion-Monitoring Front-End With Interference Compensation by Multi-Output Support Vector Regressor (2021) (0)
Live demonstration: Inexpensive 1024-channel 3D telesonography system on FPGA (2017) (0)
The sleep of reason produces monsters - From the past president (2004) (0)
Bioimaging and Functional Genomics (2006) (0)
Introduction to the Special Section on Functionality-Enhanced Devices (2014) (0)
Editorial (2012) (0)
Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition (2022) (0)
A Control Flow Prototype for a Dose Recommending Device for Chronic Myeloid Leukemia Patients (2013) (0)
Technologies and Platforms for Biomedical Systems (2014) (0)
Introduction (2018) (0)
Technologies and Platforms for Cyberphysical Systems (2014) (0)
Relative Control Generation (1992) (0)
Introduction to Case Studies (2002) (0)
Introduction to Co-simulation and Emulation (2002) (0)
Relative Control Optimization (1992) (0)
Introduction to Modeling (2002) (0)
Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography (2011) (0)
Comparing System-Level Power Management Policies System-Level Power Management 10 System-level power management is a trade-off among several factors , as this quantitative analysis shows (2001) (0)
Ultrafine grain FPGAs with polarity controllable transistors (2018) (0)
Welcome Message from the Chairs (2014) (0)
Num Bktrk/ Cost/constraint Exec Example Btk ($) Time (s) Table 4. Hierarchical Behavioral Partition- Ing and Package Design (1996) (0)
A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing (2017) (0)
A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited) (2015) (0)
Symbolic algorithms for embedded system design (2003) (0)
Programmable active pixel sensor for low-light biomedical applications (2014) (0)
Do our low-power tools have enough horse power? (panel session) (title only) (2000) (0)
Operating System Based Simulation Framework for Validation of Power Management Policies in Embedded Systems (2009) (0)
NutriChip SmartCam: an embedded image processing system for live surface receptor monitoring (2014) (0)
Keynote Address I Designing Robust Systems with Uncertain Information (2002) (0)
Plenary speaker (2020) (0)
Nanosystems: Devices, circuits, architectures and applications (2010) (0)
Clock and Power Distribution Networks for 3-D ICs (2009) (0)
Integrated Systems Challenges and Opportunities (2006) (0)
4 Optimization for Logic and Physical Design (2019) (0)
Challenges and targets of MRAM-enabled scaled spintronic logic circuits (2022) (0)
Nano-fabricated memristive biosensors for biomedical applications with liquid and dried samples. (2016) (0)
Multi-Processor System-on-Chip (MPSoC) Thermal Behavior Exploration Based on HW/SW FPGA-Based Emulation (2006) (0)
3-Dimensional Devices: Models and Design Tools (2015) (0)
Memristive Biosensors for PSA-IgM Detection (2015) (0)
Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip (2018) (0)
Master Courses (2003) (0)
1024-Channel Single 5W FPGA Towards High-quality Portable 3D Ultrasound Platform (2017) (0)
Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits (2023) (0)
ScalableGenericLogicSynthesis : One Approach to Rule Them All (2019) (0)
Direct and Catalyst-Free Growth of Vertically-Stacked Graphene-Based Structures for Enhanced Drug Sensing (2019) (0)
Sequencing Graph and Resource Model (1992) (0)
2012 IEEE International Conference on Bioinformatics and Biomedicine Workshops, BIBMW 2012, Philadelphia, USA, October 4-7, 2012 (2012) (0)
New Design Paradigms: New Architectures for New technologies (2007) (0)
Introduction to Implementation Generation (2002) (0)
Dear cas society members (2003) (0)
Deep Learning for Logic Optimization (2017) (0)
Nanosystems for a healthier and safer tomorrow (2010) (0)
Exploratory logic synthesis for multiple independent gate FETs (2018) (0)
Logic Arrays: Theory and Applications (1983) (0)
Networked CAD Systems (1997) (0)
Introduction to Reconfigurable Computing Platforms (2002) (0)
Emerging Technologies for Computing (2017) (0)
ABuffer-sizin gAlgorith mfo rNetwork so nChi pusing TDMA and credit-based end-to-end Flow Control (2006) (0)
Optimal State Assig nment for Finite State Machi nes (1985) (0)
Xor-And-Inverter Graphs for Quantum Compilation (2022) (0)
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits (2023) (0)
Nanosystems for Health and Environment (2013) (0)
The Role of Don't care Conditions (2003) (0)
Lab-on-a-chip implants: a mini laboratory under the skin (2013) (0)
MiGra: A TaskMigration Algorithm forReducing Temperature Gradient inMultiprocessor Systems onChip (2007) (0)
Hardware-software run-time systems and robotics: a case study (1998) (0)
Clinical bioimaging and functional genomics (2006) (0)
Energy-E cient Design ofBattery-Powered Embedded (1999) (0)
Chapter # 16 Energy-efficient system-level design (2002) (0)
Resource Conflict Resolution (1992) (0)
Design and Implementation of NOC based Parallel AES Computation (2020) (0)
2019 DAC Roundtable (2020) (0)
Consolidation, a modern "Moor of Venice" tale (2009) (0)
Inversion Minimization in Majority-Inverter Graphs (2016) (0)
Design Methodologies and CAD Tool Flows for NoCs (2006) (0)
Technology and Know-how Transfer (2008) (0)
Design and Optimization of Quantum Electronic Circuits (2022) (0)
Repeater Insertion Techniques for 3D Interconnects (2010) (0)
Panel: Looking backwards and forwards (2016) (0)
Representatives IEEE Solid-State Circuits Society IEEE Neural Networks Society IEEE Sensors Council (2004) (0)
Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications" (1984) (0)
Timed supersetting and the synthesis of large telescopic units (1998) (0)
Reliable Circuits Design with Nanowire Arrays (2011) (0)
Bioimaging and Clinical Genomics (2006) (0)
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications (2022) (0)
Nanosystems: Technologies and Architectures for Sensing and Computing (2011) (0)
Electronic systems for health management (2015) (0)
Correction to "Optimal State Assignment for Finite State Machines" (1986) (0)
Chapter 9 3 D Network on Chip Topology Synthesis : Designing Custom Topologies for Chip Stacks (2010) (0)
Cyber-Medical Systems: Requirements, Components and Design Examples (2017) (0)
Design and Optimization of Quantum Electronic Circuits (2022) (0)
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization (2023) (0)
3 Advances in Logic Synthesis and Technology Mapping (2019) (0)
Design and Automation for Quantum Computation and Quantum Technologies (2022) (0)
Enhanced wafer matching heuristics for 3-D ICs (2012) (0)
Design Automation for Embedded Systems (Dagstuhl Seminar 9617) (2021) (0)
Nanosystems: Technology, Architectures and Applications (2013) (0)
2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012 (2012) (0)
Integrated biosensors for cell culture monitoring (2014) (0)
Chairs and Committee Members (1997) (0)
Reliable design: a system perspective [Tutorial] (2004) (0)
Memory Effects in Multi-terminal Solid State Devices and Their Applications (2019) (0)
Highly Sensitive Enzymatic MWCNTs-Based Biosensors for Detection of Abiraterone in Human Serum (2017) (0)
Logic synthesis and physical design: Quo vadis? (2011) (0)
On-chip implementation of multiprocessor networks and switch fabrics (2008) (0)
Chapter 7 – NoC Programming (2006) (0)
Single Molecule Biosensors based on Nanogap Devices (2013) (0)
XMG-based Logic Synthesis for Emerging Reconﬁgurable Nanotechnologies (2020) (0)
5-D Integration : A Case Study (0)
CASS Brings Publishing to Its DAC Partnership (2003) (0)
Introduction to Analysis and Estimation (2002) (0)
Internet: services and opportunities in the 21st century (1998) (0)
Logic Optimization of Majority-Inverter Graphs (2019) (0)
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors (2018) (0)
3.5-D integration: A case study (2013) (0)
Health Monitoring (2018) (0)

This paper list is powered by the following services:

Other Resources About Giovanni De Micheli

What Schools Are Affiliated With Giovanni De Micheli?

Giovanni De Micheli is affiliated with the following schools:

Giovanni De Micheli's Academic­Influence.com Rankings