Graham A. Jullien
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Why Is Graham A. Jullien Influential?
(Suggest an Edit or Addition)Graham A. Jullien's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata (2004) (915)
- Residue number system arithmetic: modern applications in digital signal processing (1986) (667)
- A method of majority logic reduction for quantum cellular automata (2004) (400)
- Quantum-dot cellular automata adders (2003) (286)
- A Wireless-Implantable Microsystem for Continuous Blood Glucose Monitoring (2009) (238)
- Design Tools for an Emerging SoC Technology: Quantum-Dot Cellular Automata (2006) (210)
- A linear programming approach to recursive digital filter design with linear phase (1982) (178)
- Residue Number Scaling and Other Operations Using ROM Arrays (1978) (176)
- RAM Design Using Quantum-Dot Cellular Automata (2003) (173)
- Computer arithmetic structures for quantum cellular automata (2003) (161)
- Current-Mirror-Based Potentiostats for Three-Electrode Amperometric Electrochemical Sensors (2009) (160)
- A New Design Technique for Column Compression Multipliers (1995) (151)
- A VLSI implementation of residue adders (1987) (140)
- Theory and applications for a double-base number system (1997) (138)
- Performance comparison of quantum-dot cellular automata adders (2005) (103)
- Circuit design based on majority gates for applications with quantum-dot cellular automata (2004) (99)
- Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms (1980) (96)
- An improved residue-to-binary converter (2000) (79)
- High Level Exploration of Quantum-Dot Cellular Automata (QCA) (2004) (73)
- Fast adders using enhanced multiple-output domino logic (1997) (72)
- Simulation of random cell displacements in QCA (2007) (68)
- Efficient distributed arithmetic based DWT architecture for multimedia applications (2003) (65)
- Two-phase AC electrothermal fluidic pumping in a coplanar asymmetric electrode array (2011) (64)
- An efficient tree architecture for modulo 2n+1 multiplication (1996) (63)
- Digital filter design using genetic algorithm (1998) (62)
- Complexity and Fast Algorithms for Multiexponentiations (2000) (60)
- Simple 4-bit processor based on quantum-dot cellular automata (QCA) (2005) (57)
- Design and fabrication of MEMS-based microneedle arrays for medical applications (2009) (57)
- Complex digital signal processing using quadratic residue number systems (1985) (55)
- Recursive algorithms for the forward and inverse discrete cosine transform with arbitrary length (1994) (53)
- Implementation of FFT Structures Using the Residue Number System (1979) (52)
- An algorithm for multiplication modulo (2/spl and/N-1) (1996) (52)
- High-speed signal processing using systolic arrays over finite rings (1988) (52)
- Design of two-dimensional recursive digital filters using linear programming (1982) (51)
- Efficient techniques for binary-to-multidigit multidimensional logarithmic number system conversion using range-addressable look-up tables (2005) (50)
- A look-up table VLSI design methodology for RNS structures used in DSP applications (1987) (49)
- On decoding techniques for residue number system realizations of digital signal processing hardware (1978) (48)
- Multi-mode operator for SHA-2 hash functions (2007) (46)
- CMOS image sensor with watermarking capabilities (2005) (45)
- Residue number system implementations of number theoretic transforms in complex residue rings (1980) (44)
- A Low-Light CMOS Contact Imager With an Emission Filter for Biosensing Applications (2008) (43)
- A Number System with Continuous Valued Digits and Modulo Arithmetic (2002) (42)
- Loading the bases: a new number representation with applications (2003) (42)
- A new DCT algorithm based on encoding algebraic integers (1998) (42)
- An Algorithm for Modular Exponentiation (1998) (41)
- On Modulus Replication for Residue Arithmetic Computations of Complex Inner Products (1990) (39)
- A very low power CMOS potentiostat for bioimplantable applications (2005) (39)
- Multiplication-free 8×8 2D DCT architecture using algebraic integer encoding (2004) (39)
- The modified quadratic residue number system (MQRNS) for complex high-speed signal processing (1986) (36)
- An efficient bit-level systolic cell design for finite ring digital signal processing applications (1989) (36)
- A 2-digit multidimensional logarithmic number system filterbank for a digital hearing aid architecture (2002) (35)
- Parallel Montgomery multiplication in GF(2/sup k/) using trinomial residue arithmetic (2005) (34)
- Complex digital signal processing over finite rings (1987) (33)
- Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic (1983) (32)
- Large Dynamic Range Computations over Small Finite Rings (1994) (31)
- Number Theoretic Techniques in Digital Signal Processing (1991) (30)
- Error-free computation of Daubechies wavelets for image compression applications (2003) (28)
- Interpolation using the discrete sine transform with increased accuracy (1994) (28)
- A new time distributed DCT architecture for MPEG-4 hardware reference model (2005) (27)
- A low-power DCT IP core based on 2D algebraic integer encoding (2004) (27)
- A reconfigurable digital multiplier architecture (2003) (27)
- The use of the multi-dimensional logarithmic number system in DSP applications (2001) (26)
- PC-based real-time defect imaging system for high-speed web inspection (1993) (26)
- Study on an alternating current electrothermal micropump for microneedle-based fluid delivery systems (2013) (26)
- Vlsi Architectures of Daubechies Wavelet Transforms Using Algebraic Integers (2004) (26)
- Analytical approach to sizing nFET chains (1992) (25)
- Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC) (2004) (25)
- Error-free arithmetic for discrete wavelet transforms using algebraic integers (2003) (25)
- Design of 1-D FIR filters with genetic algorithms (1999) (25)
- A novel pipelined threads architecture for AES encryption algorithm (2002) (24)
- Split current quantum-dot cellular automata-modeling and simulation (2004) (24)
- An algebraic integer based encoding scheme for implementing Daubechies discrete wavelet transforms (2002) (23)
- A high-performance hardware implementation of the H.264 simplified 8/spl times/8 transformation and quantization [video coding] (2005) (23)
- Arithmetic for digital neural networks (1991) (23)
- Fault-tolerant computations over replicated finite rings (2003) (23)
- On the use of hash functions for defect detection in textures for in-camera web inspection systems (2002) (23)
- A hybrid DBNS processor for DSP computation (1999) (23)
- On the Error-Free Realization of a Scaled DCT Algorithm and Its VLSI Implementation (2007) (23)
- High throughput VLSI DSP using replicated finite rings (1996) (22)
- Quantization noise improvement in a hybrid distributed-neuron ANN architecture (2001) (22)
- System-on-chip for real-time applications (2003) (21)
- Dynamic computational blocks for bit-level systolic arrays (1994) (21)
- An In-Camera Data Stream Processing System for Defect Detection in Web Inspection Tasks (1999) (21)
- A new CMOS charge pump for low voltage applications (2005) (21)
- Parallel Montgomery Multiplication in GF(2k) using Trinomial Residue Arithmetic (2004) (21)
- On the use of 4:2 compressors for partial product reduction (2003) (20)
- Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing (2008) (20)
- An Efficient Tree Architecture for Modulo 2 n + 1 Multiplication Journal of VLSI Signal Processing (1996) (20)
- HARDWARE PROTOTYPING FOR THE H.264 4u 4 TRANSFORMATION (2004) (20)
- A 2-digit DBNS filter architecture (2000) (20)
- Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture (2008) (20)
- Woodchuck: a low-level synthesizer for dynamic pipelined DSP arithmetic logic blocks (1992) (19)
- QCADesigner: A CAD Tool for an Emerging Nano-Technology (2003) (19)
- A VLSI array for computing the DFT based on RNS (1986) (19)
- HARDWARE IMPLEMENTATIONS OF VIDEO WATERMARKING (2008) (19)
- Overlap resolution: arithmetic with continuous valued digits in hybrid architectures (1997) (19)
- Hardware prototyping for the H.264 4/spl times/4 transformation [video coding] (2004) (19)
- Near canonic double-based number system (DBNS) with applications in digital signal processing (1996) (19)
- A Low-Power Two-Digit Multi-dimensional Logarithmic Number System Filterbank Architecture for a Digital Hearing Aid (2005) (19)
- 1D autoregressive modeling for defect detection in web inspection systems (1998) (19)
- VLSI WATERMARK IMPLEMENTATIONS AND APPLICATIONS (2008) (19)
- Error-free computation of 8/spl times/8 2D DCT and IDCT using two-dimensional algebraic integer quantization (2005) (18)
- Design of dynamic pass-transistor logic circuits using 123 decision diagrams (1998) (18)
- The generalized discrete W transform and its application to interpolation (1992) (18)
- Multidimensional algebraic-integer encoding for high performance implementation of DCT and IDCT (2003) (18)
- Modeling of drug delivery into tissues with a microneedle array using mixture theory (2010) (18)
- Models for VLSI implementation of residue number system arithmetic modules (1983) (18)
- Hardware implementation of a DCT watermark for CMOS image sensors (2008) (17)
- Digital Multiplication using Continuous Valued Digits (2007) (17)
- New Encoding of 8×8 DCT to make H.264 Lossless (2006) (17)
- Design of 1-D FIR filters with genetic algorithms (1999) (17)
- An Efficient Architecture for a Lifted 2D Biorthogonal DWT (2005) (17)
- Hardware realization of digital signal processing elements using the residue number system. (1977) (17)
- Defect detection in web inspection using fuzzy fusion of texture features (2000) (17)
- Microneedle arrays for drug delivery and fluid extraction (2005) (16)
- A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming (2000) (16)
- A neural-like network approach to finite ring computations (1990) (16)
- Robust low-sensitivity Adaline neuron based on Continuous Valued Number System (2008) (16)
- On efficient techniques for difficult operations in one and two-digit DBNS index calculus (2000) (15)
- A unified synapse-neuron building block for hybrid VLSI neural networks (1996) (15)
- An analysis of Daubechies discrete wavelet transform based on algebraic integer encoding scheme (2002) (14)
- A low-overhead scheme for testing a bit-level finite ring systolic array (1990) (14)
- An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT (2001) (14)
- Implementation of complex number theoretic transforms using quadratic residue number systems (1986) (13)
- A VLSI prototype for Hadamard transform with application to MPEG-4 part 10 (2004) (13)
- Acoustic and magnetic MEMS components for a hearing aid instrument (2000) (13)
- Detection of defects in textures with alignment error for real-time line-scan web inspection systems (2002) (13)
- Performance Comparison of Quantum-dot Cellular (2005) (13)
- Area-time analysis of carry lookahead adders using enhanced multiple output domino logic (1994) (13)
- A full CMOS voltage regulating circuit for bioimplantable applications (2005) (13)
- Arithmetic circuits for analog digits (1999) (13)
- Overlap resolution: continuous valued digits for hybrid architectures (1997) (13)
- A systolic array for fault tolerant digital signal processing using a residue number system approach (1988) (13)
- The application of 2D algebraic integer encoding to a DCT IP core (2003) (13)
- Circuit tolerances and word lengths in overlap resolution (1998) (13)
- Designing near linear phase recursive filters using linear programming (1977) (13)
- On implementing the arithmetic Fourier transform (1992) (13)
- Design and FPGA implementation of systolic FIR filters using the Fermat number ALU (1996) (12)
- High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers (2010) (12)
- A proposed hardware reference model for spatial transformation and quantization in H.264 (2006) (12)
- Arithmetic with signed analog digits (1999) (12)
- An area-time efficient NMOS adder (1983) (12)
- Low-complexity algorithm for fractional-pixel motion estimation (2009) (12)
- Digital filtering using the multidimensional logarithmic number system (2002) (12)
- Sensitivity study and improvements on a nonlinear resistive-type neuron circuit (1999) (12)
- HIGH-DRIVE CMOS BUFFER FOR LARGE CAPACITIVE LOADS (1991) (12)
- Digital arithmetic using analog arrays (1998) (12)
- Wireless temporal artery bandage thermometer (2006) (11)
- Fault-tolerant computation within complex FIR filters (2004) (11)
- A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor (1996) (11)
- High-swing, high-drive CMOS buffer (1995) (11)
- DEVELOPING LEADERSHIP SKILLS FOR (2001) (11)
- Eisenstein residue number system with applications to DSP (1997) (10)
- A modular MEMS electromagnetic actuator for use in a hearing instrument (2000) (10)
- Efficient conversion from binary to multi-digit multi-dimensional logarithmic number systems using arrays of range addressable look-up tables (2002) (10)
- A CMOS Contact Imager for Cell Detection in Bio-Sensing Applications (2007) (10)
- On the way to an H.264 HW/SW reference model: a SystemC modeling strategy to integrate selected IP-blocks with the H.264 software reference model (2005) (9)
- Passive Reduced-Order Macromodeling Algorithm for Microelectromechanical Systems (2008) (9)
- DBNS addition using cellular neural networks (2005) (9)
- Design and VLSI implementation of a unified synapse-neuron architecture (1996) (9)
- A programmable MEMS bandpass filter (2000) (9)
- A simplified approach for designing secure Random Number Generators in HW (2008) (9)
- An array processor for inner product computations using a Fermat number ALU (1995) (9)
- Efficient direct 2D architecture for lifted biorthogonal DWT (2003) (9)
- 16-bit Binary Multiplication Using High Radix Analog Digits (2006) (9)
- Algorithms for multi-exponentiation based on complex arithmetic (1997) (9)
- Application of the residue number system to computer processing of digital signals (1978) (9)
- A programmable intelligent optical sensor realization (1994) (8)
- Optimized delay characteristics for a hearing instrument filter bank (2000) (8)
- A multilevel factorization technique for pass transistor logic (1996) (8)
- A fault-tolerant modulus replication complex FIR filter (2005) (8)
- Micromachined needles for microbiological sample and drug delivery system (2003) (8)
- A proposed hardware structure for two-dimensional recursive digital filters using the residue number system (1985) (8)
- A majority reduction technique for adder structures in quantum-dot cellular (2004) (8)
- Analog digits: bit level redundancy in a binary multiplier (1998) (8)
- Redundant finite rings for fault-tolerant signal processors (1994) (8)
- Computational techniques for least-square design of recursive digital filters (1978) (8)
- Improved cellular structures for bit-steered ROM finite ring systolic arrays (1990) (8)
- A robust hybrid neural architecture for an industrial sensor application (1998) (8)
- Impurity charging in semiconductor quantum-dot cellular automata (2005) (8)
- An efficient VLSI adder for DSP architectures based on RNS (1985) (8)
- A hybrid architecture for feed-forward multi-layer neural networks (1992) (8)
- Fault detection in RNS systolic arrays (1987) (8)
- 16-bit radix-4 continuous valued digit adder (2006) (7)
- Implementation of a Simulation Engine for Clocked Molecular QCA (2006) (7)
- Pipelined analog multi-layer feedforward neural networks (1993) (7)
- VLSI implementations of neural-like networks for finite ring computations (1989) (7)
- A residue number system implementation of real orthogonal transforms (1998) (7)
- A fast and robust RNS algorithm for evaluating signs of determinants (1998) (7)
- An algorithm for multiplication module (2/sup n/+1) (1995) (7)
- Hybrid VLSI architecture of FIR filters using residue number systems (1985) (7)
- Multiple-Base Number System: Theory and Applications (2012) (7)
- A SoC bio-analysis platform for real-time biological cell analysis-on-a-chip (2003) (7)
- A MEMS socket system for high density SoC interconnection (2002) (7)
- Efficient pre-processing algorithms for an FPGA based in-camera video-stream processing system for industry inspection (1997) (7)
- All CMOS low power platform for dielectrophoresis bio-analysis (2005) (7)
- A self-scaling neural hardware structure that reduces the effect of some implementation errors (1997) (6)
- Quantization error and limit cycles analysis in residue number system coded recursive filters (1982) (6)
- VLSI implementations of number theoretic concepts with applications in signal processing (1992) (6)
- Hardware implementation of convolution using number theoretic transforms (1979) (6)
- Digital Arithmetic Using Analog Cellular Neural Networks (1998) (6)
- Nonlinear signal processing using index calculus DBNS arithmetic (2000) (6)
- A MEMS implementation of an acoustical sensor array (2001) (6)
- VLSI prototyping of low-complexity wavelet transform on FPGA (2002) (6)
- Architectures and Building Blocks for Data Stream DSP Processors (1994) (5)
- Algorithms for length 15 and 30 discrete cosine transform (1991) (5)
- Comparisons of four learning algorithms for training the multilayer feedforward neural networks with hard-limiting neurons (1993) (5)
- Comments on "An arithmetic free parallel mixed-radix conversion algorithm" (1999) (5)
- Relationship between two algorithms for discrete cosine transform (1991) (5)
- Fault tolerant computation of large inner products (2001) (5)
- Computation of generalized FIR filter structure using the modified quadratic residue number system (1992) (5)
- Multi-look-up-table module for RNS systems implementation (1984) (5)
- Flexible modulus residue number system for complex digital signal processing (1991) (5)
- Two-Dimensional Transforms Using Number Theoretic Techniques (1996) (5)
- A design flow for an H.264 embedded video encoder (2005) (5)
- A 2-D LNS FIR Filter with a Programmable Second Base Using DRAMs (2003) (5)
- A Low noise CMOS image sensor with an emission filter for fluorescence applications (2008) (5)
- New concepts for the design of carry lookahead adders (1993) (5)
- A B-s complement continuous valued digit adder (2002) (5)
- Systolic ROM arrays for implementing RNS FIR filters (1987) (5)
- An efficient 3-modulus residue to binary converter (1996) (5)
- An Intelligent Optical Sensor (1995) (5)
- Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation (2012) (5)
- BiCMOS current steering pipeline circuit technique (1994) (5)
- VLSI implementation of a digital image threshold selection architecture (1989) (4)
- Error-Free Arithmetic and Architecture for H.264 (2005) (4)
- High Performance VLSI Signal Processing using Multiple Base Representations (2006) (4)
- VLSI digital signal processing: some arithmetic issues (1996) (4)
- Integer mapping architectures for the polynomial ring engine (1993) (4)
- Number 34 (2019) (4)
- Quantization noise improvement in a distributed-neuron architecture (1997) (4)
- An Algorithm for Modular Exponentiation Information Processing (1998) (4)
- High Performance Arithmetic for DSP Systems (1994) (4)
- Self-synchronization of time delay and integration cameras (2004) (4)
- Arithmetic arrays using cellular neural networks (1997) (4)
- Continuous Monitoring of Blood Glucose Concentration using a Fully Implantable Wireless Biomedical Microsystem (2006) (4)
- A wide dynamic range CMOS active pixel sensor with frame difference (2005) (4)
- VLSI improvements in a binary multiplier based on analog digits (1999) (4)
- Self synchronization of time delay and integration (TDI) cameras (2001) (4)
- Implementation of the discrete cosine transform and its inverse by digital filtering (1994) (4)
- A VLSI model for residue number system architectures (1984) (4)
- Array processing on finite polynomial rings (1990) (4)
- An architecture for parallel multipliers (1991) (4)
- Fast algorithm for digital logarithmic conversion (1971) (3)
- Comparisons and Analysis of DCT-based Image Watermarking Algorithms (2008) (3)
- Low velocity arcs under the influence of transverse magnetic fields (1971) (3)
- Fast computation of Chebyshev optimal nonuniform interpolation (1995) (3)
- A high-dynamic range CMOS buffer amplifier with high-drive capability (1992) (3)
- Time distributed DCT architecture for multimedia applications (2003) (3)
- Recursive algorithm for discrete sine transform with regular structure (1994) (3)
- Designing FIR filters with enhanced Fermat ALUs (1999) (3)
- Small moduli replications in the MRRNS (1991) (3)
- On computing Chebyshev optimal nonuniform interpolation (1996) (3)
- A fast VLSI systolic array for large modulus residue addition (1994) (3)
- General purpose FIR filter arrays using optimized redundancy over direct product polynomial rings (1998) (3)
- A hardware realization of an NTT convolver using ROM arrays (1980) (3)
- Robust analog neural network based on continuous valued number system (2008) (3)
- A Tool for Robustness Evaluation of Image Watermarking Algorithms (2008) (3)
- A systolic (VLSI) array using RNS for digital signal processing applications (1984) (3)
- The application of 2-D logarithms to low-power hearing-aid processors (2002) (3)
- A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems (2002) (3)
- A modulo bit-level systolic compiler (1989) (3)
- A VLSI implementation of finite impulse response digital filters using residue number systems (1985) (3)
- Array Processing Using Alternate Arithmetic - A 20 Year Legacy (2006) (3)
- Video-Active RAM: A processor-in-memory architecture for video coding applications (2010) (3)
- On using FPGAS to accelerate the emulation of quantum computing (2009) (3)
- One- and two-dimensional algorithms for length 15 and 30 discrete cosine transforms (1996) (3)
- Sampling reduction for the arithmetic Fourier transform (1989) (3)
- Column Compression Multipliers For Signal Processing Applications (1992) (3)
- Current input TSPC latch for high speed, complex switching trees (1994) (3)
- Computation of complex number theoretic transforms using quadratic residue number systems (1986) (3)
- Modified backpropagation algorithms for training the multilayer feedforward neural networks with hard-limiting neurons (1993) (3)
- A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation (2003) (3)
- A Low-Variation Nonlinear Neuron Circuit (1998) (3)
- Model validation and determination for neural network activation function modeling (1998) (3)
- Very-low-noise switching-free CNN-based adder (1999) (2)
- A high-drive CMOS buffer for high capacitive loads (1991) (2)
- Stability constraints used in computer-aided design of recursive digital filters (1974) (2)
- Passive reduced-order macromodeling algorithm for structure dynamics in MEMS systems (2006) (2)
- [Preliminary note on variations in the EEG of the cat under atmospheric superpressures]. (1953) (2)
- New design environment for defect detection in web inspection systems (1997) (2)
- A VLSI systolic quadratic residue DFT with fault tolerance (1988) (2)
- A Simplified 8 × 8 Transformation and Quantization Real-Time IP-Block for MPEG-4 H.264/AVC Applications: a New Design Flow Approach (2007) (2)
- Neural-based smart CMOS sensors for on-line pattern classification applications (1996) (2)
- Recursive algorithm for the discrete cosine transform with regular structure (1993) (2)
- Efficient fault-tolerant arithmetic using a symmetrical modulus replication RNS (2001) (2)
- Theory and Applications of the Double-Base Number System Submitted to IEEE Transactions on Computers (1998) (2)
- A review of VLSI technologies in digital signal processing (1991) (2)
- A general analysis for the time-invariant multirate digital filter (1973) (2)
- Fault tolerant complex FIR filter architectures using a redundant MRRNS (2001) (2)
- On the Reduction of Interconnect Effects in Deep Submicron Implementations of Digital Multiplication Architectures (2006) (2)
- Rrecursive reduction in finite ring computations (1989) (2)
- VLSI Modular architectures for complex digital signal processing applications (1987) (2)
- An Efficent Variable Block Size Selection Scheme for the H.264 Motion Estimation (2006) (2)
- High-speed web inspection using intelligent TDI cameras (1993) (2)
- On the refinement of the DCT/IDCT scaling factor sensitivity (2008) (2)
- Recursive digital filters in image processing (1978) (2)
- A Fault-Tolerant Complex FIR Filter for SoC Communication Technologies (2007) (2)
- High speed architectures for approximate fixed-point division and square root realization (1989) (2)
- 13 VLSI implementations of number theoretic concepts with applications in signal processing (1993) (2)
- Modeling and Simulation of Micromachined Needles (2003) (2)
- Comparisons and Analysis of Motion Estimation Search Algorithms (2009) (2)
- New architecture for parallel multipliers (1992) (2)
- A high-drive, high-swing buffer amplifier (1991) (2)
- Implementing the arithmetic fourier transform (1989) (2)
- A CRT-Based Montgomery Multiplication for Finite Fields of Small Characteristic (2005) (2)
- Ultra low noise signed digit arithmetic using cellular neural networks (2004) (2)
- Industrial Arc Instrumentation (1969) (2)
- Digital Instrumentation of Slowly Moving Arcs (1970) (2)
- A Camera Simulation Framework for Passive Depth Recovery Systems (2010) (1)
- Reconfigurable systolic architectures for hashing (1990) (1)
- New architectures for systolic hashing (1988) (1)
- A novel approach based on genetic algorithm for pipelining of recursive filters (2001) (1)
- A two-dimensional finite field processor for image filtering (1981) (1)
- A signal processing cell architecture (1987) (1)
- In-camera detection of fabric defects (2004) (1)
- System-on-chip (SoC) technology: the future of VLSI design (2003) (1)
- Proceedings : 11th Symposium on Computer Arithmetic, June 29-July 2, 1993, Windsor, Ontario (1993) (1)
- In-camera video-stream processing for bandwidth reduction in web inspection (1996) (1)
- Method for generating a new optimal nonorthogonal base in signal representation (1992) (1)
- FPGA Implementation of Residue Number System Structures (1995) (1)
- An in-the-loop training method for VLSI neural networks (1999) (1)
- An error anaylsis of a FFT implementation using the residue number system (1978) (1)
- A programmable finite ring bit-level systolic cell (1990) (1)
- A BiCMOS VLSI implementation of an intelligent sensor (1997) (1)
- An improved architecture for column compression multipliers (1992) (1)
- A Mems Socket Interface For Soc Connectivity (2003) (1)
- A method for synthesizing area efficient multilevel PTL circuits (1997) (1)
- VLSI implementations of number theoretic techniques in signal processing (1994) (1)
- Multi-level thresholding using image transformation (1984) (1)
- A MEMS micromagnetic actuator for use in a bionic interface (2000) (1)
- VLSI implementation for real-time extraction of direction vectors from binary images for pattern recognition applications (1993) (1)
- A two-dimensional logarithmic number system (2DLNS)-based Finite Impulse Response (FIR) filter design (2011) (1)
- Multi-level factorisation technique for pass transistor logic (1998) (1)
- A regular recursive algorithm for the discrete sine transform (1993) (1)
- An Optimal Call Admission and Bandwidth Reservation Scheme for Future Wireless Networks (2003) (1)
- In-the-loop training algorithm for neural network implementation with digital weights (1998) (1)
- Comments on "On asymmetrical performance of discrete cosine transform" (1994) (1)
- Neural network integrated circuits with single-block mixed-signal arrays (1997) (1)
- An Enhanced Lenient Merging Scheme for H.264 Variable Block Size Selection (2009) (1)
- A MEMS DNA replicator and sample manipulator (2000) (1)
- A VLSI implementation of an FFT/NTT computational unit (1985) (1)
- A computer program for filter design having arbitrary magnitude specifications in the frequency domain (1973) (1)
- Interconnect effects in deep submicron implementation of high performance arithmetic architectures (2003) (1)
- Bit-level designer's assistant-a knowledge based approach to systolic processor design (1990) (1)
- A residue number system implementation of real orthogonal transforms via approximation over a direct product of quadratic number rings (1996) (1)
- Recursive architectures for 2DLNS multiplication (2010) (1)
- The area-time complexity of a VLSI digital filter using residue number systems (1986) (1)
- An intelligent optical sensor realization (1993) (1)
- A Large-swing High-Drive CMOS Buffer amplifier for a Wide Load Range (1992) (1)
- A pipelined VLSI arithmetic architecture (1992) (1)
- An embedded DRAM for MDLNS FIR filter (2004) (1)
- Area efficient systolic interconnection networks (1996) (1)
- Software techniques for programming a general purpose data flow signal processor (1985) (1)
- Hierarchical pattern extraction for machine perception (1993) (1)
- Crossbar latch-based combinational and sequential logic for nano FPGA (2007) (1)
- A real time general purpose signal processor (1984) (1)
- Fault-Tolerant Computations Over Finite Rings with Applications in Digital Signal Processing (2002) (1)
- The rapid prototyping SoC co-design of a proprietary key agreement protocol (2005) (0)
- A programmable base 2D-LNS MAC with self-generated look-up tables (2004) (0)
- Efficient Design of Logical Structures and functions using Nanotechnology Based Quantum Dot Cellular Automata Design (2016) (0)
- High-speed web inspection using intelligent time delay and integration (TDI) cameras (1994) (0)
- Design and Performance Analysis of Low Power Multipliers (2020) (0)
- On the Use of Hash Functions as Preprocessing Algorithms to Detect Defects on Repeating Definite Textures (2006) (0)
- Digital Signal Processing : Some Arithmetic Issues (1996) (0)
- Split current quantum cellular automata: device and logic gates (2004) (0)
- Homogeneous VLSI Structures for Finite Ring Computations (1988) (0)
- Recursive cellular nonlinear neural networks for ultra-low noise digital arithmetic (2003) (0)
- Fast Modular Reduction for a Large Class of Moduli (2004) (0)
- Analysis of microprocessor-based digital filters (1986) (0)
- On the use of animated sequences for pedagogical enhancement (1995) (0)
- Implementation of the generalized FIR filter structure using the residue arithmetic (1987) (0)
- Memory architecture of a video-rate image convolver (1982) (0)
- Error Recovery in Continuous Valued Number System (2011) (0)
- A New Efficient Residue to Binary Converter for (5n+2)-bit Dynamic Range Moduli Set (2019) (0)
- Image recognition using a growing-cell-based neural network (1997) (0)
- RAM-JET: Towards The Removal Of Multiplicative Compleidty In Digital Signal Processingvlst Arclutectures (1988) (0)
- Detection of late potentials in electrocardiogram signals using artificial neural networks (2000) (0)
- A regular recursive algorithm for the discrete sine transform (1994) (0)
- Biochip for minimally invasive blood glucose monitoring (2009) (0)
- VLSI design of optically coupled neural networks (1989) (0)
- Parallel median filtering using cellular neural networks (1996) (0)
- Special Issue on Systems-on-Chip: Design and Integration (2006) (0)
- Area Efficient VLSI Design with Cells of Controllable Complexity (1993) (0)
- Fast RNS algorithm for computational geometry problems (2001) (0)
- SYSTEM IDENTIFICATION USING FOKKER-PLANCK TECHNIQUES. (1974) (0)
- on Algebraic Integer Encoding Scheme (2002) (0)
- The design and training of an intelligent sensor implementation (1993) (0)
- Investigations into practical closed-loop arc control systems (1969) (0)
- VLSI implementation of high throughput DSP using finite ring arithmetic (1995) (0)
- Error analysis of data mapping using 2-dimensional logarithmic number systems (2005) (0)
- Technology, Applications, and Computation (2017) (0)
- SIGNAL PROCESSING OPERATIONS IN ROBOTIC VISION. (1983) (0)
- The Modulus Replication RNS (MRRNS): A Comparative Study (1990) (0)
- VLSI Implementation of Complex Digitial Signal Processing Structures (1986) (0)
- The implementation of the generalized Lagrange FIR filter structure defined over finite fields or rings (1986) (0)
- Jfi(ton New OrCeans CJQverside, New Or(eans, Louisiana, VS)I PRELIMINARY CALL FOR PAPERS (2007) (0)
- An applicative framework for video-rate systems programming (1995) (0)
- A fast model-order reduction algorithm for microelectromechanical devices (2007) (0)
- SoC - what are our technology futures? (2006) (0)
- A Method for Nonasymptotic Performance Analyses of Array Signal Processing Algorithms (1994) (0)
- Proceedings of the 8th Great Lakes Symposium on VLSI : Hotel Acadiana Lafayette, Louisiana February 19-21, 1998 (1998) (0)
- An algorithm for in-the-loop training based on activation function derivative approximation (1998) (0)
- New perimeter sorting network (1992) (0)
- Future Special Issues/Special Sections of the Proceedings (2018) (0)
- Multiplication-free architecture for Daubechies wavelet transforms using algebraic integers (2003) (0)
- Clock Distribution in RNS-based VLSI Systems (2002) (0)
- Contraharmonic filtering using cellular neural networks (1996) (0)
- A switched gate synaptic weighting circuit for optically coupled neural networks (1992) (0)
- Introduction to the Special Issue on Computer Arithmetic (1994) (0)
- ImplementationofFFT Structures Usingthe ResidueNumber System (1979) (0)
- 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings (1993) (0)
- A programmable AC electrokinetic analysis system (2004) (0)
- Electrical and Computer Engineering Fault Tolerant Computation of Large Inner Products Submitted to Electronics Letters (2001) (0)
- Error analysis of FIR filters implemented with 1-digit 2-dimensional logarithmic number systems (2005) (0)
- An accurate fixed-point 8×8 IDCT algorithm based on 2D algebraic integer representation (2007) (0)
- Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors, July 10-12, 2000, Boston, Massachusetts (2000) (0)
- Multidimensional Logarithmic Number System (2006) (0)
- Implementation considerations in the Polynomial Ring Engine (1992) (0)
- Computing with Quantum‐Dot Cellular Automata (2009) (0)
- Homogeneous VLSI Structures For High Speed Digital Signal Processing Using Number Theoretic Techniques (1989) (0)
- A programmable base MDLNS MAC with self-generated lookup table (2004) (0)
- ROBOT VISION APPLICATION TO PARTS INSPECTION. (1982) (0)
- Modeling and simulation of a monolithic self-actuated microsystem for fluid sampling and drug delivery (2008) (0)
- Efficient Variable Block Size Selection for AVC Low Bitrate Applications (2010) (0)
- VLSI Neural System Architecture for Finite Ring Recursive Reduction (1996) (0)
- A pipelined neural computer for hierarchical pattern recognition (1994) (0)
- Homogeneous VLSI for 2-D digital signal processing (1989) (0)
- Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation (2010) (0)
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