H.-S. Philip Wong
#106,048
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Professor of electrical engineering
H.-S. Philip Wong's AcademicInfluence.com Rankings
H.-S. Philip Wongengineering Degrees
Engineering
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Electrical Engineering
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Engineering
H.-S. Philip Wong's Degrees
- PhD Electrical Engineering Stanford University
- Masters Electrical Engineering Stanford University
- Bachelors Electrical Engineering Stanford University
Why Is H.-S. Philip Wong Influential?
(Suggest an Edit or Addition)According to Wikipedia, H.-S. Philip Wong is the Willard R. and Inez Kerr Bell professor in the School of Engineering, Professor of Electrical Engineering at Stanford University. He is a Chinese-American electrical engineer whose career centers on nanotechnology, microelectronics, and semiconductor technology.
H.-S. Philip Wong's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Metal–Oxide RRAM (2012) (1967)
- Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing. (2012) (1004)
- MoS2 transistors with 1-nanometer gate lengths (2016) (934)
- Phase Change Memory (2010) (889)
- CMOS scaling into the nanometer regime (1997) (875)
- Carbon nanotube computer (2013) (822)
- A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region (2007) (776)
- A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking (2007) (697)
- Beyond the conventional transistor (2002) (636)
- An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation (2011) (613)
- Face classification using electronic synapses (2017) (598)
- Optoelectronic resistive random access memory for neuromorphic vision sensors (2019) (473)
- The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance (2005) (376)
- Electronic synapses made of layered two-dimensional materials (2018) (361)
- Conduction mechanism of TiN/HfOx/Pt resistive switching memory: A trap-assisted-tunneling model (2011) (324)
- Artificial optic-neural synapse for colored and color-mixed pattern recognition (2018) (306)
- On the Switching Parameter Variation of Metal-Oxide RRAM—Part I: Physical Modeling and Simulation Methodology (2012) (301)
- HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. (2013) (293)
- Carbon Nanotube and Graphene Device Physics (2011) (284)
- Technology and device scaling considerations for CMOS imagers (1996) (264)
- Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory (2011) (256)
- Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies (2010) (246)
- Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's (1993) (224)
- Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM) (2011) (209)
- A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations (2012) (199)
- Phase-Change Memory—Towards a Storage-Class Memory (2017) (197)
- Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes (2009) (194)
- Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics (2018) (193)
- A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors. (2008) (192)
- On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy (2012) (190)
- On the stochastic nature of resistive switching in metal oxide RRAM: Physical modeling, monte carlo simulation, and experimental characterization (2011) (187)
- A Phenomenological Model for the Reset Mechanism of Metal Oxide RRAM (2010) (185)
- Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array (2014) (181)
- Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model (1998) (180)
- A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling (2012) (179)
- Energy-Efficient Abundant-Data Computing: The N3XT 1,000x (2015) (165)
- Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems. (2014) (161)
- Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application (2009) (158)
- CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes. (2009) (154)
- Design Considerations for Complementary Nanoelectromechanical Logic Gates (2007) (150)
- Stochastic learning in oxide binary synaptic device for neuromorphic computing (2013) (142)
- A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements (2015) (135)
- Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections (2007) (134)
- HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector (2012) (132)
- A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification (2016) (131)
- Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2. (2016) (131)
- Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics (2010) (130)
- Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits (2009) (130)
- Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs (2014) (128)
- Removable and Recyclable Conjugated Polymers for Highly Selective and High-Yield Dispersion and Release of Low-Cost Carbon Nanotubes. (2016) (126)
- CMOS scaling into the 21st century: 0.1 µm and beyond (1995) (125)
- Variability in carbon nanotube transistors: improving device-to-device consistency. (2012) (121)
- Thickness and stoichiometry dependence of the thermal conductivity of GeSbTe films (2007) (120)
- Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits (2008) (117)
- Crystallization times of Ge–Te phase change materials as a function of composition (2009) (117)
- $\hbox{Al}_{2}\hbox{O}_{3}$-Based RRAM Using Atomic Layer Deposition (ALD) With 1-$\mu\hbox{A}$ RESET Current (2010) (115)
- Large‐Area Assembly of Densely Aligned Single‐Walled Carbon Nanotubes Using Solution Shearing and Their Application to Field‐Effect Transistors (2015) (115)
- Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels (2007) (115)
- Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer (2012) (113)
- Impact of a Process Variation on Nanowire and Nanotube Device Performance (2007) (113)
- Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode. (2013) (111)
- Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes (2019) (109)
- SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors (2001) (106)
- Flexible Control of Block Copolymer Directed Self‐Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning (2012) (106)
- Thermal Boundary Resistance Measurements for Phase-Change Memory Devices (2010) (106)
- High-Performance p-Type Black Phosphorus Transistor with Scandium Contact. (2016) (104)
- Verilog-A compact model for oxide-based resistive random access memory (RRAM) (2014) (103)
- Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier. (2015) (102)
- Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology. (2014) (101)
- Carbon Nanotube Robust Digital VLSI (2012) (100)
- A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors (2006) (99)
- Ultrafast characterization of phase-change material crystallization properties in the melt-quenched amorphous phase. (2014) (97)
- Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study (2018) (97)
- Selective synthesis and device applications of semiconducting single-walled carbon nanotubes using isopropyl alcohol as feedstock. (2012) (96)
- A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization (2015) (96)
- VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs (2009) (93)
- Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition (2016) (92)
- High Current Density and Low Thermal Conductivity of Atomically Thin Semimetallic WTe2. (2016) (90)
- TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits (2015) (86)
- Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs (2009) (84)
- High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms (2011) (84)
- Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic (2008) (82)
- Carbon nanotube field effect transistors for logic applications (2001) (81)
- Efficient FPGAs using nanoelectromechanical relays (2010) (81)
- Low-Energy Robust Neuromorphic Computation Using Synaptic Devices (2012) (80)
- Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length (2013) (79)
- Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures (2015) (78)
- Metal/III-V Schottky barrier height tuning for the design of nonalloyed III-V field-effect transistor source/drain contacts (2010) (77)
- Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage (2009) (76)
- Linear increases in carbon nanotube density through multiple transfer technique. (2011) (76)
- Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon (2011) (75)
- Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model (2015) (74)
- Distinctive in-Plane Cleavage Behaviors of Two-Dimensional Layered Materials. (2016) (73)
- Forming-free nitrogen-doped AlOX RRAM with sub-μA programming current (2011) (72)
- Carbon nanomaterials for non-volatile memories (2018) (71)
- Carbon nanotube circuit integration up to sub-20 nm channel lengths. (2014) (70)
- An Ultra-Low Reset Current Cross-Point Phase Change Memory With Carbon Nanotube Electrodes (2012) (70)
- Phonon and electron transport through Ge2Sb2Te5 films and interfaces bounded by metals (2013) (69)
- Ternary content-addressable memory with MoS2 transistors for massively parallel data search (2019) (69)
- Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes (2011) (65)
- Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI (2018) (64)
- Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays (2010) (63)
- Resistive RAM-Centric Computing: Design and Modeling Methodology (2017) (62)
- Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET'S (1994) (61)
- Device and circuit optimization of RRAM for neuromorphic computing (2017) (61)
- Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes (2008) (60)
- Resistance and Threshold Switching Voltage Drift Behavior in Phase-Change Memory and Their Temperature Dependence at Microsecond Time Scales Studied Using a Micro-Thermal Stage (2011) (60)
- Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing (2016) (59)
- Experimental demonstration of high mobility Ge NMOS (2009) (59)
- Energy efficient programming of nanoelectronic synaptic devices for large-scale implementation of associative and temporal sequence learning (2011) (59)
- AlOx-Based Resistive Switching Device with Gradual Resistance Modulation for Neuromorphic Device Application (2012) (59)
- VLSI-compatible carbon nanotube doping technique with low work-function metal oxides. (2014) (58)
- Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures (2008) (58)
- Analytical ballistic theory of carbon nanotube transistors: Experimental validation, device physics, parameter extraction, and performance projection (2008) (58)
- Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling (2007) (58)
- Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits (2007) (57)
- A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects (2009) (56)
- Frequency response of top-gated carbon nanotube field-effect transistors (2004) (56)
- Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs (2014) (55)
- Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array (2013) (55)
- Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution. (2016) (55)
- Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit (2011) (54)
- Nanoscale phase change memory materials. (2012) (54)
- The Effect of Donor/Acceptor Nature of Interface Traps on Ge MOSFET Characteristics (2011) (54)
- Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement (2010) (54)
- 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation (2013) (53)
- Carbon nanotube field effect transistors - fabrication, device physics, and circuit implications (2003) (53)
- First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier (2006) (53)
- Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library (2013) (53)
- A Monte Carlo study of the low resistance state retention of HfOx based resistive switching memory (2012) (53)
- Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks. (2012) (52)
- 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models (2020) (51)
- Analysis of Temperature in Phase Change Memory Scaling (2007) (51)
- Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions (2009) (51)
- Current Scaling in Aligned Carbon Nanotube Array Transistors With Local Bottom Gating (2010) (49)
- Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications (2008) (49)
- High performance double-gate device technology challenges and opportunities (2002) (49)
- In Situ Tuning of Switching Window in a Gate‐Controlled Bilayer Graphene‐Electrode Resistive Memory Device (2015) (49)
- Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration (2008) (48)
- On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators (2019) (48)
- Investigation of the Performance Limits of III-V Double-Gate n-MOSFETs (2005) (47)
- Electronic and optical switching of solution-phase deposited SnSe2 phase change memory material (2011) (47)
- An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes (2008) (47)
- Experimental demonstration of array-level learning with phase change synaptic devices (2013) (46)
- Fast Spiking of a Mott VO2-Carbon Nanotube Composite Device. (2019) (46)
- Impact of fixed charge on metal-insulator-semiconductor barrier height reduction (2011) (46)
- Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration (2018) (46)
- In situ transmission electron microscopy observation of nanostructural changes in phase-change memory. (2011) (45)
- Nanometer-Scale ${\rm HfO}_{x}$ RRAM (2013) (45)
- A 1.4µA reset current phase change memory cell with integrated carbon nanotube electrodes for cross-point memory application (2011) (45)
- SRAM, NAND, DRAM contact hole patterning using block copolymer directed self-assembly guided by small topographical templates (2011) (45)
- Picosecond Electric-Field-Induced Threshold Switching in Phase-Change Materials. (2016) (45)
- Characterization of switching parameters and multilevel capability in HfOx/AlOx bi-layer RRAM devices (2011) (44)
- Hysteresis-Free Carbon Nanotube Field-Effect Transistors. (2017) (44)
- Nanoelectromechanical relays with decoupled electrode and suspension (2011) (43)
- Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET (2008) (43)
- An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory (2007) (43)
- Monolithic 3D integration: A path from concept to reality (2015) (42)
- Analysis of the Frequency Response of Carbon Nanotube Transistors (2006) (42)
- Phase change nanodot arrays fabricated using a self-assembly diblock copolymer approach (2007) (42)
- Design and optimization methodology for 3D RRAM arrays (2013) (42)
- ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration (2009) (41)
- Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations (2015) (41)
- A general design strategy for block copolymer directed self-assembly patterning of integrated circuits contact holes using an alphabet approach. (2015) (41)
- Ultralow–switching current density multilevel phase-change memory on a flexible substrate (2021) (41)
- Effect of annealing ambient and temperature on the electrical characteristics of atomic layer deposition Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and MOSFETs (2012) (41)
- Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications (2010) (41)
- Contact-hole patterning for random logic circuits using block copolymer directed self-assembly (2012) (40)
- Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance (2011) (40)
- Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations (2011) (39)
- Metal/III-V effective barrier height tuning using atomic layer deposition of high-κ/high-κ bilayer interfaces (2011) (39)
- Understanding metal oxide RRAM current overshoot and reliability using Kinetic Monte Carlo simulation (2012) (39)
- Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts. (2018) (39)
- Ultrafast terahertz-induced response of GeSbTe phase-change materials (2014) (39)
- The Role of Ti Capping Layer in HfOx-Based RRAM Devices (2014) (38)
- Ultralow Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches (2009) (38)
- Design strategy of small topographical guiding templates for sub-15nm integrated circuits contact hole patterns using block copolymer directed self assembly (2013) (38)
- Combinational Logic Design Using Six-Terminal NEM Relays (2013) (37)
- Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection (2011) (37)
- Block copolymer directed self-assembly enables sublithographic patterning for device fabrication (2012) (37)
- Ultra-low power Al2O3-based RRAM with 1μA reset current (2010) (37)
- Laterally Actuated Platinum-Coated Polysilicon NEM Relays (2013) (37)
- Universal Selective Dispersion of Semiconducting Carbon Nanotubes from Commercial Sources Using a Supramolecular Polymer. (2017) (36)
- Engineering thermal and electrical interface properties of phase change memory with monolayer MoS2 (2019) (36)
- CMOS image sensors-recent advances and device scaling considerations (1997) (36)
- Fabrication and Characterization of Carbon Nanotube Interconnects (2007) (35)
- High-performance carbon nanotube field-effect transistors (2014) (35)
- All-Metal-Nitride RRAM Devices (2015) (35)
- Neuromorphic architectures with electronic synapses (2016) (34)
- Monolithic three-dimensional integration of carbon nanotube FET complementary logic circuits (2013) (34)
- The Trojan-proof chip (2015) (34)
- Spatial Separation of Carrier Spin by the Valley Hall Effect in Monolayer WSe2 Transistors. (2019) (33)
- Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs (2013) (33)
- Dispersion of High‐Purity Semiconducting Arc‐Discharged Carbon Nanotubes Using Backbone Engineered Diketopyrrolopyrrole (DPP)‐Based Polymers (2016) (33)
- Thermal disturbance and its impact on reliability of phase-change memory studied by the micro-thermal stage (2010) (33)
- AC conductance measurement and analysis of the conduction processes in HfOx based resistive switching memory (2011) (33)
- Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits (2010) (32)
- Characterization of low-frequency noise in the resistive switching of transition metal oxide HfO 2 (2012) (32)
- A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT) (2006) (32)
- Biomimetic Approaches for Fabricating High-Density Nanopatterned Arrays (2007) (31)
- Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell (2019) (31)
- Vertical and Lateral Copper Transport through Graphene Layers. (2015) (31)
- Efficient metallic carbon nanotube removal for highly-scaled technologies (2015) (31)
- Graphene Interconnect Lifetime: A Reliability Analysis (2012) (31)
- Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique (2012) (31)
- Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap (2009) (30)
- Carrier density and quantum capacitance for semiconducting carbon nanotubes (2008) (30)
- Scaling properties of phase change materials (2007) (30)
- Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling (2006) (30)
- Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective (2012) (30)
- Carbon nanotube circuits: Living with imperfections and variations (2010) (30)
- Exceeding Nernst limit (59mV/pH): CMOS-based pH sensor for autonomous applications (2012) (30)
- ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines (2010) (30)
- Assembly and Electrical Characterization of Multiwall Carbon Nanotube Interconnects (2008) (30)
- Nanoscale CMOS : Special issue on quantum devices and their applications (1999) (29)
- Uniaxial Stress Engineering for High-Performance Ge NMOSFETs (2010) (29)
- Phase Change Nanodots Patterning using a Self-Assembled Polymer Lithography and Crystallization Analysis (2008) (28)
- Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities (2006) (28)
- Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network (2017) (28)
- Understanding the switching mechanism of interfacial phase change memory (2019) (28)
- 1D Selection Device Using Carbon Nanotube FETs for High-Density Cross-Point Memory Arrays (2015) (27)
- Integration of Nanoelectromechanical Relays With Silicon nMOS (2012) (27)
- Directed Self-Assembly (DSA) Template Pattern Verification (2014) (27)
- High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz (2009) (26)
- Complex Band Structures: From Parabolic to Elliptic Approximation (2011) (26)
- COMPOSITE POLYSILICON-PLATINUM LATERAL NANOELECTROMECHANICAL RELAYS (2010) (26)
- Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects (2009) (26)
- Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS (2014) (25)
- Computational simulation of block copolymer directed self-assembly in small topographical guiding templates (2013) (25)
- 14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques (2019) (25)
- DSA-aware detailed routing for via layer optimization (2014) (25)
- Atomic layer deposition of high-k dielectrics on single-walled carbon nanotubes: a Raman study (2013) (25)
- Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length. (2019) (24)
- NiO resistance change memory with a novel structure for 3D integration and improved confinement of conduction path (2006) (24)
- Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory (2017) (24)
- Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe (2007) (24)
- Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses (2017) (23)
- Measuring Frequency Response of a Single-Walled Carbon Nanotube Common-Source Amplifier (2009) (23)
- Transient dynamics of NbOx threshold switches explained by Poole-Frenkel based thermal feedback mechanism (2018) (23)
- Integrating Phase-Change Memory Cell With Ge Nanowire Diode for Crosspoint Memory—Experimental Demonstration and Analysis (2008) (23)
- 32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance (2016) (23)
- Beyond the Conventional MOSFET (2001) (23)
- Ultrathin (∼2nm) HfOx as the fundamental resistive switching element: Thickness scaling limit, stack engineering and 3D integration (2014) (23)
- Electrostatic analysis of carbon nanotube arrays (2003) (23)
- High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning (2019) (22)
- Thermal conductivity measurement of amorphous dielectric multilayers for phase-change memory power reduction (2016) (22)
- BEOL compatible graphene/Cu with improved electromigration lifetime for future interconnects (2016) (21)
- Noniterative Compact Modeling for Intrinsic Carbon-Nanotube FETs: Quantum Capacitance and Ballistic Transport (2011) (21)
- Electrothermal Modeling and Design Strategies for Multibit Phase-Change Memory (2012) (21)
- An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements. (2010) (20)
- Scaling silicon MOS devices to their limits (1996) (20)
- A Physics-Based Compact Model of III–V FETs for Digital Logic Applications: Current–Voltage and Capacitance–Voltage Characteristics (2009) (20)
- Nanoelectromechanical Logic and Memory Devices (2009) (20)
- Monolithic 3D integration advances and challenges: From technology to system levels (2014) (20)
- Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit (2009) (19)
- Diblock copolymer directed self-assembly for CMOS device fabrication (2006) (19)
- Resistive switching AlOx-based memory with CNT electrode for ultra-low switching current and high density memory application (2011) (19)
- Monolithic integration of CMOS VLSI and CNT for hybrid nanotechnology applications (2008) (19)
- Metal-induced dopant (boron and phosphorus) activation process in amorphous germanium for monolithic three-dimensional integration (2009) (19)
- Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies (2016) (19)
- Electrode/oxide interface engineering by inserting single-layer graphene: Application for HfOx-based resistive random access memory (2012) (19)
- A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing (2020) (19)
- Design considerations of synaptic device for neuromorphic computing (2014) (19)
- Write disturb analyses on half-selected cells of cross-point RRAM arrays (2014) (19)
- Atomically thin graphene plane electrode for 3D RRAM (2014) (19)
- Effect of thermal insulation on the electrical characteristics of NbOx threshold switches (2018) (19)
- Phase Change Memory: Scaling and applications (2012) (18)
- Scaling the CBRAM Switching Layer Diameter to 30 nm Improves Cycling Endurance (2018) (18)
- 3-D Cross-Point Array Operation on ${\rm AlO}_{y}/{\rm HfO}_{x}$ -Based Vertical Resistive Switching Memory (2014) (18)
- Carbon nanotube transistor compact model for circuit design and performance optimization (2008) (18)
- Cu diffusion barrier: Graphene benchmarked to TaN for ultimate interconnect scaling (2015) (18)
- Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters (2008) (18)
- 1D thickness scaling study of phase change material (Ge2Sb2Te5) using a pseudo 3-terminal device (2009) (18)
- Cross plane thermal conductance of graphene-metal interfaces (2014) (17)
- 3-D Resistive Memory Arrays: From Intrinsic Switching Behaviors to Optimization Guidelines (2015) (17)
- Air-stable technique for fabricating n-type carbon nanotube FETs (2011) (17)
- Modeling and Performance Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and Screening Effect (2008) (17)
- DSA template optimization for contact layer in 1D standard cell design (2014) (17)
- Investigation of the performance limits of III-V double-gate n-MOSFETs (2005) (17)
- Grain Boundaries, Phase Impurities, and Anisotropic Thermal Conduction in Phase-Change Memory (2011) (17)
- Crystallization properties and their drift dependence in phase-change memory studied with a micro-thermal stage (2011) (16)
- High quality GeO2/Ge interface formed by SPA radical oxidation and uniaxial stress engineering for high performance Ge NMOSFETs (2006) (16)
- Design guidelines for 3D RRAM cross-point architecture (2014) (16)
- Localized Triggering of the Insulator-Metal Transition in VO2 Using a Single Carbon Nanotube. (2019) (16)
- Rapid exploration of processing and design guidelines to overcome carbon nanotube variations (2013) (16)
- CMOS technology roadmap projection including parasitic effects (2009) (15)
- Resistive switching of carbon-based RRAM with CNT electrodes for ultra-dense memory (2010) (15)
- Carbon nanotube circuits: Opportunities and challenges (2013) (15)
- Improved Performance of Bottom-Contact Organic Thin-Film Transistor Using Al Doped HfO2 Gate Dielectric (2014) (14)
- 2D molybdenum disulfide (MoS2) transistors driving RRAMs with 1T1R configuration (2017) (14)
- Microsecond transient thermal behavior of HfOx-based resistive random access memory using a micro thermal stage (MTS) (2016) (14)
- Ultra-Low Power Ni/HfO2/TiOx/TiN Resistive Random Access Memory With Sub-30-nA Reset Current (2015) (14)
- Nanoscale CMOS - Proceedings of the IEEE (1999) (14)
- One-Dimensional Thickness Scaling Study of Phase Change Material $(\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5})$ Using a Pseudo 3-Terminal Device (2011) (14)
- Experimental demonstration of In0.53Ga0.47As field effect transistors with scalable nonalloyed source/drain contacts (2011) (14)
- Beyond-CMOS Technologies for Next Generation Computer Design (2018) (14)
- Temperature-dependent studies of the electrical properties and the conduction mechanism of HfOx-based RRAM (2014) (14)
- Contact pitch and location prediction for Directed Self-Assembly template verification (2015) (14)
- Synthesis of metal chalcogenide nanodot arrays using block copolymer-derived nanoreactors. (2007) (14)
- Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays (2014) (13)
- Graphitic interfacial layer to carbon nanotube for low electrical contact resistance (2010) (13)
- A Density Metric for Semiconductor Technology [Point of View] (2020) (13)
- “Universal” effective mobility of empirical local mobility models for n- and p-channel silicon MOSFETs (1993) (13)
- Recent progress of resistive switching random access memory (RRAM) (2012) (13)
- The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology (2007) (13)
- Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes (2012) (13)
- Microthermal Stage for Electrothermal Characterization of Phase-Change Memory (2011) (13)
- Performance Prediction of Large-Scale 1S1R Resistive Memory Array Using Machine Learning (2015) (12)
- Modeling and design optimization of ReRAM (2015) (12)
- Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM) (2010) (12)
- Gate capacitance optimization for arrays of carbon nanotube field-effect transistors (2003) (12)
- Modeling Carbon Nanotube Sensors (2007) (12)
- Carbon Nanotube Quantum Capacitance for Nonlinear Terahertz Circuits (2009) (12)
- Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters (2010) (12)
- Modeling of schottky and ohmic contacts between metal and graphene nanoribbons using extended hückel theory (EHT)-based NEGF method (2008) (12)
- Physics-Based Compact Model for III–V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic Capacitance (2011) (12)
- Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays (2015) (12)
- Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture (2019) (12)
- A phenomenological model of oxygen ion transport for metal oxide resistive switching memory (2010) (11)
- High performance, integrated 1T1R oxide-based oscillator: Stack engineering for low-power operation in neural network applications (2015) (11)
- Sub-200 Ω·µm Alloyed Contacts to Synthetic Monolayer MoS2 (2021) (11)
- Sacha: The stanford carbon nanotube controlled handshaking robot (2013) (11)
- Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAM (2018) (11)
- Monolithic 3-D Integration (2019) (11)
- CMOS process compatible directed block copolymer self-assembly for 20nm contact holes and beyond (2010) (11)
- Titanium nitride sidewall stringer process for lateral nanoelectromechanical relays (2010) (11)
- First demonstration of RRAM patterned by block copolymer self-assembly (2013) (11)
- Surface Science of Catalyst Dynamics for Aligned Carbon Nanotube Synthesis on a Full-Scale Quartz Wafer (2009) (11)
- Physics-based compact model of III-V heterostructure FETs for digital logic applications (2008) (11)
- Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part I: Accurate and Computationally Efficient Modeling (2019) (11)
- Fabrication and Characterization of Nanoscale NiO Resistance Change Memory (RRAM) Cells With Confined Conduction Paths (2011) (11)
- Improved multi-level control of RRAM using pulse-train programming (2014) (11)
- Investigation of Trap Spacing for the Amorphous State of Phase-Change Memory Devices (2011) (11)
- Thermoelectric Characterization and Power Generation Using a Silicon-on-Insulator Substrate (2012) (10)
- Effect of Parasitic Resistance and Capacitance on Performance of InGaAs HEMT Digital Logic Circuits (2009) (10)
- Technology Assessment Methodology for Complementary Logic Applications Based on Energy–Delay Optimization (2011) (10)
- Statistical assessment methodology for the design and optimization of cross-point RRAM arrays (2014) (10)
- RRAM based synaptic devices for neuromorphic visual systems (2015) (10)
- System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits (2014) (10)
- First demonstration of phase change memory device using solution processed GeTe nanoparticles (2011) (10)
- 3D nanosystems enable embedded abundant-data computing: special session paper (2017) (10)
- Analog Nanoelectromechanical Relay With Tunable Transconductance (2009) (10)
- Dual sidewall lateral nanoelectromechanical relays with beam isolation (2011) (10)
- Nano-engineered architectures for ultra-low power wireless body sensor nodes (2016) (10)
- Energy-Reversible Complementary NEM Logic Gates (2008) (10)
- Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated (2011) (10)
- Design strategy for integrating DSA via patterning in sub-7 nm interconnects (2016) (9)
- Computing with Carbon Nanotubes (2016) (9)
- Thermal characterization of nanostructured superlattices of TiN/TaN: Applications as electrodes in Phase Change Memory (2014) (9)
- In-Situ Grown Graphene Enabled Copper Interconnects With Improved Electromigration Reliability (2019) (9)
- Generalized Phase Change Memory Scaling Rule Analysis (2006) (9)
- Imperfection-Immune Carbon Nanotube VLSI Circuits (2011) (9)
- Numerical and analytical simulations of suspended gate - FET for ultra-low power inverters (2007) (8)
- Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering (2008) (8)
- A Physics-Based Compact Model for CBRAM Retention Behaviors Based on Atom Transport Dynamics and Percolation Theory (2019) (8)
- Carbon Nanotube Device Modeling and Circuit Simulation (2009) (8)
- Low-power, high-performance S-NDR oscillators for stereo (3D) vision using directly-coupled oscillator networks (2016) (8)
- Analytical Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass, Carrier Density, and Quantum Capacitance (2007) (8)
- Illusion of large on-chip memory by networked computing chips for neural network inference (2021) (8)
- On the Variability of HfOx RRAM: From Numerical Simulation to Compact Modeling (2012) (8)
- Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi₂Te₃ Thermoelectric Interfacial Layer (2020) (8)
- Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM) (2017) (8)
- Fabrication of ultrathin, highly uniform thin-film SOI MOSFETs with low series resistance using pattern-constrained epitaxy (1997) (8)
- Integrating Graphene into Future Generations of Interconnect Wires (2018) (7)
- Exploration of Device Design Space to Meet Circuit Speed Targeting 22nm and Beyond (2009) (7)
- Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits (2016) (7)
- Laterally actuated nanoelectromechanical relays with compliant, low resistance contact (2013) (7)
- Synaptic Devices Based on Phase-Change Memory (2017) (7)
- Recent Progress of Phase Change Memory (PCM) and Resistive Switching Random Access Memory (RRAM) (2011) (7)
- Decoupled thermal resistances of phase change material and their impact on PCM devices (2010) (7)
- Fabrication and characterization of emerging nanoscale memory (2009) (6)
- 1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect (2007) (6)
- Technology Projection Using Simple Compact Models (2009) (6)
- Spectroscopic Evidence for Exceptional Thermal Contribution to Electron Beam-Induced Fragmentation (2010) (6)
- Intrinsic limits of leakage current in self-heating-triggered threshold switches (2019) (6)
- Dual-Layer Dielectric Stack for Thermally-Isolated Low-Power Phase-Change Memory (2017) (6)
- Analytical approximation of complex band structures for band-to-band tunneling models (2011) (5)
- Electrical and mechanical characterization of lateral NEMS Switches (2011) (5)
- Gate Quantum Capacitance Effects in Nanoscale Transistors. (2019) (5)
- A Composite Circuit Model for NDR Devices in Random Access Memory Cells (2007) (5)
- 2D analytical model for the study of NEM relay device scaling (2011) (5)
- Electro-Thermal Confinement Enables Improved Superlattice Phase Change Memory (2022) (5)
- Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic (2007) (5)
- Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning (2015) (5)
- Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array (2016) (5)
- Performance Estimation and Benchmarking for Carbon Nanotube FETs and Nanodiode Arrays (2003) (5)
- Gate-current injection and surface impact ionization in MOSFET's with a gate induced virtual drain (1992) (5)
- Wafer Bonding for High-Performance Logic Applications (2004) (4)
- Hyperdimensional Computing Nanosystem (2018) (4)
- Ultrafast Accelerated Retention Test Methodology for RRAM Using Micro Thermal Stage (2017) (4)
- Graphene interconnect lifetime under high current stress (2012) (4)
- Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length (2020) (4)
- Nano-CMOS Technology for Next Fifteen Years (2006) (4)
- Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes (2009) (4)
- Fermi level depinning for the design of III–V FET source/drain contacts (2009) (4)
- The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology (2018) (4)
- Monolithic III–V nanowire PV for photoelectrochemical hydrogen generation (2010) (4)
- Tight-binding study of Γ-L bandstructure engineering for ballistic III–V nMOSFETs (2011) (4)
- Carbon Nanotube and Graphene Device Physics: Carbon nanotubes (2010) (4)
- Viability Study of All-III–V SRAM for Beyond-22-nm Logic Circuits (2011) (4)
- Fermi-Level Depinning of GaAs for Ohmic Contacts (2008) (4)
- Robust design and experimental demonstrations of carbon nanotube digital circuits (2014) (4)
- A 1TnR array architecture using a one-dimensional selection device (2014) (4)
- Impact of pulse rise time on programming of cross-point RRAM arrays (2014) (4)
- Special session paper 3D nanosystems enable embedded abundant-data computing (2017) (3)
- The future of CMOS scaling - parasitics engineering and device footprint scaling (2008) (3)
- Molybdenum oxide on carbon nanotube: Doping stability and correlation with work function (2020) (3)
- Interconnect scaling into the sub-10nm regime (2012) (3)
- 3D RRAM: Design and optimization (2014) (3)
- Compact modeling and design optimization of carbon nanotube field-effect transistors for the sub-10-nm technology nodes (2015) (3)
- Fault-Tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry (2008) (3)
- Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs (2022) (3)
- CeO2 Doping of Hf0.5Zr0.5O2 Thin Films for High Endurance Ferroelectric Memories (2022) (3)
- Metal/III–V effective barrier height tuning using ALD high-κ dipoles (2011) (3)
- Design and materials selection for low power laterally actuating nanoelectromechanical relays (2012) (3)
- Device and circuit interactive design and optimization beyond the conventional scaling era (2010) (3)
- NEM relays using 2-dimensional nanomaterials for low energy contacts (2013) (3)
- Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses (2018) (3)
- Scanning microwave imaging of optically patterned Ge2Sb2Te5 (2019) (3)
- Phase Change Memory A comprehensive and thorough review of PCM technologies, including a discussion of material and device issues, is provided in this paper. (2010) (3)
- Measurability Issues in the Radio-Frequency Characterization of Carbon Nanotubes (2006) (3)
- High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1 . 3 GHz Citation (2009) (3)
- Highly Confined Plasmons in Individual Single-Walled Carbon Nanotube Nanoantennas (2020) (3)
- Device Engineering to Improve SRAM Static Noise Margin (2010) (3)
- Low frequency noise in phase change materials (2011) (3)
- Characterization of phase-change layer thermal properties using a micro-thermal stage (2014) (3)
- Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI (2007) (2)
- Scaling behavior of PCM cells in off-state conduction (2012) (2)
- AC stress and electronic effects on SET switching of HfO2 RRAM (2017) (2)
- Heterogeneous 3D Nano-systems: The N3XT Approach? (2020) (2)
- Reduced HfO₂ Resistive Memory Variability by Inserting a Thin SnO₂ as Oxygen Stopping Layer (2021) (2)
- Advancements with carbon nanotube digital systems (2014) (2)
- Carbon Nanotubes for Monolithic 3D ICs (2017) (2)
- Template Patterning: Flexible Control of Block Copolymer Directed Self-Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning (Adv. Mater. 23/2012) (2012) (2)
- Steady-state Thermal Conductivity Measurement of Dielectric Stacks for Phase-Change Memory Power Reduction (2015) (2)
- Neuro-inspired computing with emerging memories: where device physics meets learning algorithms (2019) (2)
- Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization (2021) (2)
- Density driven placement of sub-DSA resolution assistant features (SDRAFs) (2017) (2)
- Erratum: “An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements” [Rev. Sci. Instrum.82, 053904 (2011)] (2011) (2)
- Layout optimization and template pattern verification for directed self-assembly (DSA) (2015) (2)
- Sub-5 nm gap formation for low power NEM switches (2015) (2)
- 5. Phase Change Memory (2014) (2)
- Device and Technology Challenges for Nanoscale CMOS (2006) (2)
- Ultrathin Three-Monolayer Tunneling Memory Selectors. (2021) (2)
- Carbon Nanotube and Graphene Device Physics: Applications of carbon nanotubes (2010) (2)
- CVD HAFNIUM DIBORIDE AS A CONTACT MATERIAL FOR NANOELECTROMECHANICAL SWITCHES (2012) (2)
- Electrical Stress Effects on Mobility of Germanium-On-Insulator (GeOI) pMOSFETs with HfO2 Gate Dielectric (2007) (2)
- Time-based sensor interface circuits in carbon nanotube technology (2015) (2)
- Multi-spacer technique for low-voltage, high-aspect-ratio lateral electrostatic actuators (2011) (2)
- First Principles Study of Memory Selectors using Heterojunctions of 2D Layered Materials (2018) (2)
- Resistive switching random access memory — Materials, device, interconnects, and scaling considerations (2012) (2)
- Carbon Nanotube and Graphene Device Physics: Carbon nanotube equilibrium properties (2010) (2)
- Coming Up N3XT, After 2D Scaling of Si CMOS (2018) (2)
- Dual-beam, six-terminal nanoelectromechanical relays (2013) (1)
- Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit (2008) (1)
- Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture (2014) (1)
- Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis (2011) (1)
- A systems approach to computing in beyond CMOS fabrics (2017) (1)
- Design and Optimization Methodology for 3 D RRAM Arrays (2013) (1)
- Four-mask process based on spacer technology for scaled-down lateral NEM electrostatic actuators (2010) (1)
- Future Interconnect Materials and System Integration Strategies for Data-Intensive Applications (2018) (1)
- Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design (2010) (1)
- An analytical model for intrinsic carbon nanotube FETs (2008) (1)
- Compact models of emerging devices (2013) (1)
- Probing the Limits of Silicon-Based Nanoelectronics (1995) (1)
- Vertical Sidewall MoS2 Growth and Transistors (2019) (1)
- Hyperdimensional computing nanosystem: in-memory computing using monolithic 3D integration of RRAM and CNFET (2020) (1)
- Direct Measurement of Trap Spacing in Phase Change Memory Cells Using ATE Devices (2011) (1)
- Nanometer-Scale <formula formulatype="inline"><tex Notation="TeX">${\rm HfO}_{x}$</tex></formula> RRAM (2013) (1)
- Invited) Graphene Plane Electrode for Low Power 3D Resistive Random Access Memory (2016) (1)
- Designing Circuits with Carbon Nanotubes Open Questions and Some Possible Directions (2006) (1)
- Training and Inference in Hopfield Network Using 10 × 10 Phase Change Synaptic Array (2017) (1)
- Statistical Analysis of Contacts to Synthetic Monolayer MoS2 (2021) (1)
- Carbon electronics — From material synthesis to circuit demonstration (2011) (1)
- Bidirectional Analog Conductance Modulation for RRAM-Based Neural Networks (2020) (1)
- Experimental Demonstration and Characterization of on-chip high speed graphene interconnects (2010) (1)
- Impact of III–V and Ge Devices on Circuit Performance (2013) (1)
- Scaling Theory of Two-Dimensional Field Effect Transistors (2021) (1)
- Carbon Nanotube and Graphene Device Physics: Overview of carbon nanotubes (2010) (1)
- Novel graphene-based devices (2013) (1)
- Measurement of anisotropy in the thermal conductivity of Ge2Sb2Te5 films (2009) (1)
- In-Plane Thermal Conduction and Conductivity Anisotropy in Ge2Sb2Te5 Films for Phase Change Memory (2010) (1)
- Detachable nano-carbon chip with ultra low power (2010) (1)
- Reliability of graphene interconnects and n-type doping of carbon nanotube transistors (2013) (1)
- Statistical study of RRAM MLC SET variability induced by filament morphology (2017) (1)
- Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing (2012) (1)
- Directed self-assembly guiding template design for contact hole patterning (2015) (1)
- Carbon Nanotube and Graphene Device Physics: Ideal quantum electrical properties (2010) (1)
- Improved Contacts to Synthetic Monolayer MoS2 – A Statistical Study (2021) (1)
- Analytical Degenerate Carrier Density and Quantum Capacitance for Semiconducting Carbon Nanotubes (2008) (0)
- Research opportunities for nanoscale CMOS (2006) (0)
- Ultrafast magnetic memory bits using all-optical magnetic switching (2017) (0)
- Carbon Nanotube and Graphene Device Physics: Carbon nanotube field-effect transistors (2010) (0)
- Study of DSA interaction range using Gaussian convolution (2015) (0)
- AC characterization of top-gated carbon nanotube field effect transistors (2003) (0)
- Resonant Tunneling Diodes: an Exercise (2006) (0)
- System-level Trade-offs and Optimization for Data-Driven Applications (2018) (0)
- Electrons in solids: a basic introduction (2010) (0)
- In quest of the next information processing substrate (2017) (0)
- Contact Resistance, Electrical Breakdown and Temperature-Dependent Conductance of Multi-Walled Carbon Nanotubes (2009) (0)
- (Invited) Carbon 1D/2D Nanoelectronics: Advances in Synthesis and Integration (2013) (0)
- Carbon-Based Nanomaterial for Nanoelectronics (2011) (0)
- Carbon nanotube interconnects (2010) (0)
- Crystallization Characteristics Of Phase Change Nanoparticle Arrays Fabricated By Self-Assembly Based Lithography (2008) (0)
- Technology projections of III-V devices down to 11 nm: importance of electrostatics and series resistance (2013) (0)
- N-type doping of carbon nanotube transistors using yttrium oxide (Y2Ox) (2014) (0)
- Beyond-Silicon Devices: Considerations for Circuits and Architectures (2018) (0)
- Electrothermal Modeling and Design Strategies for Multibit Phase Change Memory (2012) (0)
- Schottky-Barrier CNFET (2007) (0)
- SLICE image analysis for diblock copolymer characterization and process optimization (2010) (0)
- Recent Progress in Carbon Nanotube Electronics - Modeling, Materials, Devices, Circuits, and Interconnects (Invited) (2008) (0)
- Memory Devices: In Situ Tuning of Switching Window in a Gate‐Controlled Bilayer Graphene‐Electrode Resistive Memory Device (Adv. Mater. 47/2015) (2015) (0)
- Advanced CMOS Devices- A Tutorial from Practical Options to Innovative Concepts. Part I- Conventional Devices and Technology Options (2006) (0)
- Threshold Switching in Phase-Change Materials by Picosecond Electric Fields (2016) (0)
- A Fully Anlytical Model for Carbon Nanotube FETs including Quantum Capacitances and Electrostatics (0)
- A General Route to Inorganic Nanoparticles Using a Condensed Electron Beam (2009) (0)
- Building the hardware of future artificial intelligence systems: two-dimensional materials based electronic synapses (2018) (0)
- Sub-15 nm nanowires enabled by cryo pulsed self-aligned nanotrench ablation on carbon nanotubes (2017) (0)
- Scaling of All-Optical Switching to Nanometer Dimensions. (2018) (0)
- A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver (2020) (0)
- Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization (2017) (0)
- Metal Oxide RRAM For Next Generation Mass Storage: 3D Vertical Architecture and Electrode/Oxide Interface Engineering (2013) (0)
- ffi cient Phase-Change Memory with Graphene as a Thermal Barrier (2015) (0)
- Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters (2018) (0)
- Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs) (2016) (0)
- Carbon Nanotube FETs for Robust Digital Logic Systems (2014) (0)
- Electrical properties of CuPc-based OTFTs with atomic layer deposited HfAlO gate dielectric (2012) (0)
- Diblock copolymer directed self-assembly for CMOS device fabrication (2008) (0)
- Atomic layer deposition of high-k dielectric layers on single-walled carbon nanotubes (2012) (0)
- Near-room temperature electrical control of spin and valley Hall effect in monolayer WSe2 transistors for spintronic applications (2017) (0)
- Density-Balancing Mask Assignment for Via Patterning with Directed Self-Assembly (2016) (0)
- RRAM Models and Applications to Circuits and Systems (2017) (0)
- Advanced CMOS devices: Part I conventional devices and technology options (2005) (0)
- Hole Mobility Characteristics under Electrical Stress for Surface-Channel Germanium Transistors with High-κ Gate Stack (2008) (0)
- Semiconducting nanotube dominant chemical vapor deposition synthesis of isopropanol carbon feedstock (2012) (0)
- Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition (2016) (0)
- Challenges in Colloidal Phase Change Nanoparticle Devices (2010) (0)
- Advanced cmos devices: Part II - exploratory devices and approaches (2005) (0)
- CeO2-Doped Hf0.5Zr0.5O2 Ferroelectrics for High Endurance Embedded Memory Applications (2022) (0)
- Size-dependent phase transitions and morphological control over phase change properties using colloidal nanoparticle building blocks (2009) (0)
- The Device Physics of Experimentally Validated Analytical Theory of Transport in Ballistic Carbon Nanotube Transistors (2009) (0)
- Phase Change Memory – The Interplay Between Thermal and Electrical Effects (2013) (0)
- Improved gradual resistive switching range and 1000× on/off ratio in HfOx RRAM achieved with a Ge2Sb2Te5 thermal barrier (2022) (0)
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