Hans-joachim Dr Rer Wunderlich

Hans-joachim Dr Rer Wunderlich's AcademicInfluence.com Rankings

Engineering

#6820

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#8166

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Electrical Engineering

#2078

World Rank

#2183

Historical Rank

Applied Physics

#2251

World Rank

#2290

Historical Rank

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Engineering

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Hans-joachim Dr Rer Wunderlich's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Minimized Power Consumption for Scan-Based BIST (1999) (380)
Multiple distributions for biased random test patterns (1988) (244)
Bit-flipping BIST (1996) (243)
A modified clock scheme for a low power BIST test pattern generator (2001) (196)
Pattern generation for a deterministic BIST scheme (1995) (156)
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters (2000) (145)
Self test using unequiprobable random patterns (1987) (126)
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST (2001) (121)
PROTEST: A Tool for Probabilistic Testability Analysis (1985) (120)
Adaptive Debug and Diagnosis Without Fault Dictionaries (2007) (119)
An analytical approach to the partial scan problem (1990) (110)
Application of Deterministic Logic BIST on Industrial Circuits (2000) (105)
Design and architectures for dependable embedded systems (2011) (97)
Tailoring ATPG for embedded testing (2001) (88)
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy (2007) (87)
Mixed-Mode BIST Using Embedded Processors (1996) (86)
Accumulator based deterministic BIST (1998) (85)
Optimized synthesis of self-testable finite state machines (1990) (73)
Deterministic BIST with Multiple Scan Chains (1998) (65)
Efficient pattern mapping for deterministic logic BIST (2004) (62)
Programmable deterministic Built-In Self-Test (2007) (61)
X-masking during logic BIST and its impact on defect coverage (2004) (61)
BIST for systems-on-a-chip (1998) (60)
Fine-Grained Access Management in Reconfigurable Scan Networks (2015) (60)
The pseudoexhaustive test of sequential circuits (1989) (59)
Efficient fault simulation on many-core processors (2010) (56)
Restrict Encoding for Mixed-Mode BIST (2009) (52)
On Computing Optimized Input Probabilities for Random Tests (1987) (52)
Using BIST control for pattern generation (1997) (52)
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor (2006) (51)
Modeling, verification and pattern generation for reconfigurable scan networks (2012) (49)
X-masking during logic BIST and its impact on defect coverage (2006) (48)
RESPIN++ - deterministic embedded test (2002) (46)
Deterministic pattern generation for weighted random pattern testing (1996) (44)
Symmetric transparent BIST for RAMs (1999) (43)
Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation (2015) (43)
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead (2009) (42)
Reusing Scan Chains for Test Pattern Decompression (2002) (41)
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures (2013) (40)
High Defect Coverage with Low-Power Test Sequences in a BIST Environment (2002) (40)
Scan pattern retargeting and merging with reduced access time (2013) (40)
TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control (1990) (38)
The design of random-testable sequential circuits (1989) (38)
Hardware-optimal test register insertion (1998) (37)
On the reliability evaluation of SRAM-based FPGA designs (2005) (36)
Selective Hardening in Early Design Steps (2008) (36)
Efficient Online and Offline Testing of Embedded DRAMs (2002) (35)
Software-Based Self-Test of Processors under Power Constraints (2006) (34)
Test Strategies for Reliable Runtime Reconfigurable Architectures (2013) (33)
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects (2014) (33)
Tools and devices supporting the pseudo-exhaustive test (1990) (33)
Securing Access to Reconfigurable Scan Networks (2013) (33)
A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units (2014) (33)
Self-adjusting output data compression: An efficient BIST technique for RAMs (1998) (32)
Non-intrusive BIST for systems-on-a-chip (2000) (31)
Generating pseudo-exhaustive vectors for external testing (1990) (29)
A diagnosis algorithm for extreme space compaction (2009) (29)
BISD: Scan-based Built-In self-diagnosis (2010) (28)
Deterministic Logic BIST for Transition Fault Testing (2006) (28)
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience (2014) (28)
GUARD (2014) (28)
High-Throughput Logic Timing Simulation on GPGPUs (2015) (28)
Efficacy and efficiency of algorithm-based fault-tolerance on GPUs (2013) (27)
Rxiensing scan chains for test pattern decompression (2001) (27)
Scan chain clustering for test power reduction (2008) (26)
STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures (2015) (26)
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing (2006) (26)
Generalized Fault Modeling for Logic Diagnosis (2010) (25)
Advanced diagnosis: SBST and BIST integration in automotive E/E architectures (2014) (25)
Scan Test Power Simulation on GPGPUs (2012) (24)
Adapting an SoC to ATE concurrent test capabilities (2002) (24)
Access Port Protection for Reconfigurable Scan Networks (2014) (24)
Structural In-Field Diagnosis for Random Logic Circuits (2011) (23)
Scan Test Planning for Power Reduction (2007) (23)
Models in Hardware Testing (2010) (22)
On-line prediction of NBTI-induced aging rates (2015) (22)
GPU-Accelerated Simulation of Small Delay Faults (2017) (22)
GPU-accelerated small delay fault simulation (2015) (22)
A common approach to test generation and hardware verification based on temporal logic (1991) (22)
GUARD: GUAranteed reliability in dynamically reconfigurable systems (2014) (21)
Error detecting refreshment for embedded DRAMs (1999) (21)
Formal verification of secure reconfigurable scan network infrastructure (2016) (21)
Transparent structural online test for reconfigurable systems (2012) (20)
Specification and verification of security in reconfigurable scan networks (2017) (20)
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits (2011) (20)
Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors (1995) (20)
Impact of test point insertion on silicon area and timing during layout (2004) (19)
Optimal hardware pattern generation for functional BIST (2000) (19)
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures (2017) (19)
Accurate QBF-based test pattern generation in presence of unknown values (2013) (19)
Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations (2016) (18)
A Neural-Network-Based Fault Classifier (2016) (18)
Structural Test for Graceful Degradation of NoC Switches (2011) (18)
A pseudo-dynamic comparator for error detection in fault tolerant architectures (2012) (17)
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits (2010) (17)
Variation-aware fault modeling (2010) (17)
Variation-Aware Fault Grading (2012) (17)
Trustworthy reconfigurable access to on-chip infrastructure (2017) (16)
Variation-aware deterministic ATPG (2014) (16)
Circuit partitioning for efficient logic BIST synthesis (2001) (16)
On applying the set covering model to reseeding (2001) (16)
Simulation results of an efficient defect analysis procedure (1994) (15)
Synthesis of workload monitors for on-line stress prediction (2013) (15)
Power Dissipation During Testing: Should We Worry About it? (1997) (15)
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms (1999) (15)
Efficient multi-level fault simulation of HW/SW systems for structural faults (2011) (15)
Hochintegrierte Schaltungen : prüfgerechter Entwurf und Test (1991) (15)
On Fault Modeling for Dynamic MOS Circuits (1986) (15)
Efficient Concurrent Self-Test with Partially Specified Patterns (2010) (15)
Cross- Layer Dependability Modeling and Abstraction in Systems on Chip (2013) (15)
Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault (2009) (15)
Algorithm-based fault tolerance for many-core architectures (2010) (14)
Scan Chain Organization for Embedded Diagnosis (2008) (14)
Optimized Selection of Frequencies for Faster-Than-at-Speed Test (2015) (14)
Structural Software-Based Self-Test of Network-on-Chip (2014) (14)
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level (2010) (14)
Synthesis of self-testable controllers (1994) (14)
Parallel self-test and the synthesis of control units (1991) (14)
Towards Variation-Aware Test Methods (2011) (13)
Low-overhead fault-tolerance for the preconditioned conjugate gradient solver (2015) (13)
Exact stuck-at fault classification in presence of unknowns (2012) (13)
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction (2007) (13)
Soft error correction in embedded storage elements (2011) (13)
Optimized synthesis techniques for testable sequential circuits (1992) (13)
From embedded test to embedded diagnosis (2005) (13)
Combining deterministic logic BIST with test point insertion (2002) (13)
The synthesis of self-test control logic (1989) (12)
Exact Logic and Fault Simulation in Presence of Unknowns (2014) (12)
An Efficient Procedure For The Synthesis Of Fast Self-testable Controller Structures (1994) (12)
A unified approach for the synthesis of self-testable finite state machines (1991) (12)
Integrating Scan Design and Soft Error Correction in Low-Power Applications (2008) (12)
Fast controllers for data dominated applications (1997) (12)
Test Set Stripping Limiting the Maximum Number of Specified Bits (2008) (12)
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip (2017) (12)
Efficient observation point selection for aging monitoring (2015) (12)
Signature Rollback - A Technique for Testing Robust Circuits (2008) (11)
Structure-Oriented Test of Reconfigurable Scan Networks (2017) (11)
Deterministic BIST with Partial Scan (1999) (11)
Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs (2012) (11)
Special ATPG to correlate test patterns for low-overhead mixed-mode BIST (1998) (11)
Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures (2012) (11)
Accurate X-Propagation for Test Applications by SAT-Based Reasoning (2012) (11)
Adaptive Bayesian Diagnosis of Intermittent Faults (2014) (11)
Self-Test and Diagnosis for Self-Aware Systems (2018) (11)
Test Strategies for Reconfigurable Scan Networks (2016) (10)
Configuring flip-flops to BIST registers (1994) (10)
OTERA: Online test strategies for reliable reconfigurable architectures — Invited paper for the AHS-2012 special session “Dependability by reconfigurable hardware” (2012) (10)
Efficient variation-aware statistical dynamic timing analysis for delay test applications (2013) (10)
Synthesis of IDDQ-testable circuits: integrating built-in current sensors (1995) (10)
Device aging: A reliability and security concern (2018) (10)
Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits (1988) (10)
Diagnosis of multiple faults with highly compacted test responses (2014) (10)
On Secure Data Flow in Reconfigurable Scan Networks (2019) (10)
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures (2014) (10)
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention (2018) (10)
Detecting and Resolving Security Violations in Reconfigurable Scan Networks (2018) (10)
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair (2007) (10)
High Quality System Level Test and Diagnosis (2014) (10)
Efficient on-line fault-tolerance for the preconditioned conjugate gradient method (2015) (9)
Test Encoding for Extreme Response Compaction (2009) (9)
Accurate Multi-cycle ATPG in Presence of X-Values (2013) (9)
Data-parallel simulation for fast and accurate timing validation of CMOS circuits (2014) (9)
Dependable on-chip infrastructure for dependable MPSOCs (2016) (9)
P-PET: Partial pseudo-exhaustive test for high defect coverage (2011) (9)
Development of an audio player as system-on-a-chip using an open source platform (2005) (8)
On Determining the Real Output Xs by SAT-Based Reasoning (2010) (8)
Test exploration and validation using transaction level models (2009) (8)
Signature analysis and test scheduling for self-testable circuits (1991) (8)
Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test (2012) (8)
Online prevention of security violations in reconfigurable scan networks (2018) (8)
Functional Diagnosis for Graceful Degradation of NoC Switches (2016) (8)
Implementing a scheme for external deterministic self-test (2005) (8)
Error masking in self-testable circuits (1990) (8)
Synthesizing Fast, Online-Testable Control Units (1998) (7)
Adaptive parallel simulation of a two-timescale model for apoptotic receptor-clustering on GPUs (2014) (6)
High-Throughput Transistor-Level Fault Simulation on GPUs (2016) (6)
Pushing the limits: How fault tolerance extends the scope of approximate computing (2016) (6)
Parallel simulation of apoptotic receptor-clustering on GPGPU many-core architectures (2012) (6)
The Time Dilation Scan Architecture for Timing Error Detection and Correction (2008) (6)
Area-efficient synthesis of fault-secure NoC switches (2014) (6)
SAT-based code synthesis for fault-secure circuits (2013) (6)
The integration of test and high level synthesis in a general design environment (1986) (6)
SAT-based fault coverage evaluation in the presence of unknown values (2011) (6)
Efficient system-level aging prediction (2012) (6)
Output-maximal control policies for cascaded production-inventory systems with control and state constraints (1984) (6)
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability (2001) (6)
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch (2015) (6)
Test pattern generation in presence of unknown values based on restricted symbolic logic (2014) (6)
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation (2014) (6)
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures (2011) (5)
On Covering Structural Defects in NoCs by Functional Tests (2014) (5)
Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (2010) (5)
Structural Test and Diagnosis for Graceful Degradation of NoC Switches (2012) (5)
System reliability evaluation using concurrent multi-level simulation of structural faults (2010) (5)
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems (2014) (5)
Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware (2016) (5)
Diagnostic Test of Robust Circuits (2011) (5)
Efficient BDD-based Fault Simulation in Presence of Unknown Values (2011) (5)
Variation-Aware Defect Characterization at Cell Level (2020) (5)
Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment (2006) (5)
Test register insertion with minimum hardware cost (1995) (5)
Multi-level timing simulation on GPUs (2018) (5)
Aging monitor reuse for small delay fault testing (2017) (5)
Bit-Flipping Scan — A unified architecture for fault tolerance and offline test (2014) (5)
Reliability Considerations forMechatronic Systems on the Basis of a State Model (2004) (5)
Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns (2016) (5)
Security Compliance Analysis of Reconfigurable Scan Networks (2019) (5)
Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks (2020) (5)
Autonomous Testing for 3D-ICs with IEEE Std. 1687 (2016) (5)
SWIFT: Switch-Level Fault Simulation on GPUs (2019) (5)
Probabilistische Verfahren für den Test hochintegrierter Schaltungen (1987) (5)
Low-power test planning for arbitrary at-speed delay-test clock schemes (2010) (5)
Probabilistic sensitization analysis for variation-aware path delay fault test evaluation (2017) (4)
Built-In Test for Hidden Delay Faults (2019) (4)
Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems (2021) (4)
Debug and Diagnosis : Mastering the Life Cycle of Nano-Scale Systems on Chip (2007) (4)
Adaptive multi-layer techniques for increased system dependability (2015) (4)
DFG-Projekt RealTest – Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project – Test and Reliability of Nano-Electronic Systems) (2006) (4)
Resistive Open Defect Classification of Embedded Cells under Variations (2021) (4)
Some common aspects of design validation, debug and diagnosis (2006) (4)
A synthesis approach to reduce scan design overhead (1990) (4)
Incremental computation of delay fault detection probability for variation-aware test generation (2014) (3)
Testability-Enhancing Resynthesis of Reconfigurable Scan Networks (2021) (3)
Energy-efficient and error-resilient iterative solvers for approximate computing (2017) (3)
Sequence Length , Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST (2004) (3)
Fault tolerance of approximate compute algorithms (2016) (3)
GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling (2020) (3)
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses (2019) (3)
Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction (2020) (3)
Integrated tools for automatic design for testability (1988) (3)
Synthesis of Fault-Tolerant Reconfigurable Scan Networks (2020) (3)
Analysis and mitigation or IR-Drop induced scan shift-errors (2017) (3)
Multi-Layer Test and Diagnosis for Dependable NoCs (2015) (3)
Fast self-recovering controllers (1998) (3)
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test (2012) (3)
Embedded Test for Highly Accurate Defect Localization (2011) (2)
Test and testable design (2000) (2)
Parity prediction synthesis for nano-electronic gate designs (2010) (2)
Academic network for microelectronic test education (2007) (2)
Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung (2005) (2)
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures (2015) (2)
The random pattern testability of programmable logic arrays (1987) (2)
Power Conscious BIST Approaches (2002) (2)
Test engineering education in Europe: the EuNICE-Test project (2003) (2)
Eingebetteter Test zur hochgenauen Defekt-Lokalisierung (2011) (2)
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test (2016) (2)
Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene (2010) (2)
Models for Power-Aware Testing (2010) (2)
Fail-safety in core-based system design (2011) (2)
Using mission logic for embedded testing (2001) (2)
Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan Testing (2006) (2)
Automatisierung des Entwurfs vollständig testbarer Schaltungen (1988) (2)
Synthesis of irregular combinational functions with large don't care sets (2007) (2)
Power-Aware Design-for-Test (2010) (2)
Korrektur transienter Fehler in eingebetteten Speicherelementen (2011) (1)
Tolérance aux fautes et rendement de fabrication (2011) (1)
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing (2018) (1)
The effectiveness of different test sets for PLAs (1990) (1)
Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen (2009) (1)
THE SYNTHESIS OF SEL.F·TEST CONTROL. L.OGIC (1989) (1)
Advances in hardware reliability of reconfigurable many-core embedded systems (2019) (1)
Digital, memory and mixed-signal test engineering education: five centres of competence in Europe (2004) (1)
Technique Structurelle d'Affectation des Bits Non Spécifiés en Vue d'une Réduction de la Puissance de Pic Pendant le Test Série (2006) (1)
A unified method for assembling global test schedules (1994) (1)
Adaptive Test and Diagnosis of Intermittent Faults (2013) (1)
Verifikation Rekonfigurierbarer Scan-Netze (2014) (1)
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (2007) (1)
Emulation of Scan Paths in Sequential Circuit Synthesis (1991) (1)
IDENTIFICATION OF TIME VARYING PARAMETERS OF THE ROBOT DYNAMICS (1988) (1)
SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks (2022) (1)
Preprint Optimized Selection of Frequencies for Faster-Thanat-Speed Test (2016) (1)
A Hybrid Protection Scheme for Reconfigurable Scan Networks (2021) (1)
On Extracting Reliability Information from Speed Binning (2022) (1)
DLBIST for Delay Testing (1)
Guest Editors' Introduction (2018) (1)
Guest Editors' Introduction - Special Issue on Approximate Computing (2018) (0)
Supporting structure of a motor vehicle (2002) (0)
Preprint Fail-Safety in Core-Based System Design (2012) (0)
Preprint Variation-Aware Fault Grading (2012) (0)
Preprint Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation (2014) (0)
Session details: Facing dependability: system-level solutions and cybercar challenges (2012) (0)
Panel Summaries (1998) (0)
Das Testproblem für integrierte Schaltungen (1987) (0)
Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit (2008) (0)
Using Embedded Processors for BIST (1996) (0)
Stress-Aware Periodic Test of Interconnects (2021) (0)
Device Aging : A Security and Reliability Concern (2018) (0)
Identifying Resistive Open Defects in Embedded Cells under Variations (2023) (0)
Simulation Res ults of an Effici ent Defect Analys is Procedure (1994) (0)
Preprint Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate Gradient Method (2015) (0)
Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information (2008) (0)
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems (2014) (0)
Prüfgerechter Entwurf und Test hochintegrierter Schaltungen (1992) (0)
Methoden der Testvorbereitung zum IC-Entwurf (1990) (0)
Preprint Efficient System-Level Aging Prediction (2012) (0)
Preprint Securing Access to Reconfigurable Scan Networks (2013) (0)
Stress-Aware Periodic Test of Interconnects (2022) (0)
ETS 2015 best paper (2016) (0)
Networks-on-a-Chip (2003) (0)
Fehlerentdeckungs- und Signalwahrscheinlichkeiten (1987) (0)
A mixed-mode BIST scheme based on folding compression (2002) (0)
Preprint High Quality System Level Test and Diagnosis (2014) (0)
Die Bestimmung effizienter Zufallstests (1987) (0)
Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling (2020) (0)
Efficient Consistency Checking for Embedded Memories (1998) (0)
Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen (1992) (0)
Online Periodic Test of Reconfigurable Scan Networks (2022) (0)
Grundlagen. Definitionen und Vorarbeiten (1987) (0)
Exploiting Symmetries to Speed Up Transparent BIST (1999) (0)
SAT-based ATPG beyond stuck-at fault testing (2014) (0)
Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant Architecture (2012) (0)
Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures (2020) (0)
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications (1997) (0)
Fast Controllers for Data Dominated Applica (1997) (0)
Maximizing the fault coverage in complex circuits by minimal number of signatures (1991) (0)
On Commuting Outimized Intmt Probabilities for Random Tests (2015) (0)
Guest Editorial (1997) (0)
Robuster Selbsttest mit Diagnose (2014) (0)
Der pseudo-erschöpfende Test (1991) (0)
Preprint Dependable on-chip infrastructure for dependable MPSOCs (2016) (0)
Multi-level timing and fault simulation on GPUs (2019) (0)
14.1 Fast Self-Recovering Controllers (1998) (0)
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks (2022) (0)
2012 JETTA Reviewers (2013) (0)
Test und Zuverlässigkeit nanoelektronischer Systeme (2007) (0)
Anwendungen bei Test- und Synthese-Algorithmen (1987) (0)
Preprint Variation-Aware Deterministic (2014) (0)
Der Test mit Zufallsmustern (1991) (0)
Robust Reconfigurable Scan Networks (2022) (0)
Reliable Simulations on Many-Core Architectures (2011) (0)
GPU-Accelerated Small Delay Fault Simulation Aging Rates (2018) (0)
Deterministische Testerzeugung für Schaltnetze (1991) (0)
Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern (1989) (0)
University of Stuttgart M.Sc. Program INFOTECH (2002) (0)
Testing visions (2015) (0)
ROUTER DESIGN WITH GT AND BE SERVICES (0)
Pn 2: Molecular Simulations with High-performance and Many-core Computer Systems ____________________________________________________________________________ 35 Sub-project " Mapping Simulation Algorithms to Noc Mpsoc Computers " State of Current Work (2010) (0)
Hauptseminar : Reliable Networks-On-Chip in the Many-Core Era Summer Semester , 2009 Self-calibrating Asynchronous NoC Links (2009) (0)
Preprint Scan Test Power Simulation on GPGPUs (2012) (0)
Test und Diagnose (2014) (0)
Testverfahren für spezielle Strukturen (1991) (0)
Preprint GPU-Accelerated Small Delay Fault Simulation (2015) (0)
Deterministic BIST Scheme Based on Reseeding of Folding Counters (2001) (0)
Software-Based Hardware Fault Tolerance for Many-Core Architectures (2009) (0)
Methoden der Testvorbereitung (1989) (0)
Modellierung der Testinfrastruktur auf der Transaktionsebene (2010) (0)
Preprint Diagnostic Test of Robust Circuits (2012) (0)
Efficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep Learning (2022) (0)
Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen (2008) (0)
Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern (2012) (0)
Guest Editor's Introduction (2018) (0)
Chapter 7 Models for Power-Aware Testing (2010) (0)
Preprint Autonomous Testing for 3 D-ICs with IEEE Std . 1687 (2016) (0)
Preprint Trustworthy Reconfigurable Access to On-Chip Infrastructure (2017) (0)
Preprint High-Throughput Logic Timing Simulation on GPGPUs (2015) (0)
Logic Fault Diagnosis of Hidden Delay Defects (2020) (0)
Efficient test set evaluation (1992) (0)
Preprint Soft Error Correction in Embedded Storage Elements (2012) (0)
Preprint Efficient Observation Point Selection for Aging Monitoring (2015) (0)
Optimized Synthesis of Self-Testable Finite Sta (2016) (0)
New Transparent RAM BIST Based on Self-Adjusting Output Data Compression (1998) (0)
Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time (1994) (0)
3 Test Preparation and Generation ( T 2 ) (2018) (0)
Intelligent Methods for Test and Reliability (2022) (0)
Test und Synthese schneller eingebetteter Systeme (1998) (0)
Teststrategien für Schaltwerke (1991) (0)
Special Panel Session (2010) (0)
Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler (2015) (0)
Access Port Protection for Reconfigurable Scan Networks (2014) (0)
On Computing Optjmized Inout Prohabilities for Random Tes'S (1987) (0)
Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis (1995) (0)
Adaptive Bayesian Diagnosis of Intermittent Faults (2014) (0)
Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlssigkeit und Ausbeute (2007) (0)
Structural Test and Diagnosis for Graceful Degradation of NoC Switches (2012) (0)
Synthesis Procedures for Self-Testable Controllers (1995) (0)
Preprint Towards Variation-Aware Test Methods (2012) (0)
Weighted random patterns with multiple distributions (1988) (0)
Special session on early life failures (2017) (0)
Schaltungs- und Fehlermodellierung (1991) (0)
Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen (1989) (0)

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