Henk Corporaal

Q: What Schools Are Affiliated With Henk Corporaal

Henk Corporaal is affiliated with the following schools: Eindhoven University of Technology, Delft University of Technology

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Henk Corporaal

Computer Science

#7134

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#7514

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#4191

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#4359

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Computer Science

Henk Corporaal's Degrees

PhD Computer Science Eindhoven University of Technology

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Henk Corporaal's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Microprocessor architectures - from VLIW to TTA (1997) (293)
Embedded System Design (2006) (266)
Memory-centric accelerator design for Convolutional Neural Networks (2013) (264)
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs (2007) (194)
System-scenario-based design of dynamic embedded systems (2009) (174)
Bones (2014) (166)
Memristor based computation-in-memory architecture for data-intensive applications (2015) (148)
Designing domain-specific processors (2001) (132)
A detailed GPU cache model based on reuse distance theory (2014) (113)
MOVE: a framework for high-performance processor design (1991) (105)
An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip (2007) (94)
Memristor for computing: Myth or reality? (2017) (88)
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA (2008) (86)
Code generation for transport triggered architectures (1996) (86)
Layer assignment techniques for low energy in multi-layered memory organisations (2003) (79)
Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management (2006) (77)
Adaptive and transparent cache bypassing for GPUs (2015) (75)
Automatic scenario detection for improved WCET estimation (2005) (72)
Run-Time Management of a MPSoC Containing FPGA Fabric Tiles (2008) (71)
NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning (2019) (67)
Coarse grained reconfigurable architectures in the past 25 years: Overview and classification (2016) (67)
Locality-Aware CTA Clustering for Modern GPUs (2017) (65)
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply (2009) (64)
Partitioned register file for TTAs (1995) (61)
Making graphs reducible with controlled node splitting (1997) (61)
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage (2010) (60)
Using Transport Triggered Architectures for Embedded Processor Design (1998) (57)
Design of transport triggered architectures (1994) (56)
A Review of Near-Memory Computing Architectures: Opportunities and Challenges (2018) (55)
Clustered loop buffer organization for low energy VLIW embedded processors (2005) (53)
A Safari Through the MPSoC Run-Time Management Jungle (2010) (51)
High performance predictable histogramming on GPUs: exploring and evaluating algorithm trade-offs (2011) (51)
Register file port requirements of transport triggered architectures (1994) (50)
TTAs: Missing the ILP complexity wall (1999) (49)
Transport Triggered Architectures : Design and Evaluation (1995) (49)
Introducing 'Bones': a parallelizing source-to-source compiler based on algorithmic skeletons (2012) (48)
Low Power Coarse-Grained Reconfigurable Instruction Set Processor (2003) (48)
NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling (2020) (47)
Inter-cluster communication models for clustered VLIW processors (2003) (46)
Near-Memory Computing: Past, Present, and Future (2019) (46)
Analytics for the internet of things (2009) (45)
Power breakdown analysis for a heterogeneous NoC platform running a video application (2005) (43)
CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications (2010) (43)
FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications (2021) (42)
Speed sign detection and recognition by convolutional neural networks (2011) (42)
Fine-Grained Synchronizations and Dataflow Programming on GPUs (2015) (42)
Fast Hough Transform on GPUs: Exploration of Algorithm Trade-Offs (2011) (41)
Application Scenarios in Streaming-Oriented Embedded-System Design (2008) (41)
MOVE-Pro: A low power and high code density TTA architecture (2011) (41)
An End-to-End Computing Model for the Square Kilometre Array (2014) (41)
Modeling static-order schedules in synchronous dataflow graphs (2012) (41)
Xetal-Pro: An ultra-low energy and high throughput SIMD processor (2010) (40)
Intra-task scenario-aware voltage scheduling (2005) (40)
Dynamic time-slot allocation for QoS enabled networks on chip (2005) (39)
Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT (2007) (39)
Transport-Triggering versus Operation-Triggering (1994) (39)
Design-Time Application Exploration for MP-SoC Customized Run-Time Management (2005) (38)
Real-Time Face Recognition on a Smart Camera. (2003) (36)
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management (2006) (36)
Analyzing composability of applications on MPSoC platforms (2008) (35)
Design space exploration algorithm for heterogeneous multi-processor embedded system design (1998) (34)
Automated bottleneck-driven design-space exploration of media processing systems (2010) (34)
Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations (2007) (32)
Vt balancing and device sizing towards high yield of sub-threshold static logic gates (2007) (32)
Skeleton-based automatic parallelization of image processing algorithms for GPUs (2011) (31)
SFU-Driven Transparent Approximation Acceleration on GPUs (2016) (30)
Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators (2015) (30)
Parametric throughput analysis of scenario-aware dataflow graphs (2012) (29)
Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications (2011) (29)
Scheduling Real-Time Streaming Applications onto an Embedded Multiprocessor (2013) (29)
The boat hull model: enabling performance prediction for parallel computing prior to code development (2012) (28)
Throughput-constrained DVFS for scenario-aware dataflow graphs (2013) (28)
Multi-Processor System-Level Synthesis for Multiple Applications on Platform FPGA (2007) (28)
xCPS: a tool to explore cyber physical systems (2017) (28)
Centralized end-to-end flow control in a best-effort network-on-chip (2005) (27)
SmartCam: Devices for Embedded Intelligent Cameras (2002) (27)
Distributed Congestion Control for Packet Switched Networks on Chip (2005) (27)
Profiling Driven Scenario Detection and Prediction for Multimedia Applications (2006) (26)
The Impact of Higher Communication Layers on NoC Supported MP-SoCs (2007) (26)
Exploring trade-offs between performance and resource requirements for synchronous dataflow graphs (2009) (26)
Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors (2007) (26)
Move32int, a sea of gates realization of a high performance transport triggered architecture (1993) (25)
Compile-time GPU memory access optimizations (2010) (25)
Design of heterogenous multi-processor embedded systems: applying functional pipelining (1997) (25)
A modular and parameterisable classification of algorithms (2011) (25)
Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications (2008) (25)
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip (2006) (25)
Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems (2013) (24)
Systematic Preprocessing of Data Dependent Constructs for Embedded Systems (2005) (24)
Overcoming the limitations of the traditional loop parallelization (1997) (24)
Analytic Multi-Core Processor Model for Fast Design-Space Exploration (2018) (24)
Cosynthesis with the MOVE framework (1996) (24)
Scheduling for register file energy minimization in explicit datapath architectures (2012) (24)
Global memory optimisation for embedded systems allowed by code duplication (2005) (24)
Instruction buffering exploration for low energy VLIWs with instruction clusters (2004) (23)
The boat hull model: adapting the roofline model to enable performance prediction for parallel computing (2012) (23)
An Automated Flow to Map Throughput Constrained Applications to a MPSoC (2011) (23)
Evaluation of speed and area of clustered VLIW processors (2005) (23)
SDRAM-Energy-Aware memory allocation for dynamic multi-media applications on multi-processor platforms (2003) (22)
Automatic detection of recurring operation patterns (1999) (22)
Soft reliability: an interdisciplinary approach with a user–system focus (2009) (22)
Efficiency Optimization of Trainable Feature Extractors for a Consumer Platform (2011) (22)
Cluster assignment of global values for clustered VLIW processors (2003) (22)
Advanced copy propagation for arrays (2003) (21)
Iterative compilation for energy reduction (2005) (21)
Parallelization of while loops in nested loop programs for shared-memory multiprocessor systems (2011) (21)
Quality-of-service trade-off analysis for wireless sensor networks (2009) (20)
Application Scenarios in Streaming-Oriented Embedded System Design (2006) (20)
Automatic Synthesis of Transport Triggered Processors (1995) (20)
Predictable real-time software synthesis (2007) (20)
Algorithmic species: A classification of affine loop nests for parallel programming (2013) (20)
Floating Point to Fixed Point Conversion of C Code (1999) (20)
X: A Comprehensive Analytic Model for Parallel Machines (2016) (20)
From Xetal-II to Xetal-Pro: On the Road Toward an Ultralow-Energy and High-Throughput SIMD Processor (2011) (20)
Critical points based register-concurrency autotuning for GPUs (2016) (19)
Worst-case throughput analysis of real-time dynamic streaming applications (2012) (19)
A model-driven design approach for mechatronic systems (2007) (19)
A 0.964mW digital hearing aid system (2011) (19)
Global Analysis of Resource Arbitration for MPSoC (2006) (19)
Transit: A Visual Analytical Model for Multithreaded Machines (2015) (19)
Error Estimation in Model-Driven Development for Real-Time Software (2004) (19)
Algorithmic skeletons for stream programming in embedded heterogeneous parallel image processing applications (2006) (18)
Automated extraction of scenario sequences from disciplined dataflow networks (2013) (18)
Design-time application mapping and platform exploration for MP-SoC customised run-time management (2007) (18)
RASW: A run-time adaptive sliding window to improve Viola-Jones object detection (2013) (18)
Model-Driven Design-Space Exploration for Software-Intensive Embedded Systems (2012) (18)
Feasibility of Contactless Pulse Rate Monitoring of Neonates using Google Glass (2015) (17)
Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems (2006) (17)
DominoSearch: Find layer-wise fine-grained N: M sparse schemes from dense neural networks (2021) (17)
Analysing qos trade-offs in wireless sensor networks (2007) (17)
Specification for User Modeling with Self-Observing Systems (2008) (17)
Instruction buffering exploration for low energy embedded processors (2005) (16)
Schedule-Extended Synchronous Dataflow Graphs (2013) (16)
Declarative Loop Tactics for Domain-specific Optimization (2019) (16)
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors (2002) (16)
A SIMD-VLIW Smart Camera Architecture for Real-Time Face Recognition (2003) (16)
Skeletons and Asynchronous RPC for Embedded Data- and Task Parallel Image Processing (2006) (16)
Fast and accurate protocol specific bus modeling using TLM 2.0 (2009) (16)
Algorithmic species revisited: A program code classification based on array references (2013) (16)
A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printer (2015) (16)
Feasibility Analysis of Ultra High Frame Rate Visual Servoing on FPGA and SIMD Processor (2011) (16)
Exploring processor parallelism: Estimation methods and optimization strategies (2013) (16)
Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms (2011) (16)
PROGRESS white papers 2006 (2006) (15)
Roofline-aware DVFS for GPUs (2014) (15)
DualSR: Zero-Shot Dual Learning for Real-World Super-Resolution (2021) (15)
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric (2021) (15)
Trade-offs in loop transformations (2009) (15)
Introducing the SuperGT Network-on-Chip (2007) (15)
Online multi-face detection and tracking using detector confidence and structured SVMs (2015) (15)
Global interconnect trade-off for technology over memory modules to application level: case study (2003) (15)
Automatic SIMD Parallelization of Embedded Applications Based on Pattern Recognition (2000) (15)
FP-map-an approach to the functional pipelining of embedded programs (1997) (15)
Inter-cluster communication in VLIW architectures (2007) (14)
Transformatiing and Parallelizing ANSI C Programs using Pattern Recognition (1999) (14)
Dictionary-based program compression on transport triggered architectures (2005) (14)
Improving Product Usage Monitoring and Analysis with Semantic Concepts (2009) (14)
A Quick Safari Through the MPSoC Run-Time Management Jungle (2007) (14)
A Low-Energy Wide SIMD Architecture with Explicit Datapath (2015) (14)
TTA Processor Synthesis (1995) (14)
Real-time implementations of Hough Transform on SIMD architecture (2008) (14)
Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management (2011) (14)
Software pipelining for transport-triggered architectures (1991) (14)
Analytic processor model for fast design-space exploration (2015) (13)
Exploiting fine- and coarse-grain parallelism in embedded programs (1998) (13)
Evaluating transport triggered architectures for scalar applications (1993) (13)
Automatic Skeleton-Based Compilation through Integration with an Algorithm Classification (2013) (13)
Predictability in Real-Time System Development (2005) (13)
An efficient, reference weight-based garbage collection method for distributed systems (1990) (13)
Iteration-Based Trade-Off Analysis of Resource-Aware SDF (2011) (13)
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices (2007) (13)
Reviewing inference performance of state-of-the-art deep learning frameworks (2020) (12)
Loop transformations leveraging hardware prefetching (2018) (12)
Skeleton-based design and simulation flow for Computation-in-Memory architectures (2016) (12)
Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs (2013) (12)
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths (2014) (12)
Model Interpretation for Executable Observation Specifications (2008) (12)
Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm (2014) (12)
A Locality Aware Convolutional Neural Networks Accelerator (2015) (12)
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems (2010) (12)
Reusing Real-Time Systems Design Experience Through Modelling Patterns (2006) (12)
Variations on the Cascade-Correlation Learning Architecture for Fast Convergence in Robot Control (1992) (12)
Symbolic analysis of dataflow applications mapped onto shared heterogeneous resources (2014) (11)
SIMD made explicit (2013) (11)
The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision (2016) (11)
Computation in the Context of Transport Triggered Architectures (2000) (11)
Schedule Synthesis for Halide Pipelines through Reuse Analysis (2019) (11)
Energy efficient special instruction support in an embedded processor with compact isa (2012) (11)
QoS Management for Wireless Sensor Networks with a Mobile Sink (2009) (11)
Registers On Demand, an integrated region scheduler and register allocator (1998) (11)
A Systematic Approach to Design Low-Power Video Codec Cores (2007) (11)
A tool for fast ground truth generation for object detection and tracking from video (2014) (11)
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration (2011) (11)
MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs (2013) (11)
Controlled Node Splitting (1996) (11)
Automatic Generation of Multi-Objective Polyhedral Compiler Transformations (2020) (11)
OpenCL code generation for low energy wide SIMD architectures with explicit datapath (2013) (11)
Layer assignment techniques for low power in multi-layered memory organisations. (2003) (11)
An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs (2015) (10)
Implementing face recognition using a parallel image processing environment based on algorithmic skeletons (2004) (10)
(AS)2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration (2015) (10)
Strengthening Property Preservation in Concurrent Real-Time Systems (2006) (10)
Extending Halide to Improve Software Development for Imaging DSPs (2017) (10)
NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil Computations (2019) (10)
GPU-Vote: A Framework for Accelerating Voting Algorithms on GPU (2012) (10)
Evaluating template-based instruction compression on transport triggered architectures (2003) (10)
Demo: An embedded vision system for high frame rate visual servoing (2011) (10)
Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture (1992) (10)
Reconfigurable Multi-Processor Network-on-Chip on FPGA (2006) (10)
Transport Triggered Architectures examined for general pu rpose applications (1993) (10)
Dictionary-based program compression on TTAs: effects on area and power consumption (2005) (10)
Schedule Synthesis for Halide Pipelines on GPUs (2020) (10)
Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs (2014) (10)
Scenario-based SDRAM-Energy-Aware Scheduling for Dynamic Multi-Media Applications on Multi-Processor Platforms. (2002) (9)
A different approach to high performance computing (1997) (9)
Using iterative compilation to reduce energy consumption (2004) (9)
Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures (2020) (9)
CIM-SIM: Computation In Memory SIMuIator (2019) (9)
Dictionary-based program compression on customizable processor architectures (2009) (9)
High-level software-pipelining in LLVM (2015) (9)
Playing games with scenario- and resource-aware SDF graphs through policy iteration (2012) (9)
TC-CIM: Empowering Tensor Comprehensions for Computing-In-Memory (2020) (9)
Correlation ratio based volume image registration on GPUs (2015) (9)
Clustered L0 Buffer Organization for Low Energy Embedded Processors (2002) (9)
Bottlenecks and Tradeoffs in High Frame Rate Visual Servoing: A Case Study (2011) (9)
Low Precision Processing for High Order Stencil Computations (2019) (9)
An Automated Approximation Methodology for Arithmetic Circuits (2019) (9)
A Fast Estimator of Performance with Respect to the Design Parameters of Self Re-Entrant Flowshops (2016) (8)
A Programmable ANSI C Transformation Engine (1999) (8)
Demystifying the 16 × 16 thread‐block for stencils on the GPU (2015) (8)
A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA (2018) (8)
MacSim: A MAC-Enabled High-Performance Low-Power SIMD Architecture (2016) (8)
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications (2006) (8)
Robust online face tracking-by-detection (2016) (8)
Heuristics for Scenario Creation to Enable General Loop Transformations (2007) (8)
The Impact of Data Communication and Control Synchronization on Coarse-Grain Task Parallelism (1996) (8)
Resynchronization of Cyclo-Static Dataflow graphs (2011) (8)
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures (2005) (8)
REAL-TIME FACE RECOGNITION ON A MIXED SIMD VLIW ARCHITECTURE (2003) (8)
Statistical noise margin estimation for sub-threshold combinational circuits (2008) (8)
Modeling resource sharing using FSM-SADF (2015) (7)
OPTCOMNET: Optimized Neural Networks for Low-Complexity Channel Estimation (2020) (7)
Mapping facial expression recognition algorithms on a low-power smart camera (2008) (7)
High Performance Image Processing using TTAs (1996) (7)
Designing Energy Efficient Approximate Multipliers for Neural Acceleration (2018) (7)
Clustering on the move. (2002) (7)
AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition (2018) (7)
Benchmarks for SmartCam Development. (2003) (7)
MOVE32INT Architecture and Programmer's Reference Manual (1994) (7)
Design style case study for embedded multi media compute nodes (2004) (7)
Automatic complex instruction identification for efficient application mapping onto ASIPs (2014) (7)
An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors (2013) (7)
Quantization of deep neural networks for accumulator-constrained processors (2020) (7)
A High Level Memory Energy Estimator based on Reuse Distance. (2005) (7)
Implementation of encryption algorithms on transport triggered architectures (2001) (7)
Future of GPGPU micro-architectural parameters (2013) (7)
A tuneable software cache coherence protocol for heterogeneous MPSoCs (2009) (7)
End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources (2016) (7)
Modular operational semantic specification of transport triggered architectures (1997) (7)
Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration (2008) (7)
MoESR: Blind Super-Resolution using Kernel-Aware Mixture of Experts (2022) (7)
IMACS: A Framework for Performance Evaluation of Image Approximation in a Closed-loop System (2019) (7)
A new approach for mechatronic system design: mechatronic design quotient (MDQ) (2005) (7)
Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling (2011) (6)
A predictable communication assist (2010) (6)
Sibyl: adaptive and extensible data placement in hybrid storage systems using online reinforcement learning (2022) (6)
Simulation and architecture improvements of atomic operations on GPU scratchpad memory (2013) (6)
Quantifying the common computational problems in contemporary applications (2011) (6)
Combining data and instruction memory energy optimizations for embedded applications (2005) (6)
Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency (2019) (6)
Modelling patterns for analysis and design of real-time systems (2006) (6)
Identifying bottlenecks in manufacturing systems using stochastic criticality analysis (2017) (6)
R-GPU (2016) (6)
Exploiting Inter and Intra Application Dynamism to Save Energy (2011) (6)
A configurable SIMD architecture with explicit datapath for intelligent learning (2016) (6)
The design space of garbage collection (1991) (6)
Patterns for Automatic Generation of Soft Real-time System Models (2009) (6)
Semantic concepts in product usage monitoring and analysis (2008) (6)
ADVISE. Performance evaluation of parallel VHDL simulation (1997) (6)
GPU-CC: a reconfigurable GPU architecture with communicating cores (2013) (6)
SCWC: Structured channel weight sharing to compress convolutional neural networks (2021) (6)
A step toward a scalable dynamic single assignment conversion (2003) (6)
End-to-end compute model of the Square Kilometre Array (2014) (6)
Configurable XOR Hash Functions for Banked Scratchpad Memories in GPUs (2016) (6)
Memory and Parallelism Analysis Using a Platform-Independent Approach (2019) (6)
Reusing Real-Time Systems Design Experience (2006) (6)
System Simulation of Memristor Based Computation in Memory Platforms (2020) (6)
Performance modelling and analysis using POOSL for an in-car navigation system (2006) (6)
Real-time Face Recognition on a Mixed SMID VLIW Architecture. (2003) (6)
A Unified Model for Analysis of Real-Time Properties (2004) (6)
Efficient communication support in predictable heterogeneous MPSoC designs for streaming applications (2013) (5)
Hierarchical rewriting and hiding of data dependent conditions to enable global loop transformations. (2004) (5)
UML Profile for modeling product observation (2008) (5)
A Study of the Potential of Locality-Aware Thread Scheduling for GPUs (2014) (5)
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths (2015) (5)
Smartcam Design Framework. (2003) (5)
Enabling MPSoC Design Space Exploration on FPGAs (2008) (5)
DC-SIMD : Dynamic communication for SIMD processors (2008) (5)
Data- and Task Parallel Image Processing on a Mixed SIMD-ILP Platform using Skeletons and Asynchronous RPC (2004) (5)
Efficient code generation for ASIPs with different word sizes (1997) (5)
A Scalable VLSI MIMD Routing Cell (1991) (5)
A framework for automatic custom instruction identification on multi-issue ASIPs (2014) (5)
Conservative application-level performance analysis through simulation of MPSoCs (2010) (5)
TDO-CIM: Transparent Detection and Offloading for Computation In-memory (2020) (5)
BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching (2014) (5)
1000 fps visual servoing on the reconfigurable wide SIMD processor (2010) (5)
Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory (2019) (5)
Platform Independent Software Analysis for Near Memory Computing (2019) (5)
Data Transport Reduction in Move Processors (1997) (4)
Energy efficient code generation for processors with exposed datapath (2011) (4)
The Utilization of a Fully Conngurable Microprocessor Development Environment for Rapid Vhdl Prototyping and Implementation of 'c'-based Algorithms (1996) (4)
Optimal iteration scheduling for intra- and inter-tile reuse in nested loop accelerators (2013) (4)
Thermal-aware scratchpad memory design and allocation (2010) (4)
Dataflow-Based Multi-ASIP Platform Approach for Digital Control Applications (2013) (4)
Quantization of Constrained Processor Data Paths Applied to Convolutional Neural Networks (2018) (4)
Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM (2016) (4)
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment (2006) (4)
Dealing with data dependent conditions to enable general global source code transformations (2009) (4)
Instruction Transfer And Storage Exploration for Low Energy VLIWs (2006) (4)
Analyzing CUDA’s Compiler through the Visualization of Decoded GPU Binaries (2012) (4)
A Linker for effective Whole-Program Optimization (1999) (4)
Web server controlled multi-tasking on a FPGA based multiprocessor platform (2009) (4)
Modeling FPGA-Based Systems via Few-Shot Learning (2021) (4)
An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA (2013) (4)
ConvFusion A Model for Layer Fusion in Convolutional Neural Networks (2021) (4)
Programming tensor cores from an image processing DSL (2020) (4)
Near Memory Acceleration on High Resolution Radio Astronomy Imaging (2020) (4)
PET-to-MLIR: A polyhedral front-end for MLIR (2020) (4)
On Efficiency of Transport Triggered Architectures in DSP Applications (2002) (4)
Distributed Smart Camera Calibration Using Blinking LED (2008) (4)
Registers On Demand: Integrated register allocation and instruction scheduling (1997) (4)
Global Program Optimization: Register Allocation of Static Scalar Objects (1999) (4)
Approximation Trade Offs in an Image-Based Control System (2020) (4)
Intra- and inter-processor hybrid performance modeling for MPSoC architectures (2008) (4)
Dissecting Tensor Cores via Microbenchmarks: Latency, Throughput and Numeric Behaviors (2022) (4)
VLIW Code Generation for a Convolutional Network Accelerator (2015) (4)
A Framework for Designing Efficient Deep Learning-Based Genomic Basecallers (2022) (3)
Design and Evaluation of Communication Processors supporting Message Passing in Distributed Memory Systems (1991) (3)
A data-reuse aware accelerator for large-scale convolutional networks (2014) (3)
Attentive Decision-making and Dynamic Resetting of Continual Running SRNNs for End-to-End Streaming Keyword Spotting (2022) (3)
Run-time reconfiguration of communication in SIMD architectures (2006) (3)
Multimedia Multiprocessor Systems: Analysis, Design and Management (2010) (3)
Conclusions and Open Problems (2011) (3)
Immediate optimization for compressed transport triggered architecture instructions (2003) (3)
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators (2021) (3)
L0 Cluster Synthesis and Operation Shuffling (2004) (3)
Reaching intrinsic compute efficiency requires adaptable micro-architectures (2016) (3)
CSDFa: A Model for Exploiting the Trade-Off between Data and Pipeline Parallelism (2016) (3)
ILP architectures: trading hardware for software complexity (1997) (3)
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation (2021) (3)
Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware (2022) (3)
Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project (2017) (3)
A Programmable ANSI C Code Transformation Engine. (1999) (3)
Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note) (2000) (3)
An overview of application scenario usage in streaming-oriented embedded system design (2006) (3)
Towards stronger property preservation in real-time system synthesis (2006) (3)
Fast Huffman decoding by exploiting data level parallelism (2010) (3)
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation (2002) (3)
The OSI Model Applied to MIMD Communication Processor Design (1993) (3)
Integrated Register Allocation and Software Pipelining (1998) (3)
Dataflow model for credit-controlled static-priority arbitration (2010) (3)
Sharper WCET upper bounds using automatically detected scenarios (2005) (3)
A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension (2013) (3)
An MPSoC design approach for multiple use-cases of throughput constrainted applications (2011) (3)
Exploiting Specification Modularity to Prune the Optimization-Space of Manufacturing Systems (2018) (3)
SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species (2015) (3)
Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures (2017) (2)
Real-time audio processing for hearing aids using a model-based bayesian inference framework (2020) (2)
A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor (2015) (2)
Collaborative detection of repetitive behavior by multiple uncalibrated cameras (2015) (2)
UML profile for modeling system observation (2008) (2)
Fault Tolerant FPGAs: Where to Spend the Effort? (2019) (2)
PhD forum: A cyber-physical system approach to embedded visual servoing (2011) (2)
Accurate run-time performance prediction for multi-application multiprocessor systems (2008) (2)
Reusing systems design experience through modelling patterns (2007) (2)
Supplementary Materials to Adaptive and Transparent Cache Bypassing for GPUs (2015) (2)
NMPO: Near-Memory Computing Profiling and Offloading (2021) (2)
Automatic heapmanagement and realtime performance (1991) (2)
Robust Bayesian Beamforming for Sources at Different Distances with Applications in Urban Monitoring (2019) (2)
Augmenting the Exploration Space for Global Loop Transformations by Systematic Preprocessing of Data Dependent Constructs. (2004) (2)
Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction (2012) (2)
ViewCorrect: Predictable Co-Design for distributedembedded mechatronic control systems (2005) (2)
Construction and exploitation of VLIW asips with multiple vector-widths (2014) (2)
Software Transformations to Reduce Instruction Memory Power Consumption using a Loop Buffer (2003) (2)
Towards Efficient Code Generation for Exposed Datapath Architectures (2019) (2)
Dynamic-SIMD for lens distortion compensation (2006) (2)
NAPEL (2019) (2)
Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection (2021) (2)
Approximation-Aware Design of an Image-Based Control System (2020) (2)
Correctness-preserving synthesis for real-time control software (2006) (2)
A new flexible VHDL simulator (1994) (2)
Energy Efficient Code Generation for Streaming Applications (2009) (2)
Efficient Tensor Cores support in TVM for Low-Latency Deep learning (2021) (2)
Efficient Architecture Exploration of a Clustered Loop Buffer (2006) (2)
Handling Dynamism in Embedded System Design by Application Scenarios (2006) (2)
Property-preserving synthesis for unified conrol- and data-oriented models. (2006) (2)
The Potential of Exploiting Coarse-Grain Task Parallelism from Sequential Programs (1997) (2)
Cross-Domain Modeling and Optimization of High-Speed Visual Servo Systems (2018) (2)
How Flexible is Your Computing System? (2021) (2)
Error computation for predictable real-time software synthesis (2011) (2)
Fixed-point arithmetic for ASIP code generation (1998) (2)
OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory (2022) (2)
Hardware Approximation of Exponential Decay for Spiking Neural Networks (2021) (2)
Synthesis for Unified Control- and Data-Oriented Models (2005) (2)
Reduction operator for wide-SIMDs reconsidered (2014) (2)
How to train accurate BNNs for embedded systems? (2022) (2)
Multi-granular Arithmetic in a Coarse-Grain Reconfigurable Architecture (2016) (1)
Automatic Memory-Efficient Scheduling of CNNs (2019) (1)
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture (2022) (1)
Low- and Mixed-Precision Inference Accelerators (2022) (1)
Distributed Heapmanagement using reference weights (1991) (1)
Limited Address Range Architecture for Reducing Code Size in Embedded Processors (2003) (1)
A comparative study of energy-efficient multiplier design using data-width-aware methodology. (2012) (1)
Methodology for propagating technology trade-offs over memory modules to the application level (2003) (1)
SySCIM: SystemC-AMS Simulation of Memristive Computation In-Memory (2022) (1)
Parallelism support in SIMD/VLIW Image processing architectures (2005) (1)
Multimedia Multiprocessor Systems (2010) (1)
Trends and Challenges in Multimedia Systems (2011) (1)
Interconnect exploration for future wire dominated technologies (2002) (1)
Application Modeling and Scheduling (2011) (1)
Advanced Signal Propagation (2002) (1)
Characterization of Mems Microphone Sensitivity and Phase Distributions with Applications in Array Processing (2021) (1)
LEAPER: Fast and Accurate FPGA-based System Performance Prediction via Transfer Learning (2022) (1)
(AS): Accelerator Synthesis using Algorithmic Skeletons for Rapid Design Space Exploration (2014) (1)
LocalNorm: Robust Image Classification through Dynamically Regularized Normalization (2019) (1)
Methodology for building processor design space exploration frameworks (2005) (1)
Multiprocessor System Design and Synthesis (2011) (1)
Impact of ILP-improving Code Transformations on Intruction Memory Energy (2007) (1)
Array Based Structure Loop Transformations For Cache Miss Reduction (2000) (1)
Design style case study for computer nodes of a heterogeneous NoC platform (2004) (1)
xCPS: A tool to eXplore Cyber Physical Systems (2015) (1)
Data Flow Computation Models (2014) (1)
MAMPSx : A Design Methodology for Rapid System-Level Exploration , Synthesis of Heterogeneous SoC on FPGA (2013) (1)
A Scalable Communication Processor Design supporting Systolic Communication (1991) (1)
Parallel object-oriented specification language (2008) (1)
Remove : A Computer Architecture Designed for Modern VLSI Technology (1999) (1)
Applying SIMD to optical character recognition (OCR) (2008) (1)
Branching-Time Property Preservation Between Real-Time Systems (2006) (1)
Code Positioning for VLIW Architectures (2001) (1)
A Framework For Design of Heterogeneous Multi-processor Embedded Systems (1997) (1)
Instruction and Data Memory Energy Trade-off using a High-level Model (Abstract) (2004) (1)
Resource Assignment in a Compiler for Transport Triggered Architectures (1996) (1)
Programming the GPU-CC architecture using a visual programming language (2013) (1)
On Composability of MPSoC Applications (2006) (1)
FPGA Implementation of 1000 fps visual servoing for repetitive structures (2010) (1)
Link-time effective whole-program optimizations (2000) (1)
The effect of process switches on branch prediction accuracy (2000) (1)
Performance evaluation of concurrently executing parallel applications on multi-processor systems (2009) (1)
Performance Evaluation of Parallel VHDL Simulation (1994) (1)
Impact of ILP-improving code transformations on loop buffer energy (2007) (1)
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis (2013) (1)
Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures (2022) (1)
Bitwise Neural Network Acceleration: Opportunities and Challenges (2019) (1)
Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems (2019) (0)
A Low-Energy Wide SIMD Architecture with Explicit Datapath (2014) (0)
Dataflow modeling ad analysing software-de ned radio (2011) (0)
High-level synthesis of massively parallel vision architectures for 100000 frames-per-second visual servo control (2013) (0)
pace Exploration Algorithm For Heterogeneous rocessor Embedded System Design (2009) (0)
Automated Design of an ASIP for Image Processing Applications (Research Note) (2000) (0)
CONVOLVE: Smart and seamless design of smart edge processors (2022) (0)
Conclusions and Further Work (2014) (0)
The Blocks Framework (2021) (0)
(AS)2 : accelerator synthesis using algorithmic skeletons (2014) (0)
Neuromorphic Simulator Track : Deep Learning , Embedded Systems , Software Programming Capacity group : Electronic Systems Supervisors (2020) (0)
Using Multiple Paths in NoCs for Guaranteed Resource Allocation and Improved Best Effort Performance in NoCs. (2005) (0)
Approximate Inference by Kullback-Leibler Tensor Belief Propagation (2020) (0)
Towards predictability in real-time embedded system design. Invited presentation (2005) (0)
Energy, Area, and Performance Evaluation (2021) (0)
DOAS: an object oriented architecture supporting secure languages (1989) (0)
CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures (2021) (0)
Closed-Loop Evaluation of an Embedded Visual Servo System (2012) (0)
Using performance prediction to enable architectural choice prior to the development of target specific code (2011) (0)
Flexible application mapping environment (FAME) (2001) (0)
SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computation (2023) (0)
Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems (2011) (0)
BOMP-NAS: Bayesian Optimization Mixed Precision NAS (2023) (0)
Instruction and Data Memory Energy Exploration (Abstract) (2004) (0)
LoopOpt: Declarative Transformations Made Easy (2021) (0)
GPU shared memory hash functions (2015) (0)
Application Driven MIMD Communication Processor Design (1994) (0)
Concept of the Blocks Architecture (2021) (0)
UML Profile for Modeling Product Observation Version 1 . 0 (2008) (0)
Heuristics forScenario Creation toEnable General Lo Trans forations (2007) (0)
Generalized GPU voting algorithm (2011) (0)
Highly efficient historgramming on many-core GPU architectures (2010) (0)
Case Study: The BrainSense Platform (2021) (0)
SE1: What Technologies Will Shape the Future of Computing? (2021) (0)
DMA-aware scheduling for multiprocessor systems-on-chip. (2010) (0)
LEAPER: Modeling Cloud FPGA-based Systems via Transfer Learning (2022) (0)
Minimal data transfer by iteration reordering for loop nest accelerators (2013) (0)
AivoTTA (2018) (0)
BrainWave (2020) (0)
Probabilistic Performance Prediction (2011) (0)
CELR: Cloud Enhanced Local Reconstruction from low-dose sparse Scanning Electron Microscopy images (2022) (0)
Predicting Implementation Accuracy for Real-Time Control Systems (2005) (0)
Research SoftReliability:An InterdisciplinaryApproach withaUser-SystemFocus (2008) (0)
CGRA Background and Related Work (2021) (0)
Partial Evaluation in Junction Trees (2022) (0)
Thermal-Aware Scratchpad . . . (0)
Visualization, modeling and steering: a case study in computational sciences. (1997) (0)
Automated extraction of analysable models from disciplined dataflow programs (2013) (0)
SoftReliability : An InterdisciplinaryApproach withaUser – SystemFocus (2008) (0)
Optimization Through Recomputation in the Polygedrak Model; Work in progress (2018) (0)
A design framework for low energy wide SIMD architectures with explicit datapath (2013) (0)
Accelerating Video Object Detection by Exploiting Prior Object Locations (2022) (0)
BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs (2020) (0)
Session details: Design space exploration for embedded systems (2002) (0)
A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor (2014) (0)
Iterative Probabilistic Performance Prediction for (2010) (0)
A Comprehensive Analytic Model for Parallel Machines (2015) (0)
L0 buffer energy optimization through scheduling and exploration (2004) (0)
Architectural Model (2021) (0)
SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components (2022) (0)
Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude (2018) (0)
Power consumption reduction methods using loop transformations. (2000) (0)
Algorithm development for scalable processor systems based on transport triggered architectures (1999) (0)
Automatic Model Generation for Evaluation of Scenario Creation Heuristics. (2006) (0)
Automatic complex instruction identification for efficient application mapping onto application-specific instruction set processors (2015) (0)
Automatic complex instruction identification for efficient application mapping onto application-specific instruction set processors (2015) (0)
UXsuite -Product Experience Analytics (2010) (0)
ReMeCo: Reliable Memristor-Based In-Memory Neuromorphic Computation (2023) (0)
Resource Modeling and Compile Time Scheduling (2014) (0)
SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator (2022) (0)
Progressive Raising in Multi-level IR (2021) (0)
Novel reduction algorithms optimized for low-power wide SIMD processors (2013) (0)
An Efficient FPGA Implementation for Real-Time and Low-Power UAV Object Detection (2022) (0)
Multiple Use-cases System Design (2011) (0)
Chapter 1 PREDICTABILITY IN REAL-TIME SYSTEM DEVELOPMENT (2005) (0)
Quantization: how far should we go? (2022) (0)
Scenario creation for low power embedded systems. (2005) (0)
BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC (2022) (0)
Session details: Interconnect Exploration for Future Wire Dominated Technologies (2002) (0)
Evaluation of a Potential for Automatic SIMD Parallelization of Embedded Applications (2007) (0)
Thermal-aware address decoding in scratchpad memories (2010) (0)
Taming the State-space Explosion in the Makespan Optimization of Flexible Manufacturing Systems (2021) (0)
for Modeling Product Observation (2008) (0)
THOR - A Neuromorphic Processor with 7.29G TSOP$^2$/mm$^2$Js Energy-Throughput Efficiency (2022) (0)
MeSAP: A fast analytic power model for DRAM memories (2017) (0)
Implementing Time-Constrained Applications on a Predictable MPSoC (2018) (0)
Aerial networking communication solutions using Micro Air Vehicle (MAV) (2014) (0)
Interconnect and Architecture Planning: Global interconnect trade-off for technology over memory modules to application level: case study. (2003) (0)
Road through the interconnect red brick wall (2003) (0)
Mode-Controlled Data Flow (2014) (0)
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models (2023) (0)
Branch history register cache (2002) (0)
Automatic Scenario Detect ion for Improved W C ET Estimation (2005) (0)
Model-driven design of real-time systems (2006) (0)
Embedded Systems Design (2006) (0)
Hardware- and Situation-Aware Sensing for Robust Closed-Loop Control Systems (2021) (0)
A Comparison of Different Multithreading Architectures (1997) (0)
Aggressive Data Transfer Reduction by loop fusion and re-computation for dedicated accelerators (2015) (0)
Design of Heterogenous Multi-processor Em Applying Functional Pipelinin (1997) (0)
Thermal-aware scratchpad memory. (2010) (0)
Optimization through recomputation in the polyhedral model (2018) (0)
DNAsim: Evaluation Framework for Digital Neuromorphic Architectures (2022) (0)
GPU mapping of convolutional neural networks for fast vision applications (2011) (0)
Exploiting wiring hierarchy and system design to surpass the interconnect red brick wall (2002) (0)
FastMulti-Dimension Multi-Choice Knapsack (2006) (0)
Embedded processor Design using Transport Triggered Architectures. (2001) (0)
PROGRESS white papers 2006:embedded systems design, networks and connected systems, verification and validation, networks on chip (2006) (0)
Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures (2022) (0)
Data locality modeling for convolutional neural networks (2012) (0)
Cluster Generation and Scheduling for Instruction (L0) Clusters (2003) (0)
Methodology for building processor design space exploration (2007) (0)
Conclusions and future work (2020) (0)

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