Hideo Fujiwara
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Computer Science
Hideo Fujiwara's Degrees
- PhD Computer Science University of Tokyo
- Masters Computer Science University of Tokyo
- Bachelors Computer Science University of Tokyo
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(Suggest an Edit or Addition)Hideo Fujiwara's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- On the Acceleration of Test Generation Algorithms (1983) (819)
- Logic Testing and Design for Testability (1985) (307)
- The Complexity of Fault Detection Problems for Combinational Logic Circuits (1982) (152)
- A Design of Programmable Logic Arrays with Universal Tests (1981) (105)
- A test methodology for interconnect structures of LUT-based FPGAs (1996) (82)
- Implementing a Built-In Self-Test PLA Design (1985) (73)
- Universal Fault Diagnosis for Lookup Table FPGAs (1998) (67)
- Efficient test solutions for core-based designs (2004) (65)
- ON THE ACCELERATION OF TEST GENERATION ALGORlTHMS (1995) (61)
- Universal test complexity of field-programmable gate arrays (1995) (59)
- A New PLA Design for Universal Testability (1984) (58)
- Functional Constraints vs. Test Compression in Scan-Based Delay Testing (2006) (58)
- Parity-Scan Design to Reduce the Cost of Test Application (1992) (57)
- Computational complexity of controllability/observability problems for combinational circuits (1988) (57)
- SPIRIT: a highly robust combinational test generation algorithm (2001) (56)
- Easily Testable Sequential Machines with Extra Inputs (1975) (56)
- Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction (2007) (56)
- Secure and testable scan design using extended de Bruijn graphs (2010) (47)
- On the Computational Complexity of System Diagnosis (1978) (46)
- An Easily Testable Design of Programmable Logic Arrays for Multiple Faults (1983) (45)
- Design for strong testability of RTL data paths to provide complete fault efficiency (2000) (44)
- A layout adjustment problem for disjoint rectangles preserving orthogonal order (1998) (43)
- Instruction-Based Self-Testing of Delay Faults in Pipelined Processors (2006) (43)
- System-on-chip test scheduling with reconfigurable core wrappers (2006) (42)
- Partial Scan Approach for Secret Information Protection (2009) (42)
- Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip (2016) (39)
- A circuit failure prediction mechanism (DART) for high field reliability (2009) (39)
- An efficient scan tree design for test time reduction (2004) (38)
- Optimal granularity of test generation in a distributed system (1989) (38)
- An optimal time expansion model based on combinational ATPG for RT level circuits (1998) (35)
- Design and analysis of multiple weight linear compactors of responses containing unknown values (2005) (35)
- A memory grouping method for sharing memory BIST logic (2006) (34)
- A new definition and a new class of sequential circuits with combinational test generation complexity (2000) (34)
- An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images (1995) (33)
- Power constrained preemptive TAM scheduling (2002) (33)
- A non-scan DFT method at register-transfer level to achieve complete fault efficiency (2000) (32)
- An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers (2007) (29)
- A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST (2008) (28)
- Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints (2007) (27)
- Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip (2007) (27)
- Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals (1983) (27)
- Faster-than-at-speed test for increased test quality and in-field reliability (2011) (25)
- Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores (2002) (24)
- Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution (2003) (24)
- Power-Constrained Test Scheduling for Multi-Clock Domain SoCs (2006) (24)
- Low-Cost Hardening of Image Processing Applications Against Soft Errors (2006) (23)
- A Failure Prediction Strategy for Transistor Aging (2012) (23)
- Untestable Fault Identification in Sequential Circuits Using Model-Checking (2008) (22)
- Some Existence Theorems for Probabilistically Diagnosable Systems (1978) (22)
- Design of Diagnosable Sequential Machines Utilizing Extra Outputs (1974) (22)
- Improving test effectiveness of scan-based BIST by scan chain partitioning (2005) (21)
- Non-scan design for testability for synchronous sequential circuits based on conflict analysis (2000) (21)
- Instruction-based delay fault self-testing of processor cores (2004) (21)
- Design for hierarchical two-pattern testability of data paths (2001) (20)
- Test resource partitioning and optimization for SOC designs (2003) (19)
- Testing for the programming circuit of LUT-based FPGAs (1997) (19)
- Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST (2007) (19)
- Efficient template generation for instruction-based self-test of processor cores (2004) (18)
- A snapshot algorithm for distributed mobile systems (1996) (18)
- A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency (2000) (18)
- A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models (2008) (18)
- Clustering algorithms in ad hoc networks (2005) (18)
- Integrated test scheduling, test parallelization and TAM design (2002) (17)
- On Closedness and Test Complexity of Logic Circuits (1981) (17)
- Localized random access scan: Towards low area and routing overhead (2008) (17)
- Partial scan design methods based on internally balanced structure (1998) (16)
- Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing (2010) (16)
- Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps (2001) (16)
- An efficient test generation algorithm based on search state dominance (1992) (16)
- A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings (2002) (16)
- Design for Testability of Software-Based Self-Test for Processors (2006) (15)
- A non-scan DFT method for controllers to achieve complete fault efficiency (1998) (15)
- Three-valued neural networks for test generation (1990) (15)
- A method of test generation for path delay faults using stuck-at fault test generation algorithms (2003) (15)
- RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage (2010) (14)
- False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults (2007) (14)
- Thermal-aware test scheduling for NOC-based 3D integrated circuits (2013) (14)
- Power-Constrained SOC Test Schedules through Utilization of Functional Buses (2006) (14)
- A design of programmable logic arrays with random pattern-testability (1988) (14)
- A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability (2001) (13)
- Fault-Tolerant and Self-Stabilizing Protocols Using an Unreliable Failure Detector (2000) (13)
- Temperature-Variation-Aware Test Pattern Optimization (2011) (13)
- Test generation for acyclic sequential circuits with hold registers (2000) (13)
- Hierarchical BIST: Test‐per‐clock BIST with low overhead (2007) (13)
- Instruction-based delay fault self-testing of pipelined processor cores (2005) (13)
- Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System (1995) (12)
- A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead (1987) (12)
- Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture (2007) (11)
- Design for Testability for Complete Test Coverage (1984) (11)
- Connection Assignments for Probabilistically Diagnosable Systems (1978) (11)
- A unified test and fault-tolerant multicast solution for network-on-chip designs (2016) (10)
- Optimal system-on-chip test scheduling (2003) (10)
- Secure scan design using shift register equivalents against differential behavior attack (2011) (10)
- Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing (2018) (10)
- A New Class of Sequential Circuits with Acyclic Test Generation Complexity (2006) (10)
- Fast false path identification based on functional unsensitizability using RTL information (2009) (10)
- SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design (2010) (10)
- Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints (2009) (10)
- Delay Fault Testing of Processor Cores in Functional Mode (2005) (9)
- Software-based delay fault testing of processor cores (2003) (9)
- On the complexity of universal fault diagnosis for look-up table FPGAs (1997) (9)
- Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits (2011) (9)
- RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences (2009) (9)
- A method of test generation for path delay faults in balanced sequential circuits (2002) (9)
- Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores (2007) (9)
- Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults (1997) (9)
- On Minimization of Test Application Time for RAS (2010) (9)
- Single-control testability of RTL data paths for BIST (2000) (9)
- A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead (1987) (9)
- Design for Testability Based on Single-Port-Change Delay Testing for Data Paths (2005) (8)
- A Low Power Deterministic Test Using Scan Chain Disable Technique (2006) (8)
- Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses (2007) (8)
- A BIST method based on concurrent single-control testability of RTL data paths (2001) (8)
- Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests (2006) (8)
- Test Scheduling for Memory Cores with Built-In Self-Repair (2007) (8)
- A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation (2015) (8)
- Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers (2015) (8)
- New DFT techniques of non-scan sequential circuits with complete fault efficiency (1998) (8)
- Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints (2007) (7)
- A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint (2008) (7)
- A DFT method for core-based systems-on-a-chip based on consecutive testability (2001) (7)
- A latency-optimal superstabilizing mutual exclusion protocol (1997) (7)
- Fault-dependent/independent Test Generation Methods for State Observable FSMs (2007) (7)
- An extended class of sequential circuits with combinational test generation complexity (2002) (7)
- Area and time co-optimization for system-on-a-chip based on consecutive testability (2003) (7)
- Non-scan design for testable data paths using thru operation (1997) (7)
- Handling the pin overhead problem of DFTs for high-quality and at-speed tests (2002) (7)
- Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops (2005) (7)
- Design for consecutive transparency of cores in system-on-a-chip (2003) (7)
- A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency (2005) (7)
- On theAcceleration of TestGeneration Algorithms (1983) (7)
- Static and dynamic test sequence compaction methods for acyclic sequential circuits using a time expansion model (1999) (6)
- F-scan: An approach to functional RTL scan for assignment decision diagrams (2009) (6)
- Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST (2005) (6)
- Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems) (2005) (6)
- Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption (2000) (6)
- A Self-Stabilizing Spanning Tree Protocol that Tolerates Non-quiescent Permanent Faults (2002) (6)
- Seed Ordering and Selection for High Quality Delay Test (2010) (6)
- Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing (2007) (5)
- A method of unsensitizable path identification using high level design information (2010) (5)
- A parallel algorithm for weighted distance transforms (1997) (5)
- Spirit: satisfiability problem implementation for redundancy identification and test generation (2000) (5)
- A high-level synthesis approach to partial scan design based on acyclic structure (1999) (5)
- Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester (2007) (5)
- RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC (2010) (5)
- A high-level synthesis method for weakly testable data paths (1998) (5)
- Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design (2011) (5)
- On the synthesis of synchronizable finite state machines with partial scan (1998) (5)
- Fault‐tolerant distributed algorithms for autonomous mobile robots with crash faults (1997) (5)
- LORES - Logic Reorganization System (1978) (5)
- Aging test strategy and adaptive test scheduling for SoC failure prediction (2010) (5)
- A sequential circuit structure with combinational test generation complexity and its application (1997) (5)
- A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification (2009) (5)
- Introduction to Logic Testing (1985) (4)
- Delay fault ATPG for F-scannable RTL circuits (2010) (4)
- Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design (2013) (4)
- NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints (2008) (4)
- Constrained ATPG for functional RTL circuits using F-Scan (2010) (4)
- Classification of Sequential Circuits Based on tauk Notation and Its Applications (2005) (4)
- Fault set partition for efficient width compression (2001) (4)
- Classification of sequential circuits based on /spl tau//sup k/ notation (2004) (4)
- A New Scan Design Technique Based on Pre-Synthesis Thru Functions (2006) (4)
- A response compactor for extended compatibility scan tree construction (2009) (4)
- Graph theoretic approach for scan cell reordering to minimize peak shift power (2010) (4)
- A scheduling problem in test generation (1995) (4)
- Balanced Secure Scan: Partial Scan Approach for Secret Information Protection (2011) (4)
- Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits (2010) (4)
- A cost optimal parallel algorithm for weighted distance transforms (1999) (4)
- On the Non-scan BIST Schemes under Power Constraints for RTL Data Paths (2003) (4)
- Testable design of sequential circuits with improved fault efficiency (2001) (3)
- Some tau-equivalent classes of sequential circuits (2004) (3)
- Enhancing random-pattern coverage of programmable logic arrays via masking technique (1988) (3)
- LFSR-Based Deterministic TPG for Two-Pattern Testing (2000) (3)
- F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG (2011) (3)
- Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach (2010) (3)
- Classification of Sequential Circuits Based on Combinational Test Generation Complexity (2004) (3)
- Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation (2005) (3)
- Period of Grace : A New Paradigm for Efficient Soft Error Hardening (2006) (3)
- Test pattern selection to optimize delay test quality with a limited size of test set (2010) (3)
- Enhancement of Test Environment Generation for Assignment Decision Diagrams (2015) (3)
- A DFT Method for Time Expansion Model at Register Transfer Level (2007) (3)
- Faster-ThanAt-Speed Test for Increased Test Quality and InField Reliability (2015) (3)
- Test Pattern Ordering and Selection for High Quality Test Set under Constraints (2012) (3)
- Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power (2010) (3)
- Fast and effective fault simulation for path delay faults based on selected testable paths (2007) (3)
- Theorems for Separable Primary Input Faults in Internally Balanced Structures (2000) (3)
- Testing superscalar processors in functional mode (2005) (3)
- High-Level Synthesis for Weakly Testable Data Paths (1998) (3)
- Fault Detection Capability of an O ( m・n ) Test Generation Algorithm for PLAs (1991) (3)
- A Class of Linear Space Compactors for Enhanced Diagnostic (2005) (3)
- Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester (2006) (3)
- Design for two-pattern testability of controller-data path circuits (2002) (3)
- Test synthesis for datapaths using datapath-controller functions (2003) (3)
- Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects (2008) (3)
- Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture (2005) (3)
- Reducibility of sequential test generation to combinational test generation for several delay fault models (2003) (2)
- Sequential test generation based on circuit pseudo-transformation (1997) (2)
- Test research in Japan (1988) (2)
- Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture (2006) (2)
- An Approach to RTL False Path Mapping Using Uniqueness of Paths (2009) (2)
- A self‐stabilizing max‐heap protocol in tree networks (2003) (2)
- Design for testability and built-in self-test for VLSI circuits (1986) (2)
- Parallel algorithms for selection on the BSP and BSP* models (2002) (2)
- Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch (2006) (2)
- Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing (2007) (2)
- A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits (2006) (2)
- Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints (2012) (2)
- A Simple Parallel Algorithm for the Medial Axis Transform (Special Issue on Architectures Algorithms and Networks for Massively parallel Computing) (1996) (2)
- F-Scan: A DFT Method for Functional Scan at RTL (2011) (2)
- SR-Quasi-Equivalents : Yet Another Approach to Secure and Testable Scan Design (2015) (2)
- A New Data Structure for Complete Implication Graph with Application for Static Learning (2000) (2)
- Software-Based Self-Test of Processors for Stuck-at Faults and Path Delay Faults (2005) (2)
- Strong self-testability for data paths high-level synthesis (2000) (2)
- Preemptive System-on-Chip Test Scheduling (2004) (2)
- SelfStabilizing WaitFree Clock Synchronization with Bounded Space (1998) (2)
- Testing for the Programming Circuit of SRAM-Based FPGAs (1999) (2)
- Properties of Generalized Feedback Shift Registers for Secure Scan Design (2016) (2)
- Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability (2005) (2)
- A method of search space pruning based on search state dominance (1994) (2)
- Functional Unit and Register Binding Methods for Hierarchical Testability (2015) (2)
- Max-testable class of sequential circuits having combinational test generation complexity (2004) (2)
- A Search Space Pruning Method for Test Pattern Generation using Search State Dominance (1993) (2)
- A Binding Method for Hierarchical Testing Using Results of Test Environment Generation (2013) (2)
- Enabling False Path Identification from RTL for Reducing Design and Test Futileness (2010) (2)
- Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents (2013) (2)
- Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC (2009) (2)
- Internally Balanced Structure with Hold and Switching Functions (2003) (2)
- A Functional Test Method for State Observable FSMs (2005) (2)
- Test Scheduling for Multi-Clock Domain SoCs under Power Constraint (2008) (1)
- Preemptive power constrained TAM scheduling for scan-based system-on-chip (2002) (1)
- A new class of easily testable assignment decision diagrams (2010) (1)
- Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE (2007) (1)
- A method of test generation for weakly testable data paths using test knowledge extracted from RTL description (1999) (1)
- An Effective Design for Hierarchical Test Generation Based on Strong Testability (2005) (1)
- The Complexity of Testing (1985) (1)
- SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般) (2000) (1)
- A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation (2007) (1)
- RedSOCs-3 D : Thermal-safe Test Scheduling for 3 D-Stacked SOC (2015) (1)
- A framework for low complexity static learning (2001) (1)
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般) (2000) (1)
- A scheduling method for hierarchical testability based on test environment generation results (2016) (1)
- Fast test pattern generation using a multiprocessor system (1988) (1)
- Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System (1997) (1)
- Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram (2015) (1)
- Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis (2003) (1)
- An Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100% Fault Efficiency (2000) (1)
- A scheduling method in high-level synthesis for acyclic partial scan design (2002) (1)
- A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips (2006) (1)
- A causal broadcast protocol for distributed mobile systems (2001) (1)
- Efficient and effective test program generation for software-based self-test of pipelined processors (2006) (1)
- Improving test quality of scan-based BIST by scan chain partitioning (2003) (1)
- BIST pretest of ICs: risks and benefits (2006) (1)
- TAM Design and Optimization for Transparency-Based SoC Test (2007) (1)
- A design methodology to realize delay testable controllers using state transition information (2004) (1)
- Non-scan design for testability based on fault oriented conflict analysis (2002) (1)
- An approach to test synthesis from higher level (1998) (1)
- Parallel algorithms for connected-component problems of gray-scale images (1997) (1)
- A DFT selection method for reducing test application time of system-on-chips (2003) (1)
- Test generation complexity for stuck-at and path delay faults based on tau[k] - notation (2005) (1)
- Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost (2007) (1)
- Test Generation and Design-for-Testability Based on Acyclic Structure with Hold Registers (2000) (1)
- A framework for low complexitgy static learning (2001) (1)
- An Approach for Verification Assertions Reuse in RTL Test Pattern Generation (2010) (1)
- Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers (2002) (1)
- An approach to the synthesis of synchronizable finite state machines with partial scan (1996) (1)
- Software-based delay fault self-testing of pipelined processor cores (2004) (1)
- Design for Built-In-Self-Testing (1985) (1)
- Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation (2005) (1)
- Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips (2008) (1)
- Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths (2005) (1)
- Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST (2005) (1)
- On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time (2008) (1)
- Improving test quality of scan-based BIST by scan chain partitioning (2003) (1)
- Universal Testing for Linear Feed-Forward/Feedback Shift Registers (2020) (1)
- Over-testing reduction for delay faults through false path exclusion using RTL information (2007) (1)
- A design scheme for delay fault testability of controllers using state transition information (2003) (0)
- A Framework for Low Complexity Static Learning 1 (2001) (0)
- Path-Based Resource Binding to Reduce Delay Fault Test Cost ∗ (2015) (0)
- Combinational Test Generation Complexity and Non-Scan Design-for-Testability Method (2003) (0)
- Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般) (2006) (0)
- Design to Minimize the Cost of Test Generation (1985) (0)
- A New Non-Scan DFT Method Based on the Time Expansion Model for RTL Controller-Datapath Circuits (2015) (0)
- Parallel Algorithms for the All Nearest Neighbors of Binary Image on the BSP Model (2000) (0)
- Parallel Algorithms for Selection on the BSP Model and the BSP ∗ Model (1999) (0)
- Extended Compatibilities for Scan Tree Construction (2015) (0)
- Observation-Point Selection at Register-Transfer Level to Increase Defect Coverage for Functional Test Sequences § (2009) (0)
- Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design (2016) (0)
- Power-constrained DFT algorithms for non-scan BIST-able RTL data paths (2004) (0)
- One More Class of Sequential Circuits having Combinational Test Generation Complexity (2015) (0)
- Parallel algorithms for all nearest neighbors of binary images on the BSP model (1999) (0)
- FOREWORD (Special Issue on Synthesis and Verification of Hardware Design) (1996) (0)
- Scan Design for Sequential Logic Circuits (1985) (0)
- Test synthesis for strongly testable datapaths using datapath-controller functions (2003) (0)
- Design to Minimize the Cost of Test Application (1985) (0)
- A Reconfigurable Wrapper Design for Multi-Clock Domain Cores (2015) (0)
- Optimizing Delay Test Quality with a Limited Number of Test Set (2015) (0)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint (2003) (0)
- Design & Test Education in Asia (2004) (0)
- Designing Power-aware Wrappers for Multi-clock Domain Cores Using Clock Domain Partitioning (2015) (0)
- A Non-scan DFT Method at Register-Transfer Level to Achieve 100 % Fault Efficiency (2003) (0)
- Efficient Constraint Extraction for Template-Based Processor Self-Test Generation (2005) (0)
- Introduction to Design for Testability (1985) (0)
- A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification (2010) (0)
- Design for consecutive transparency of RTL circuits (2002) (0)
- A New Design-for-Testability Method Based on Thru-Testability (2011) (0)
- A method of test plan grouping to shorten test length for RTL data paths under a test controller area constraint (2003) (0)
- A Test Generation Method Based on k-Cycle Testing for Finite State Machines (2018) (0)
- Design for Testability (1985) (0)
- A nonscan DFT method for controllers to provide complete fault efficiency (2002) (0)
- Non-scan design for testability for mixed RTL circuits with both data paths and controller via conflict analysis (2003) (0)
- Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms (2009) (0)
- Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation (2007) (0)
- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability (2007) (0)
- Non-scan Design for Single-Port-Change Delay Fault Testability (2006) (0)
- Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術) (2007) (0)
- Efficient Mutual Exclusion Algorithm for High System Congestion (2009) (0)
- A synthesis method to propagate false path information from RTL to gate level (2010) (0)
- RT-Level Identification of Potentially Testable Initialization Faults (2015) (0)
- D-10-18 An Approach to Temperature Control During VLSI Test (2009) (0)
- ATS 2003 Best Paper Award (2003) (0)
- An Optimal Test Bus Design for Transparency-based SoC Test (2015) (0)
- Test Generation and DFT Based on Partial Thru Testability (2015) (0)
- Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors (2008) (0)
- Electrical Behavior of GOS Faults in Domino Logic (2005) (0)
- A Path Delay Test Generation Method for Sequential Circuits Based on Reducibility to Combinational Test Generation (2015) (0)
- An approach to reduce over-testing of path delay faults in data paths using RT-level information (2006) (0)
- Test Generation for Sequential Circuits with Partial Thru Testability (2009) (0)
- Observation-Point Selection at the Register-Transfer Level to Enhance Defect Coverage for Functional Test Sequences ∗ (2015) (0)
- Perfect error identification in at-speed BIST environment (2015) (0)
- On the Test Sequence Compaction for Acyclic Sequential Circuits Using Time-Expansion Model (1998) (0)
- SPIRIT : A High Robust Combinational Test Generation Algorithm^1 (2000) (0)
- 1 Defect Level vs . Yield and Fault Coverage in the Presence of an Imperfect BIST (2015) (0)
- Matrices of Multiple Weights for Test Response Compaction with Unknown Values (2015) (0)
- Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints (2012) (0)
- Power constrained IP core wrapper design with partitioned clock domains (信号処理) (2007) (0)
- Program-Based Testing of Superscalar Microprocessors (2015) (0)
- A Design Scheme for Delay Testing of Controllers Using State Transition Information (2004) (0)
- An ILP formulation for consecutive testability of system-on-a-chip (2002) (0)
- An extended class of acyclically testable circuits (2007) (0)
- Serial and Parallel TAM Designs for System-on-Chip Interconnects Based on 2-Pattern Testability (2004) (0)
- Efficient path delay test generation based on stuck-at test generation using checker circuitry (2007) (0)
- A random-pattern testable design for programmable logic arrays (1987) (0)
- Performance Analysis of Parallel Test Generation for Combinational Circuits (1996) (0)
- Pretest of ICs : Risks and Benefits (2015) (0)
- Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints (2008) (0)
- A method of DFT for data paths using bit - match function (2004) (0)
- RTL Don't Care Path Identification and Synthesis for Transforming Don't Care Paths into False Paths (2007) (0)
- Design and Optimization of Transparency-Based TAM for SoC Test (2010) (0)
- Needed: Third-generation ATPG Benchmarks (1998) (0)
- An Evaluation for Testability of Functional k-Time Expansion Models (2014) (0)
- Mutual Exclusion Algorithm with Skipping Arbitration Tree (2009) (0)
- Optimal test time for system-on-chip designs using preemptive scheduling and reconfigurable wrappers (2002) (0)
- A DFT Method for BIST of RTL Data Paths Based on Single-Control Testability (2003) (0)
- Diagnosis in Designs with Block Compactors (2015) (0)
- 5 Test Vector Set Reduction Analysis (2002) (0)
- A secure scan design approach using extended de Bruijn graph (ディペンダブルコンピューティング) (2009) (0)
- Electrical analysis of a domino logic cell with GOS faults (2005) (0)
- Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths (2008) (0)
- Effect of BIST Pretest on IC Defect Level (2006) (0)
- Scheduling Power-Constrained Tests through the SoC Functional Bus (2008) (0)
- One More Class of Sequential Circuits having Combinational Test Generation Complexity (2015) (0)
- Design for consecutive transparency method of RTL circuits (2006) (0)
- A Test Generation Method for Acyclic Sequential Circuits with L/H-Type Registers (1998) (0)
- A nonscan DFT method for RTL circuits based on fixed‐control testability (2003) (0)
- New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency (2004) (0)
- Wait-Free Linearizable Implementation of a Distributed Shared Memory (Algorithm Engineering as a New Paradigm) (1999) (0)
- Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents (2017) (0)
- Instruction-Based Self-Test for Sequential Modules in Processors (2015) (0)
- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation (2006) (0)
- A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint (2010) (0)
- A DFT Method for RTL Data Paths Achieving 100 % Fault Efficiency under Hierachical Test Environment (2015) (0)
- Electrical behavior of GOS fault affected domino logic cell (2006) (0)
- Fault Set Partition for Efficient Width Compression 1 (2015) (0)
- Enhanced Functional Fault Model for Micro Operation Faults (2010) (0)
- NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints (2007) (0)
- On the Effect of Scheduling in Test Generation (1996) (0)
- Classification of sequential circuits based on acyclic test generation complexity (2006) (0)
- Bidirectional Delay Test of FPGA Routing Networks (2015) (0)
- 1 Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults (2015) (0)
- Satisfiability Problem Implementation for Redundancy Identification and Test Generation 1 (2015) (0)
- A DFT Method with Embedded Test Plans for RTL Circuits (2002) (0)
- Hierarchical BIST : Test-Per-Clock Scheme BIST with Low Overhead (2003) (0)
- A Test Generation Method for Delay Faults in Sequential Circuits with Discontinuous Reconvergence Structure (2003) (0)
- Special Issue on Verification, Test and Diagnosis of VLSI Systems (1995) (0)
- Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information (2007) (0)
- Fault Dependent/Independent Two-Pattern Test Generation Methods for State Observable FSMs (2006) (0)
- TEST REGISTER INSERTION AT RTL BASED ON REDUCED BIST (2016) (0)
- A three-valued neural network model for test generation in logic circuits (abstract) (1992) (0)
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