Hiroshi Kawaguchi
#178,599
Most Influential Person Now
Hiroshi Kawaguchi's AcademicInfluence.com Rankings
Hiroshi Kawaguchiengineering Degrees
Engineering
#8277
World Rank
#9789
Historical Rank
Electrical Engineering
#2591
World Rank
#2718
Historical Rank
Applied Physics
#2972
World Rank
#3035
Historical Rank
Download Badge
Engineering
Hiroshi Kawaguchi's Degrees
- PhD Electrical Engineering University of Tokyo
- Masters Electrical Engineering University of Tokyo
- Bachelors Electrical Engineering University of Tokyo
Why Is Hiroshi Kawaguchi Influential?
(Suggest an Edit or Addition)Hiroshi Kawaguchi's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- A large-area, flexible pressure sensor matrix with organic field-effect transistors for artificial skin applications. (2004) (1694)
- Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes. (2005) (1263)
- A reduced clock-swing flip-flop (RCSFF) for 63% power reduction (1998) (371)
- Integration of organic FETs with organic photodiodes for a large area, flexible, and lightweight sheet image scanners (2005) (238)
- A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current (2000) (233)
- High mobility of pentacene field-effect transistors with polyimide gate dielectric layers (2004) (160)
- An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment (2007) (158)
- Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era (2003) (137)
- 1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme (2003) (129)
- Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection (2012) (128)
- Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin (2005) (124)
- Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential — (2008) (112)
- Control of threshold voltage of organic field-effect transistors with double-gate structures (2005) (104)
- Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration (2000) (99)
- Low-power high-speed level shifter design for block-level dynamic voltage scaling environment (2005) (95)
- Delay and noise formulas for capacitively coupled distributed RC lines (1998) (93)
- Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs (2007) (73)
- VTH-hopping scheme to reduce subthreshold leakage for low-power processors (2002) (70)
- An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display (2007) (65)
- Low-power CMOS design through VTH control and low-swing circuits (1997) (61)
- A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current (1998) (60)
- A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing (2007) (57)
- Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS) (2006) (54)
- A Wearable Healthcare System With a 13.7 $\mu$ A Noise Tolerant ECG Processor (2015) (49)
- A large-area flexible wireless power transmission sheet using printed plastic MEMS switches and organic field-effect transistors (2006) (41)
- Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications (2006) (40)
- Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches (2007) (39)
- Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video (2010) (37)
- Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector (2015) (35)
- A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme (2009) (33)
- FP 12.4: A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current (1998) (31)
- A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection (2013) (30)
- Cut-and-paste organic FET customized ICs for application to artificial skin (2004) (28)
- Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering (2008) (28)
- Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-V/sub DD/ SRAM's (2003) (28)
- Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems (2012) (27)
- Implementing Virtual Agent as an Interface for Smart Home Voice Control (2012) (27)
- A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix (2005) (26)
- Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs (2006) (26)
- A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment (2006) (26)
- Noise tolerant QRS detection using template matching with short-term autocorrelation (2014) (23)
- V/sub TH/-hopping scheme for 82% power saving in low-voltage processors (2001) (23)
- Quality of a Bit (QoB): A New Concept in Dependable SRAM (2008) (23)
- Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags (2013) (23)
- A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition (2011) (22)
- A Controller LSI for Realizing VDD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System (2002) (20)
- A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection (2009) (20)
- A 40-nm 0.5-V 20.1-µW/MHz 8T SRAM with low-energy disturb mitigation scheme (2011) (20)
- A low memory bandwidth Gaussian mixture model (GMM) processor for 20,000-word real-time speech recognition FPGA system (2008) (19)
- A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops (2012) (19)
- Stacked-chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems (2006) (19)
- . 7 10 . 7 1 . 27 Gb / s / pin 3 mW / pin Wireless Superconnect ( WSC ) Interface Scheme (2003) (18)
- Observation of one-fifth-of-a-clock wake-up time of power-gated circuit (2004) (18)
- Managing Subthreshold Leakage in Charge-Based Analog Circuits With Low- Transistors by Analog T- Switch (AT-Switch) and Super Cut-off (2006) (18)
- A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system (2013) (18)
- Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS) (2001) (17)
- A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI (2014) (17)
- A large-area, flexible, and lightweight sheet image scanner integrated with organic field-effect transistors and organic photodiodes (2004) (17)
- An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks (2009) (16)
- 95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping (2005) (16)
- Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems (2001) (16)
- Impact of aggregation efficiency on GIT routing for wireless sensor networks (2006) (16)
- An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin (2006) (16)
- Wearable pulse wave velocity sensor using flexible piezoelectric film array (2017) (16)
- A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10−19 (2011) (15)
- Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems (2013) (15)
- /spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications (2005) (14)
- An FPGA Implementation of a HOG-based Object Detection Processor (2013) (14)
- Physical activity group classification algorithm using triaxial acceleration and heart rate (2015) (14)
- A Dependable SRAM with 7T/14T Memory Cells (2009) (14)
- $V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time (2006) (14)
- Managing leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T-switch (AT-Switch) and super cut-off CMOS (2005) (14)
- A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition (2012) (14)
- Isochronous MAC using Long-Wave Standard Time Code for Wireless Sensor Networks (2006) (13)
- 7T SRAM enabling low-energy simultaneous block copy (2010) (13)
- A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM (2009) (13)
- A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition (2008) (13)
- Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process (2011) (13)
- NMOS-inside 6T SRAM layout reducing neutron-induced multiple cell upsets (2012) (12)
- Experimental verification of row-by-row variable V/sub DD/ scheme reducing 95% active leakage power of SRAM's (2005) (12)
- A Low-Power Multi Resolution Spectrum Sensing (MRSS) Architecture for a Wireless Sensor Network with Cognitive Radio (2010) (12)
- 6-3 Vth-Hopping Scheme for 82% Power Saving in Low-Voltage Processors (2000) (12)
- A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering (2006) (12)
- Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure (2011) (12)
- Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS) (2005) (11)
- Improvement of Counter-based Broadcasting by Random Assessment Delay Extension for Wireless Sensor Networks (2007) (11)
- A sheet-type scanner based on a 3D stacked organic-transistor circuit with double word-line and double bit-line structure (2005) (11)
- Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder (2002) (11)
- Bit error rate estimation in SRAM considering temperature fluctuation (2012) (11)
- Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis (2016) (11)
- A 3-D-Stack Organic Sheet-Type Scanner with Double-Wordline and Double-Bitline Structure (2006) (11)
- Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks (2006) (10)
- A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems (2014) (10)
- Model-based fault injection for failure effect analysis — Evaluation of dependable SRAM for vehicle control units (2011) (10)
- A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing (2008) (10)
- Estimating metabolic equivalents for activities in daily life using acceleration and heart rate in wearable devices (2018) (10)
- Abnormal leakage suppression (ALS) scheme for low standby current SRAMs (2001) (10)
- An LSI for V/sub DD/-hopping and MPEG4 system based on the chip (2001) (10)
- A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video (2013) (10)
- Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution (2007) (10)
- A Power-Variation Model for Sensor Node and the Impact against Life Time of Wireless Sensor Networks (2006) (10)
- A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier (2013) (9)
- Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring (2018) (9)
- A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability (2014) (9)
- 8-3 Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch ( AT-Switch ) and Super Cut-off CMOS (2005) (8)
- A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC (2011) (8)
- Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system (2009) (8)
- 6.3 A 0.5V, 400MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology (2003) (8)
- Neutron-induced soft error rate estimation for SRAM using PHITS (2012) (8)
- A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition (2011) (8)
- Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor (2019) (8)
- A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition (2012) (8)
- Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare (2017) (8)
- Optimum Device Parameters and Scalability of Variable Threshold CMOS (VTCMOS) (2000) (8)
- Non-contact biometric identification and authentication using microwave Doppler sensor (2017) (7)
- Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network (2011) (7)
- VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition (2011) (7)
- 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM (2010) (7)
- Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping (2006) (7)
- Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes (2007) (7)
- Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things (2019) (7)
- A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor (2015) (7)
- Scalable parallel processing for H.264 encoding application to multi/many-core processor (2010) (6)
- Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application (2017) (6)
- Development of the High-Power, Low-Emission Engine for the “Honda S2000” (2000) (6)
- A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction (2012) (6)
- A negative-resistance sense amplifier for low-voltage operating STT-MRAM (2015) (6)
- A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping (2012) (6)
- A 38 μA wearable biosignal monitoring system with near field communication (2013) (5)
- A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond (2006) (5)
- Intelligent ubiquitous sensor network for sound acquisition (2010) (5)
- A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller (2014) (5)
- A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing (2006) (5)
- Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock (2008) (5)
- An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology (2016) (5)
- FPGA implementation of mixed integer quadratic programming solver for mobile robot control (2009) (5)
- FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature (2017) (5)
- A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology (2003) (5)
- A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator (2012) (5)
- An inter-die variability compensation scheme for 0.42-V 486-kb FD-SOI SRAM using substrate control (2008) (5)
- Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode (2016) (4)
- Trends of On-Chip Interconnects in Deep Sub-Micron VLSI (2006) (4)
- An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication (2006) (4)
- A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations (2020) (4)
- A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition (2013) (4)
- A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer (2008) (4)
- A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing (2006) (4)
- Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks (2008) (4)
- More than two orders of magnitude leakage current reduction in look-up table for FPGAs (2005) (4)
- Use of laser drilling in the manufacture of organic inverter circuits (2005) (4)
- 256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V (2011) (4)
- A 58-µW single-chip sensor node processor using synchronous MAC protocol (2009) (4)
- Experimental Evaluation of Cooperative Voltage Scaling ( CVS ) : A Case Study (2001) (4)
- A ferroelectric-based non-volatile flip-flop for wearable healthcare systems (2015) (4)
- Failure Modes and Effects Analysis Using Virtual Prototyping System with Microcontroller Model for Automotive Control System (2013) (4)
- Swallowable sensing device for long-term gastrointestinal tract monitoring (2016) (4)
- A 34.7-mW quad-core MIQP solver processor for robot control (2010) (4)
- An accurate soft error propagation analysis technique considering temporal masking disablement (2015) (4)
- Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery (2015) (3)
- A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio (2011) (3)
- An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing (2020) (3)
- Normally-off technologies for healthcare appliance (2014) (3)
- Radiation-Induced Soft Errors (2018) (3)
- A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing (2016) (3)
- A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning (2017) (3)
- Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition (2019) (3)
- A swallowable sensing device platform with wireless power feeding and chemical reaction actuator (2017) (3)
- Low-Traffic and Low-Power Data-Intensive Sound Acquisition with Perfect Aggregation Specialized for Microphone Array Networks (2010) (3)
- A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline (2006) (3)
- A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding (2008) (3)
- Pocket scanner using organic transistors and detectors (2005) (3)
- Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis (2018) (3)
- A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output (2011) (3)
- Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems (2015) (3)
- A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells (2013) (3)
- A 6T-4C shadow memory using plate line and word line boosting (2014) (3)
- Live demonstration: Intelligent ubiquitous sensor network for sound acquisition (2010) (3)
- Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices (2015) (3)
- A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops (2013) (3)
- Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture (2007) (3)
- Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks (2007) (3)
- 12.5-m Distance Measurement in High-Interference Environment Using Ultrasonic Array Sensors (2021) (2)
- Batteryless sensorless bicycle speed recorder with hub dynamo and STT-MRAM (2015) (2)
- An 800-μW H.264 Baseline-Profile Motion Estimation Processor Core (2006) (2)
- Doppler shift compensation technique for ultrasonic DSSS ranging system (2020) (2)
- Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors (2020) (2)
- 0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM (2011) (2)
- Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling. (2016) (2)
- Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout (2013) (2)
- Hop count aware broadcast algorithm with Random Assessment Delay extension for wireless sensor networks (2008) (2)
- A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme (2019) (2)
- A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM (2014) (2)
- A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing (2008) (2)
- Subcentimeter Precision Ranging System for Moving Targets With a Doppler-Effect- Compensated Ultrasonic Direct Sequence Spread Spectrum (2021) (2)
- Design for Mixed Circuits of Organic FETs and Plastic MEMS Switches for Wireless Power Transmission Sheet (2007) (2)
- Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy (2011) (2)
- Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process (2012) (2)
- A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems (2015) (2)
- Effectiveness of the heartbeat interval error and compensation method on heart rate variability analysis (2022) (2)
- A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme (2012) (2)
- Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system (2013) (2)
- A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme (2012) (2)
- A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection (2020) (2)
- Frequency–voltage cooperative CPU power control: A design rule and its application by feedback prediction (2005) (2)
- STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier (2014) (2)
- A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure (2013) (2)
- A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique (2012) (2)
- Handsfree Voice Interface for Home Network Service Using a Microphone Array Network (2012) (2)
- Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare (2018) (2)
- A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells (2012) (2)
- A 75-variable MIQP solver processor for real-time autonomous robot control (2011) (2)
- A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit (2019) (2)
- Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's (2006) (2)
- A Low-Power Portable H.264/AVC Decoder Using Elastic Pipeline (2009) (1)
- Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential (2011) (1)
- Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme (2007) (1)
- A metabolic equivalents estimation algorithm using triaxial accelerometer and adaptive sampling for wearable devices (2017) (1)
- Time-Dependent Degradation in Device Characteristics and Countermeasures by Design (2018) (1)
- A 19-μA metabolic equivalents monitoring SoC using adaptive sampling (2017) (1)
- Multiple-cell-upset hardened 6T SRAM using NMOS-centered layout (2013) (1)
- PAPER Special Section on VLSI Design and CAD Algorithms A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond (2006) (1)
- A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm (2015) (1)
- A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme (2015) (1)
- Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling (2016) (1)
- An soft error propagation analysis considering logical masking effect on re-convergent path (2016) (1)
- Virtualization: System-Level Fault Simulation of SRAM Errors in Automotive Electronic Control Systems (2018) (1)
- Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control (2011) (1)
- A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers (2011) (1)
- Positioning system for mobile terminals using a microphone array network as an intuitive interface (2011) (1)
- A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video (2017) (1)
- Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM (2013) (1)
- Integration of organic transistors and organic photodiodes : Applications to sheet image scanners (2005) (1)
- Introducing Multiple Microphone Arrays for Enhancing Smart Home Voice Control (応用音響) (2013) (1)
- Temperature compensation using least mean squares for fast settling all-digital phase-locked loop (2013) (1)
- A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM (2016) (1)
- A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI (2014) (1)
- Millimeter-Precision Ultrasonic DSSS Positioning Technique With Geometric Triangle Constraint (2022) (1)
- A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques (2015) (1)
- Parallel-processing VLSI architecture for mixed integer linear programming (2010) (1)
- An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment (2019) (1)
- 20-µs Accuracy Time-Synchronization Method using Bluetooth Low Energy for Internet-of-Things Sensors (2022) (1)
- 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory (2011) (1)
- A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement (2014) (1)
- Data-Intensive Sound Acquisition System with Large-scale Microphone Array (2011) (1)
- DELAYED WEIGHT UPDATE FOR FASTER CONVERGENCE IN DATA-PARALLEL DEEP LEARNING (2018) (1)
- A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI (2013) (1)
- Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning (2018) (1)
- 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme (2012) (1)
- An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter (2014) (1)
- Recent advances in applications of organic integrated circuits for large-area electronics (2005) (1)
- A design methodology of chip-to-chip wireless power transmission system (2007) (1)
- A VGA 30-fps optical-flow processor core based on Pyramidal Lucas and Kanade algorithm (2007) (1)
- Organic field-effect transistors with bending radius down to 1 mm (2004) (1)
- A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate (2018) (1)
- A 168-mW 2 . 4 ×-Real-Time 60-kWord Continuous Speech Recognition Processor (2013) (0)
- Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation (2016) (0)
- IsochronousMAC usingLong-Wave Standard Time Code forWirelessSensorNetworks (2006) (0)
- An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding (2008) (0)
- Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores (2012) (0)
- Design forMixed Circuits of OrganicFETs andPlastic MEMS Switches for WirelessPower TransmissionSheet (2007) (0)
- Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines (2007) (0)
- Recent progress of organic transistor integrated circuits for large-area sensor applications (2005) (0)
- A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique (2013) (0)
- A Physical Unclonable Function Chip Exploiting Variation in SRAM Bitcells (2012) (0)
- Low Leakage-power FPGA Design using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-hopping (2006) (0)
- Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell (2014) (0)
- A novel test scheme for detecting faulty recall margin cells for 6T-4C FeRAM (2017) (0)
- Foreword: Special section on VLSI design and CAD algorithms (2014) (0)
- A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design (2010) (0)
- Coupling-driven bus design-power application-specific systems (2002) (0)
- A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor (2016) (0)
- Low-Power SRAM in 28-nm FD-SOI for Image Processor (2014) (0)
- A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's (2007) (0)
- A 58-W Sensor Node LSI with Synchronous MAC Protocol (2006) (0)
- A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme (2012) (0)
- Session VII: Low-power designs (2011) (0)
- LowPowerandFlexible Braille Sheet Display withOrganic FET'sandPlastic Actuators (2006) (0)
- Low-power control techniques for silicon and organic circuits with array structures (2009) (0)
- Sheet Image Scanner with Organic Transistor Integrated Circuits (2005) (0)
- Organic inverter circuits with via holes formed by CO 2 laser drill machine (2004) (0)
- 3D Reconstruction from Outdoor Ultrasonic Image Using Variation Autoencoder (2022) (0)
- Thermal Stimulation Device Using Matrix Drive Circuitry (2022) (0)
- Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code (2007) (0)
- Design of SRAM Resilient Against Dynamic Voltage Variations (2018) (0)
- An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation (2004) (0)
- A variation-aware 0.57-V set-associative cache with mixed associativity using 7T/14T SRAM (2012) (0)
- PAPER Special Section on Analog Circuits and Related SoC Integration Technologies A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks (2009) (0)
- Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path (2016) (0)
- A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors (2019) (0)
- An 80-1 WH 264 Baseline-ProfileMotionEstimation Processor Core (2006) (0)
- Model-Based Fault Injection for Large-Scale Failure Effect Analysis with 600-Node Cloud Computers (2013) (0)
- A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks (2009) (0)
- Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth (2018) (0)
- Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes (2012) (0)
- A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668] (2018) (0)
- A counter-based read circuit tolerant to process variation for low-voltage operating STT-MRAM (2015) (0)
- SRAM Failure Injection to a Vehicle ECU and Its Behavior Evaluation (2013) (0)
- A 284-µW 1.85-GHz 20-phase oscillator using transfer gate phase couplers (2010) (0)
- A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI (2014) (0)
- Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy (2012) (0)
- Wearable Perspiration Volume Sensor Using Dual-Frequency Impedance Measurement (2022) (0)
- GPQ: Greedy Partial Quantization of Convolutional Neural Networks Inspired by Submodular Optimization (2020) (0)
- WSC) Interface Scheme (2003) (0)
- Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction (2005) (0)
- Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques (2005) (0)
- PAPER Special Section on Circuits and Design Techniques for Advanced Large Scale Integration VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition ∗ (2011) (0)
- Estimating metabolic equivalents for activities in daily life using acceleration and heart rate in wearable devices (2018) (0)
- A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture (2006) (0)
- Machine Learning-Based Severity Classification of Spinal Cord Injury Patients Using Straight Leg Raising Test (2022) (0)
- ED2000-124 / SDM2000-106 / ICD2000-60 Boosted Gate MOS(BGMOS):Leakage-Free Circuits by Device/Circuit Cooperation Scheme (2000) (0)
- A 60-dB image rejection filter using Δ-Σ modulation and frequency shifting (2009) (0)
- Impact of divided static random access memory considering data aggregation for wireless sensor networks (2008) (0)
- 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning (2018) (0)
- A Study on Low-Power Circuit Design for Silicon VLSI's and Organic IC's in Ubiquitous Electronics Environment (2006) (0)
- ffi ciency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks (2006) (0)
- Low-power CMOS design through V/sub TH/ control and low-swing circuits (1997) (0)
- A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation (2014) (0)
- Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path (2015) (0)
- Swallowable sensing device for long-term gastrointestinal tract monitoring. (2016) (0)
- Model-Based Fault Injection for Failure Effect Analysis (2011) (0)
- Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators (2015) (0)
- Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks (2007) (0)
- PAPER Special Section on Emerging Technologies for Practical Ubiquitous and Sensor Networks Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks ∗ (2008) (0)
- An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter (2015) (0)
- Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology (2014) (0)
- A flexible baseband processor with multi-resolution spectrum-sensing functionality (2008) (0)
- Non-contact Atrial Fibrillation Detection using a 24-GHz Microwave Doppler Radar (2022) (0)
- A designmethodology of chip-to-chip wirelesspower transmission system (2007) (0)
- An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter (2013) (0)
- A sheet image scanner based on 3 D organic transistor integrated circuits (2005) (0)
- AN ULTRA-LOW-POWERVAD HARDWAREIMPLEMENTATION FOR INTELLIGENT UBIQUITOUS SENSORNETWORKS (2009) (0)
- Architecture of GMM Processing and Viterbi Decoder for 60 , 000-Word Real-Time Continuous Speech Recognition ∗ (2011) (0)
This paper list is powered by the following services:
What Schools Are Affiliated With Hiroshi Kawaguchi?
Hiroshi Kawaguchi is affiliated with the following schools:
