Hisayo Momose | Academic Influence

Hisayo Momose's AcademicInfluence.com Rankings

Hisayo Momose

Computer Science

#12721

World Rank

#13624

Historical Rank

Machine Learning

#5870

World Rank

#5958

Historical Rank

Artificial Intelligence

#6328

World Rank

#6436

Historical Rank

Database

#9827

World Rank

#10412

Historical Rank

computer-science Degrees

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Computer Science

Hisayo Momose's Degrees

PhD Computer Science University of Tokyo
Masters Computer Science Kyoto University
Bachelors Computer Science Kyoto University

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Why Is Hisayo Momose Influential?

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According to Wikipedia, Hisayo Sasaki Momose is a Japanese electrical engineer specializing in semiconductor devices, including MOSFETs and CMOS image sensors. She is a researcher at the Toshiba Center for Semiconductor Research and Development in Kawasaki.

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Hisayo Momose's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Future perspective and scaling down roadmap for RF CMOS (1999) (105)
Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide (1998) (98)
High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs (1996) (89)
Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs (1994) (80)
An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs (2000) (71)
Control of charge dynamics through a charge-separation interface for all-solid perovskite-sensitized solar cells. (2014) (65)
Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration (1994) (57)
Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films (1990) (52)
Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate (2002) (49)
1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate (2003) (46)
Ultra-thin gate oxides-performance and reliability (1998) (45)
Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS (2001) (45)
0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation (1998) (44)
Huge suppression of charge recombination in P3HT-ZnO organic-inorganic hybrid solar cells by locating dyes at the ZnO/P3HT interfaces. (2013) (33)
Very lightly nitrided oxide gate MOSFETs for deep-sub-micron CMOS devices (1991) (31)
A NiSi salicide technology for advanced logic devices (1991) (28)
Relationship between mobility and residual-mechanical-stress as measured by Raman spectroscopy for nitrided-oxide-gate MOSFETs (1990) (28)
Future perspective and scaling down roadmap for RF CMOS (1999) (27)
High performance RF characteristics of raised gate/source/drain CMOS with Co salicide (1998) (27)
Nitrogen-doped nickel monosilicide technique for deep submicron CMOS salicide (1995) (27)
Prospects for low-power, high-speed MPUs using 1.5 nm direct-tunneling gate oxide MOSFETs (1997) (27)
A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime (1997) (26)
0.18 /spl mu/m low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique (1997) (25)
Thermal stability of CoSi/sub 2/ film for CMOS salicide (2000) (25)
Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating (1998) (25)
Improvement of high resistivity substrate for future mixed analog-digital applications (2002) (24)
Fabrication of sub‐50‐nm gate length n‐metal–oxide–semiconductor field effect transistors and their electrical characteristics (1995) (24)
Hot carrier related phenomena for n- and p-MOSFETs with nitrided gate oxide by RTP (1989) (23)
A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime (1998) (23)
High efficiency 2 GHz power Si-MOSFET design under low supply voltage down to 1 V (1996) (22)
The future of ultra-small-geometry MOSFETs beyond 0.1 micron (1995) (21)
RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip (1998) (20)
110 GHz cutoff frequency of ultra-thin gate oxide p-MOSFETs on [110] surface-oriented Si substrate (2002) (20)
P-MOSFET's with ultra-shallow solid-phase-diffused drain structure produced by diffusion from BSG gate-sidewall (1993) (19)
An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics (1992) (19)
Analysis of the temperature dependence of hot-carrier-induced degradation in bipolar transistors for Bi-CMOS (1994) (19)
0.2 /spl mu/m analog CMOS with very low noise figure at 2 GHz operation (1996) (18)
0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology (1998) (18)
The impact of oxynitride process, deuterium annealing and STI stress to1/f noise of 0.11 /spl mu/m CMOS (2003) (17)
Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs (1995) (17)
Unified Transient and Frequency Domain Noise Simulation for Random Telegraph Noise and Flicker Noise Using a Physics-Based Model (2014) (16)
Improvement of 1/f noise by using VHP (vertical high pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS (1999) (15)
Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures (1989) (14)
A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides (2001) (14)
High performance 0.15 /spl mu/m single gate Co salicide CMOS (1996) (14)
RF noise simulation for submicron MOSFET's based on hydrodynamic model (1999) (13)
High performance MIM capacitor for RF BiCMOS/CMOS LSIs (1999) (12)
On-chip spiral inductors with diffused shields using channel-stop implant (1998) (11)
Lower submicron FCBiMOS (fully complementary BiMOS) process with RTP and MeV implanted 5 GHz vertical PNP transistor (1990) (11)
The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVD (1995) (11)
Analysis of an ONO gate film effect on n- and p-MOSFET mobilities (1990) (11)
Thermal Stability of CoSi Film for CMOS Salicide (2000) (10)
Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V (1995) (9)
Anomalous current gain degradation in bipolar transistors (1991) (9)
A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration (1995) (9)
An improvement of hot-carrier reliability in the stacked nitride-oxide gate n- and p-MISFET's (1995) (9)
Technology towards low power/low voltage and scaling of MOSFETs (1997) (9)
Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide (2001) (8)
An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs (1999) (8)
Si-MOSFET scaling down to deep-sub-0.1-micron range and future of silicon LSI (1995) (8)
Supply voltage design tradeoffs between speed and NMOSFET reliability of half-micrometer BiCMOS gates (1991) (8)
Ultra-thin chip with permalloy film for high performance MS/RF CMOS (2004) (7)
Gate Oxide Thickness Dependence of Hot Carrier Induced Degradation on PMOSFETs (1989) (7)
A high frequency 0.35 /spl mu/m gate length power silicon NMOSFET operating with breakdown voltage of 13 V (1995) (7)
New charge pumping method for direct measurement of spatial distribution of fixed charge (1991) (7)
Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET (2009) (6)
Power Si-MOSFET operating with high efficiency under low supply voltage (2000) (6)
Stacked-nitride oxide gate MISFET with high hot-carrier-immunity (1990) (6)
Poly Si-Si interfacial oxide ball-up mechanism and its control for 0.8 mu m BiCMOS VLSIs (1989) (5)
Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer (2001) (5)
Ultra Thin Nitride Gate MISFET Operating with Tunneling Gate Current (1990) (5)
Comprehensive Understanding of Random Telegraph Noise with Physics Based Simulation (2011) (5)
HfSiON gate dielectrics design for mixed signal CMOS (2005) (5)
Hot-Carrier Reliability of S4D n-MOSFETs (1996) (5)
Limits on Gate Insulator Thickness for MISFET Operation in Pure-Oxide and Nitrided-Oxide Gate Cases (2015) (4)
Application of direct-tunneling gate oxides to high-performance CMOS (1998) (4)
RF Noise Study of Small Gate Width Si-MOSFETs up to 8GHz Application for Low Power Consumption (1998) (4)
0.15-/spl mu/m buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer (1998) (4)
Mechanical Stress Induced Threshold Voltage Shifts for Nitrided Oxide Gate n- and p- MOSFETs (1990) (4)
Degradation Mechanism of Lightly Doped Drain (LDD) n‐Channel MOSFET's Studied by Ultraviolet Light Irradiation (1985) (3)
Prevention of boron penetration from p+ poly gate by RTN produced thin gate oxide (1990) (3)
A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation (1999) (3)
Study of direct-tunneling gate oxides for CMOS applications (1998) (3)
Influence of high substrate doping concentration on the hot-carrier and other characteristics of small-geometry CMOS transistors down to the 0.1 /spl mu/m generation (1994) (3)
Si channel surface dependence of electrical characteristics in ultra-thin gate oxide CMOS (2003) (3)
90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate (2009) (3)
Effects of Si channel orientation on MOSFET characteristics (2008) (2)
Comprehensive understanding of random telegraph noise with (2011) (2)
Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel (2007) (2)
Single-gate 0.15 and 0.12 μm CMOS with Co salicide technology (1999) (2)
CMOS/BiCMOS Technology (2000) (1)
Change of Editor-in-Chief (2019) (1)
2.2um BSI CMOS image sensor with two layer photo-detector (2015) (1)
Layout dependence of RF CMOS performance on ultra-thin Si substrate (2004) (1)
Process induced damage on RFCMOS (1998) (1)
Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application (2008) (1)
Comparison of hot-carrier degradation in n- and p-MOSFETs with various nitride-oxide gate films (1990) (1)
Hot-carrier reliability of ultra-thin gate oxide CMOS (2000) (1)
2 . 2 um BSI CMOS image sensor with two layer photodetector (2015) (0)
New short-channel effects on nitrided oxide gate MOSFETs (1990) (0)
Guard-ring design for high-performance RF CMOS (2002) (0)
Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel (2008) (0)
Advanced rf CMOS technology (1999) (0)
Realization of high‐performance MOSFETs with gate lengths of 0.1 μm or less (1996) (0)
A Band-to-Band Tunneling MOSFET Using a Thin Film Transistor (1990) (0)
A high performance 0.15 μm buried channel pMOSFET with extremely shallow counter doped channel region using solid phase diffusion (1999) (0)
Process dependence of 1/f noise : For realization of high performance analog circuits (2003) (0)
High performance of silicided silicon-sidewall source and drain (S/sup 4/D) structure (1998) (0)
A study of self-align doped channel structure for low power and low l/f noise operation (1998) (0)
All manuscripts, correspondence and communication should be directed to IEEE/EDS Publications Office (2010) (0)
A High Performance 0.15μm Single Gate CMOS Technology (1995) (0)
New model of Dark fixed pattern noise generation in CMOS imager pixel with negative transfer-gate bias operation (2013) (0)
RF modelling for 0.1um gate length MOSFETs (1999) (0)
Tunneling gate oxide MOSFET technology (1997) (0)
A hot-carrier degradation mechanism and electrical characteristics in S/sup 4/D n-MOSFET's (1997) (0)
EX-OFFICIO MEMBERS (Only includes Standing Committee Vice-Presidents, Technical Committee Chairs and Publication Editors-in-Chief, unless already listed above) (2009) (0)
Gate Oxide Thickness Dependence of Intrinsic Gain and Flicker Noise in InGaZnO Thin Film Transistors (2013) (0)
Standing Committee Vice-Presidents Technical Committee Chairs Publication Editors-in-Chief (2015) (0)
Study on the Realization of High Performance MOSFETs with Gate lenths 0.1μm and Below (1996) (0)
Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique (1999) (0)
ULSI PROCESS INTEGRATION II ULSI PROCESS INTEGRATION II Proceedings ofthe International Symposium Editors (2019) (0)
Direct measurement and analysis of highly injected intrinsic base potential (1991) (0)
Analysis of 1/f noise for CMOS with high-k gate dielectrics (2006) (0)
TEMPERATURE IN A WIDE RANGE USING A TUNNEL JUNCTION (2017) (0)

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