H. J. De Man
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Computer Science
H. J. De Man's Degrees
- PhD Computer Science Delft University of Technology
- Masters Computer Science Delft University of Technology
- Bachelors Computer Science Delft University of Technology
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(Suggest an Edit or Addition)H. J. De Man's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix (2003) (575)
- NORA: a racefree dynamic CMOS technique for pipelined logic structures (1983) (304)
- Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling (2003) (234)
- DRESC: a retargetable compiler for coarse-grained reconfigurable architectures (2002) (225)
- Compensation of IQ imbalance and phase noise in OFDM systems (2005) (217)
- A combined OFDM/SDMA approach (2000) (208)
- Cathedral-II: A Silicon Compiler for Digital Signal Processing (1986) (206)
- CoWare—A design environment for heterogeneous hardware/software systems (1996) (189)
- Loop Optimization in Register-Transfer Scheduling for DSP-Systems (1989) (154)
- Instruction set definition and instruction selection for ASIPs (1994) (147)
- Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms (1990) (138)
- Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings (1998) (134)
- Optimized synthesis of asynchronous control circuits from graph-theoretic specifications (1990) (132)
- Cathedral-III : architecture-driven high-level synthesis for high throughput DSP applications (1991) (125)
- Hardware/software co-design of digital telecommunication systems (1997) (122)
- Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications (1997) (118)
- DSP specification using the Silage language (1990) (110)
- Power exploration for data dominated video applications (1996) (108)
- Global Communication and Memory Optimizing Transformations for Low Power Systems (1994) (103)
- Joint compensation of IQ imbalance and frequency offset in OFDM systems (2003) (102)
- High-level synthesis for real-time digital signal processing (1993) (88)
- Static Timing Analysis of Dynamically Sensitizable Paths (1989) (88)
- Background memory area estimation for multidimensional signal processing systems (1995) (88)
- Operating system based software generation for systems-on-chip (2000) (85)
- An efficient microcode compiler for application specific DSP processors (1990) (85)
- Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications (1996) (84)
- A generalized state assignment theory for transformations on signal transition graphs (1992) (83)
- High-level address optimization and synthesis techniques for data-transfer-intensive applications (1998) (83)
- Timing verification using statically sensitizable paths (1990) (82)
- Minimizing the required memory bandwidth in VLSI system realizations (1999) (80)
- Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system (1986) (79)
- Combined hardware selection and pipelining in high performance data-path design (1990) (71)
- Data routing: a paradigm for efficient data-path synthesis and code generation (1994) (65)
- Array placement for storage size reduction in embedded multimedia systems (1997) (62)
- Formalized methodology for data reuse exploration in hierarchical memory mappings (1997) (62)
- Adaptive loading for OFDM/SDMA-based wireless networks (2002) (60)
- Space-time block coding for single-carrier block transmission DS-CDMA downlink (2003) (59)
- Transforming set data types to power optimal data structures (1995) (58)
- System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach (1998) (57)
- Dataflow-driven Memory Allocation For Multi-dimensional Signal Processing Systems (1994) (56)
- 80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band (2001) (55)
- Flow graph balancing for minimizing the required memory bandwidth (1996) (55)
- Low-power driven technology mapping under timing constraints (1993) (53)
- Constrained least squares detector for OFDM/SDMA-based wireless networks (2001) (52)
- Compensation of transmitter IQ imbalance for OFDM systems (2004) (49)
- Evolution of substrate noise generation mechanisms with CMOS technology scaling (2006) (48)
- A specification invariant technique for operation cost minimisation in flow-graphs (1994) (46)
- Code transformations for low power caching in embedded multimedia processors (1998) (46)
- Time, frequency, and z-domain modified nodal analysis of switched-capacitor networks (1981) (45)
- Simulated‐annealing‐based optimization of coefficient and data word‐lengths in digital filters (1988) (44)
- Application-specific architectural methodologies for high-throughput digital signal and image processing (1990) (42)
- Modeling multidimensional data and control flow (1993) (42)
- Assassin: a synthesis system for asynchronous control circuits (1994) (42)
- Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment (1991) (40)
- Strategy for power-efficient design of parallel systems (1999) (40)
- Digital ground bounce reduction by supply current shaping and clock frequency Modulation (2005) (40)
- A single-carrier frequency-domain SDMA basestation (2000) (39)
- Co-Design of DSP Systems (1996) (39)
- Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor (1999) (39)
- A graph based processor model for retargetable code generation (1996) (39)
- Background Memory Synthesis for Algebraic Algorithms on Multi-Processor DSP Chips (1989) (38)
- A robust joint linear precoder and decoder MMSE design for slowly time-varying MIMO channels (2004) (38)
- SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parameters (1988) (38)
- Cache conscious data layout organization for embedded multimedia applications (2001) (38)
- Compiling multi-dimensional data streams into distributed DSP ASIC memory (1991) (38)
- The adjoint switched capacitor network and its application to frequency, noise and sensitivity analysis (1981) (38)
- Architectural strategies for an application-specific synchronous multiprocessor environment (1988) (37)
- Computer design aids for VLSI circuits (1981) (37)
- PeopleMover: an example of interdisciplinary project-based education in electrical engineering (2003) (37)
- In-place memory management of algebraic algorithms on application specific ICs (1991) (36)
- An analytic Volterra-series-based model for a MEMS variable capacitor (2003) (35)
- An efficient VLSI architecture for 2-D wavelet image coding with novel image scan (1999) (34)
- Loop transformation methodology for fixed-rate video, image and telecom processing applications (1994) (33)
- Ambient intelligence: gigascale dreams and nanoscale realities (2005) (32)
- Just in time scheduling (1992) (32)
- DIALOG: An Expert Debugging System for MOSVLSI Design (1985) (31)
- Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems (1998) (31)
- System-level transformations for low power data transfer and storage (1998) (31)
- Time constrained allocation and assignment techniques for high throughput signal processing (1992) (30)
- Open-ended system for high-level synthesis of flexible signal processors (1990) (30)
- System-Level Memory Management for Weakly Parallel Image Processing (1996) (30)
- Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer (1998) (30)
- Definition and assignment of complex data-paths suited for high throughput applications (1989) (29)
- OFDM versus Single Carrier: A Realistic Multi-Antenna Comparison (2004) (29)
- A data path layout assembler for high performance DSP circuits (1990) (29)
- System level memory optimization for hardware-software co-design (1997) (29)
- Cache conscious data layout organization for conflict miss reduction in embedded multimedia applications (2005) (29)
- Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators (1993) (28)
- Joint compensation of IQ imbalance, frequency offset and phase noise in OFDM receivers (2004) (28)
- An efficient ASIC architecture for real-time edge detection (1989) (28)
- Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling (1983) (28)
- Cathedral II: A Synthesis and Module Generation System for Multiprocessor Systems on a Chip (1987) (27)
- Advanced Data Layout Optimization for Multimedia Applications (2000) (27)
- Memory organization for video algorithms on programmable signal processors (1995) (26)
- A proof of the nonrestoring division algorithm and its implementation on an ALU (1994) (26)
- Integration of signal processing systems on heterogeneous IC architectures (1992) (26)
- Quadratic zero-one programming based synthesis of application specific data paths (1993) (25)
- Power exploration for dynamic data types through virtual memory management refinement (1998) (25)
- Synthesis of ASIC regular arrays for real-time image processing systems (1991) (25)
- Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management (1998) (25)
- Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (2002) (25)
- Interprocessor communication in synchronous multiprocessor digital signal processing chips (1989) (24)
- Testability analysis in high level data path synthesis (1993) (24)
- Real-time multi-tasking in software synthesis for information processing systems (1995) (24)
- Efficient CAD tools for the coefficient optimisation of arbitrary integrated digital filters (1984) (24)
- SWAN: high-level simulation methodology for digital substrate noise generation (2006) (24)
- Cellular automata based deterministic self-test strategies for programmable data paths (1994) (24)
- System-on-Chip Design: Impact on Education and Research (1999) (23)
- Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment (1990) (23)
- Exact evaluation of memory size for multi-dimensional signal processing systems (1993) (23)
- Extensions to linear mapping for regular arrays with complex processing elements (1990) (23)
- Task concurrency management experiment for power-efficient speed-up of embedded MPEG4 IM1 player (2000) (22)
- Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding (2006) (22)
- ADOPT: efficient hardware address generation in distributed memory architectures (1996) (22)
- Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm (1999) (22)
- A unified scheduling model for high-level synthesis and code generation (1995) (22)
- A specification invariant technique for regularity improvement between flow-graph clusters (1996) (22)
- Embedded architecture co-synthesis and system integration (1996) (21)
- Partial scan at the register-transfer level (1993) (21)
- Transformation of Nested Loops with Modulo Indexing to Affine Recurrences (1994) (21)
- Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects (2002) (20)
- System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs (1998) (20)
- Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures (1995) (20)
- Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II (1991) (20)
- Evolution of CAD tools towards third generation custom VLSI design (1987) (20)
- An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory (1991) (19)
- Hardware Cache Optimization for Parallel Multimedia Applications (1998) (18)
- Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing (1997) (18)
- A preprocessing step for global loop transformations for data transfer optimization (2000) (18)
- Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures (1995) (18)
- Security Considerations in the Design and Implementation of a new DES chip (1987) (18)
- Semi-blind space-time chip equalizer receivers for WCDMA forward link with code-multiplexed pilot (2001) (18)
- CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler (1990) (17)
- A generalized signal transition graph model for specification of complex interfaces (1994) (17)
- System-level data-flow transformations for power reduction in image and video processing (1996) (17)
- A testability strategy for microprocessor architecture (1989) (17)
- A strategy for real-time kernel support in application-specific HW/SW embedded architectures (1996) (17)
- An Intelligent Module Generator Environment (1986) (17)
- An efficient microcode compiler for custom multiprocessor DSP-systems (1987) (16)
- Deriving ASIC architectures for the Hough transform (1990) (16)
- Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers (1987) (16)
- Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications (2002) (16)
- High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (2004) (16)
- Digital ground bounce reduction by phase modulation of the clock (2004) (16)
- A hardware virtual machine for networked reconfiguration (2000) (15)
- Control flow optimization for fast system simulation and storage minimization /spl lsqb/real-time multidimensional signal processing/spl rsqb/ (1994) (15)
- Architectural exploration and optimization for counter based hardware address generation (1997) (15)
- Global interconnect trade-off for technology over memory modules to application level: case study (2003) (15)
- Sizing and verification of communication buffers for communicating processes (1993) (15)
- Cellular automata based self-test for programmable data paths (1990) (15)
- DIGEST: a digital filter evaluation and simulation tool for MOS VLSI filter implementations (1984) (14)
- Design of a C-testable booth multiplier using a realistic fault model (1994) (14)
- High-level simulation of substrate noise generation from large digital circuits with multiple supplies (2001) (14)
- Control flow optimization for fast system simulation and storage minimization [real-time multidimens (1994) (14)
- An optimal and flexible delay management technique for VLSI (1986) (14)
- Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata (1992) (13)
- DMT-based power line communication for the CENELEC A-band (1999) (13)
- DIANA as a mixed-mode simulation for MOSLSI sampled-data circuits (1980) (13)
- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform (2000) (13)
- Efficient and accurate multiparameter analysis of linear digital filters using a multivariable feedback representation (1984) (13)
- Acceleration of relaxation-based circuit simulation using a multiprocessor system (1990) (13)
- Exploration and synthesis of dynamic data sets in telecom network applications (1999) (13)
- Multicarrier Block-Spread CDMA for Broadband Cellular Downlink (2004) (13)
- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware (2001) (13)
- Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications (2000) (13)
- Timed executable system specification of an ADSL modem using a C++ based design environment: A case study (1999) (13)
- Clustering techniques for register optimization during scheduling preprocessing (1991) (13)
- Virtual Java/FPGA interface for networked reconfiguration (2001) (13)
- Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures (2001) (13)
- Education for the deep submicron age: business as usual? (1997) (12)
- An Efficient Microcode-Compiler for Custom DSP-Processors (2003) (12)
- Assessment of the cathedral-ii silicon compiler for digital-signal-processing applications (1991) (12)
- Multi-thread graph: a system model for real-time embedded software synthesis (1997) (12)
- Design technology research for the nineties: more of the same? (1992) (12)
- Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs] (2004) (12)
- On the impact of multi-antenna RF transceivers' amplitude and phase mismatches on transmit MRC (2005) (12)
- A general and efficient noise analysis technique for switched capacitor filters (1983) (12)
- Mixed-Mode Circuit Simulation Techniques and their Implementation in DIANA (1984) (12)
- System level verification of video and image processing specifications (1995) (11)
- Scheduling with register constraints for DSP architectures (1994) (11)
- A true silicon compiler for the design of complex ics for digital signal-processing (1989) (11)
- Reed-solomon codes implementing a coded single-carrier with cyclic prefix scheme (2009) (11)
- Synthesis of High Throughput DSP ASICs Using Application Specific Datapaths (1994) (11)
- Very efficient computer algorithms for direct frequency, aliasing and sensitivity analysis of switched capacitor networks (1981) (11)
- A METHODOLOGY FOR PROVING CORRECTNESS OF PARAMETERIZED HARDWARE MODULES IN HOL (1991) (11)
- A loop transformation approach for combined parallelization and data transfer and storage optimization (2000) (11)
- On the comparison of HOL and Boyer-Moore for formal hardware verification (1993) (10)
- A Description Methodology for Parameterized Modules in the Boyer-Moore Logic (1992) (10)
- Memory and Data-Path Mapping for Image and Video Applications (1993) (10)
- An optimisation methodology for array mapping of affine recurrence equations in video and image processing (1994) (10)
- SLOCOP-II: a versatile timing verification system for MOSVLSI (1990) (9)
- Combining Reed-Solomon Codes and OFDM for Impulse Noise Mitigation: RS-OFDM (2006) (9)
- The adjoint switched capacitor network and its applications (1980) (9)
- Sailplane: a simulated annealing based CAD-tool for the analysis of limit-cycle behaviour (1985) (9)
- On Nanoscale Integration and Gigascale Complexity in the Post.Com World (2002) (9)
- Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator (1989) (9)
- Customized architectural methodologies for high-speed image and video processing (1988) (9)
- An SDMA algorithm for a high-speed wireless LAN. Performance and complexity (1998) (8)
- Microsystems: A Challenge for CAD Development (1990) (8)
- A Memory Efficient, Programmable Multi-Processor Architecture for Real-Time Motion Estimation Type Algorithms (1995) (8)
- Modeling Data Flow and Control Flow for DSP System Synthesis (1994) (8)
- On spatial-mode selection for the joint transmit and receive MMSE design (2004) (8)
- Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec (1999) (8)
- A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors (2002) (8)
- Beyond the horizon: The next 10x reduction in power - Challenges and solutions (2011) (8)
- Behavioral modeling and simulation of a mixed analog/digital automatic gain control loop in a 5 GHz WLAN receiver (2003) (8)
- A digital 72Mb/s 64-QAM OFDM tranceiver for 5GHz wireless LAN in 0.18µm CMOS (2001) (8)
- Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment (1992) (8)
- Design and optimization of dynamically reconfigurable embedded systems (2001) (8)
- Flexible hardware acceleration for multimedia oriented microprocessors (2000) (8)
- A CAD environment for the thorough analysis, simulation and characterization of VLSI implementable DSP systems (1986) (8)
- Reducing storage size for static control programs mapped onto parallel structures (1996) (7)
- System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache (1999) (7)
- Test algorithms for double-buffered random access and pointer-addressed memories (1993) (7)
- The systematic design of a motion estimation array architecture (1991) (7)
- Testability strategy and test pattern generation for register files and customized memories (1990) (7)
- Power-efficient flexible processor architecture for embedded applications (2003) (7)
- Affine transformations for multi-dimensional signal processing on ASIC regular arrays (1991) (7)
- Nonlinear transformations for high level regular array ASIC synthesis (1992) (7)
- Synthesis of pipelined DSP accelerators with dynamic scheduling (1995) (7)
- Formalized three-layer system-level reuse model and methodology for embedded data-dominated applications (2000) (7)
- Embedded Systems Education: How to Teach the Required Skills? (2004) (7)
- A system design methodology for telecommunication network applications (1997) (7)
- Correctness verification of VLSI modules supported by a very efficient Boolean prover (1989) (6)
- Efficient system-level functional verification methodology for multimedia applications (2003) (6)
- A computer-aided design methodology for mapping DSP-algorithms onto custom multiprocessor architectures (1986) (6)
- A fast adder-based multiplication unit for customised digital signal processors (1986) (6)
- Delay management algorithms for digital filter implementations (1983) (6)
- Models for bit-true simulation and high-level synthesis of DSP applications (1992) (6)
- Adaptive MMSE/pcPIC-MMSE multiuser detector for MC-CDMA satellite system (2001) (6)
- DARSI: RC data reduction [VLSI simulation] (1991) (6)
- Space-time chip equalizer receivers for WCDMA forward link with time-multiplexed pilot (2001) (6)
- A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints (1999) (6)
- Demands on Microelectronics Education and Research in the Post-PC Era (2000) (6)
- Breaking the bottleneck of sequential decoding for high-speed digital communication (1991) (6)
- Type-handling in bit-true silicon compilation for DSP (1989) (6)
- Efficient computer-analysis of ideal switched-capacitor circuits using matrix compaction techniques (1983) (6)
- Performance Through Hierarchy in Static Timing Verification (1992) (6)
- Timing optimization by bit-level arithmetic transformations (1995) (6)
- Efficient functional validation of system-level loop transformations for multi-media applications (1997) (6)
- General bounds on parasitic oscillations in arbitrary digital filters and their application in CAD (1984) (5)
- Application specific integrated filters for HIFI digital audio signal processing (1986) (5)
- Spatial-Mode Selection for the Joint Transmit and Receive MMSE Design (2004) (5)
- A single-package solution for wireless transceivers (1999) (5)
- Critically Subsampled Filterbanks for SISO Reed–Solomon Decoding (2006) (5)
- CORDIC-based HiFi digital FM demodulator algorithm for compact VLSI implementation (1985) (5)
- Nanoscale system design challenges: Business as usual? (2002) (5)
- Discrete coefficient optimisation for the CAD of arbitrary integrated digital filters (1983) (5)
- Designing single chip systems (1996) (5)
- A single-carrier/OFDM comparison for broadband wireless communication (2004) (5)
- Turbo-like soft-decision decoding of Reed-Solomon codes (2004) (5)
- Antenna array processing for wireless LAN (1998) (5)
- Large impact of task-level concurrency transformations on the MPEG4 IM1 player for weakly parallel processor platforms (2000) (5)
- A scalable architecture to support networked reconfiguration (1999) (5)
- Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks (1992) (5)
- Signal analysis and signal transformations for ASIC regular array architecture synthesis (1992) (5)
- Optimization of memory organisation and partitioning for decreased size and power in Vvideo and image processing systems (1995) (5)
- Search space reduction through clustering in test generation (1995) (5)
- DIANA.SC — a versatile top-down analysis tool for switched-capacitor circuits (1983) (5)
- Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL (1993) (5)
- Modelling hardware-specific data-types for simulation and compilation in HW/SW co-design (1996) (5)
- Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education (1998) (4)
- Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications (1991) (4)
- Code transformations for reduced data transfer and storage in low power realisations of MPEG-4 full-pel motion estimation (1998) (4)
- Silicon Synthesis of a Flexible CDMA/QPSK Mobile Communication Modem (1994) (4)
- A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms (2001) (4)
- Bit-alignment for retargetable code generators (1994) (4)
- A combined waveform relaxation-waveform relaxation Newton algorithm for efficient parallel circuit simulation (1990) (4)
- Critically subsampled filterbanks implementing Reed-Solomon codes (2004) (4)
- Soft-in soft-out Reed-Solomon decoding using critically subsampled filterbanks (2005) (4)
- REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures (1989) (4)
- Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment (1991) (4)
- CTH03-3: Reed-Solomon Codes Implementing a Coded OFDM Scheme for Rayleigh Fading Channels (2006) (4)
- Filterbank Decompositions for (Non)-Systematic Reed–Solomon Codes With Applications to Soft Decoding (2007) (4)
- Towards and Beyond 2015: technology, devices, circuits and systems (2006) (4)
- A unified box of CAD tools for the design of dedicated signal processing chips (1984) (4)
- Regular Array Synthesis for Image and Video Applications (1993) (4)
- Efficient microcoded processor design for fixed rate DFT and FFT (1990) (4)
- The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL (1992) (4)
- AN APPLICATION SPECIFIC MULTI-PRECISION MULTIPLIER ARCHITECTURE FOR A DYNAMIC RANGE COMPRESSOR FOR AUDIO* (1992) (4)
- A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU (1992) (3)
- Custom integration of a VLSI transmultiplexer using a computer-aided design methodology based on bit-serial architectures (1985) (3)
- A pictorial derivation of the signal processing mechanism of multiphase switched capacitor networks (1982) (3)
- A systematic approach for system bus load reduction applied to medical imaging (2001) (3)
- Automatic gain control for OFDM-based wireless burst receivers (2000) (3)
- Optimal scheduling and software pipelining of repetitive signal flow graphs with delay line optimization (1994) (3)
- Code size effects of power optimizing code transformations for embedded multimedia applications (1999) (3)
- Efficient computation of symbol statistics from bit a priori information in turbo receivers (2009) (3)
- Efficient VLSI Architectures for a High-Performance Digital Image Communication System (1990) (3)
- A parallel method for functional verification of medium and high throughput DSP synthesis (1994) (3)
- A Hilbert fractal codec for region oriented compression of color images (1996) (3)
- Signal type optimisation in the design of time-multiplexed DSP architectures (1994) (3)
- An integrated automatic design system for complex DSP algorithms (1990) (3)
- A SW/HW Interface API for Java/FPGA Co-Designed Applets (2001) (3)
- Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (1989) (3)
- Extended design reuse trade-offs in hardware-software architecture mapping (2000) (3)
- Defining Recursive Functions In HOL (1991) (3)
- Bit‐serial vlsi implementation for an optimized transmultiplexer design (1987) (3)
- An overview of CAD techniques for switched capacitor networks (1981) (3)
- A VLSI architecture for the 2-D wavelet transform with novel image scan (1995) (3)
- SPI: an open interface integrating highly interactive electronic CAD tools (1990) (3)
- CAD Tools for Third Generation Custom VLSI Design (1985) (2)
- System design challenges in the post-PC era (keynote address) (2000) (2)
- A Data Path Layout Assembler for High Performance (1990) (2)
- Computer Aided Design : Trying to Bridge the Gap (1978) (2)
- Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures (1995) (2)
- A unified theory for the computer aided analysis of general switched capacitor networks (1980) (2)
- Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers (1992) (2)
- CAD Tools for the optimized design of custom VLSI wave digital filters (1985) (2)
- Task concurrency management methodology summary (2001) (2)
- Analysis of the nonlinear behavior of a MEMS variable capacitor (2002) (2)
- Formal Hardware Verification In Hol And In Boyer-moore: A Comparative Analysis (1991) (2)
- Derivation of signal flow direction in MOS VLSI: an alternative (1990) (2)
- Connecting E-Dreams to Deep-Submicron Realities (2004) (2)
- OFDM vs. single-carrier: a multi-antenna comparison (2004) (2)
- Efficient false path elimination algorithms for timing verification by event graph preprocessing (1989) (2)
- Modeling multi-rate DSP specification semantics for formal transformational design in HOL (1994) (2)
- Filterbank decompositions for BCH-codes with applications to soft decoding and code division multiple acces systems (2005) (2)
- General datapath, controller and inter-communication architectures for the creation of a dedicated multi-processor environment (1986) (2)
- Optimizing graphics applications: a data transfer and storage exploration perspective (1999) (2)
- Partial scan and symbolic test at the register-transfer level (1995) (2)
- Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications (2003) (2)
- System-level exploration of association table implementations in telecom network applications (2002) (2)
- Reasoning About a Class of Linear Systems of Equations in HOL (1994) (1)
- Micro-coded ASIC Architecture for Real-Time Extraction of a Fetal Electro Cardiogram using the SVD Algorithm (1990) (1)
- The Heritage of Mead & Conway : What Has Remained the Same , What Has Changed , What Was Missed , and What Lies Ahead (2014) (1)
- Analysis of non-ideal sc circuits including resistances and op amp poles (1981) (1)
- Functional validation of system-level loop transfomations for power efficient caching (1998) (1)
- Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language (1989) (1)
- Methodology for propagating technology trade-offs over memory modules to the application level (2003) (1)
- Area Optimization of Bit-Parallel Custom Data Paths (1995) (1)
- Interconnect exploration for future wire dominated technologies (2002) (1)
- A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints (2000) (1)
- An optimisation methodology for mapping a diffusion algorithm for vision into a modular and flexible array architecture (1995) (1)
- Space-Time Chip Equalization for WCDMA Forward Link with Code-Multiplexed Pilot and Soft Handover (2007) (1)
- Investigation of finite word-length effects in arbitrary digital filters and the solution of travelling salesman problems using simulated annealing (1986) (1)
- Mixed-signal compensation techniques for low-cost 802.11a receiver front-ends (2002) (1)
- A flexible OFDM transceiver ASIC for high-speed wireless local networks (2000) (1)
- SPI: A Practical and Open Interface for Electronic CAD Tool Integration (1989) (1)
- Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors (2004) (1)
- Implementation of data structures (1993) (1)
- Telecommunications system design (1996) (1)
- Solving large scale assignment problems in high-level synthesis by approximative quadratic programming (2001) (1)
- Entwurf von Nanosystemen für Ambient Intelligence (Designing Nano-Scale Systems for the Ambient-Intelligence World) (2003) (1)
- On the frequency domain analysis of switched capacitor networks including all parasistics (1981) (1)
- Application Characteristics and Architectural Style (1997) (0)
- Asynchronous I/O Interface Synthesis (1994) (0)
- ASICs for a High Performance IVIulti Processor Systemfor Photo-realistic Image Synthesis (1992) (0)
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- Submicron design tools: problems and suppliers (1996) (0)
- Ambient Intelligence : A Giga-Scale Dream Facing Nano-Scale Realities (0)
- Cluster to ASU Assignment (1997) (0)
- Convergence analysis of iterative MIMO processing (2003) (0)
- The High-Level Data-Path Mapping Script (1997) (0)
- Design Technology Research and Education for Deep-Submicron Systems of the Next Century (1999) (0)
- Were the good old days all that good?: EDA then and now (2004) (0)
- Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead (2013) (0)
- Critically subsampled filterbanks implementing Reed-Solomon codes: an algebraic point of view (2005) (0)
- Simulation of Analog Sampled-Data MOSLSI Circuits (1984) (0)
- SYSTEM-LEVEL DATA-FLOW TRANSFORMATIONS FOR POWERREDUCTION IN IMAGE AND VIDEO PROCESSINGFrancky (1996) (0)
- 0 Embedded Architecture Co-Syntp . esis and System Integration (2003) (0)
- 2001 IEEE Computer Society Workshop on VLSI Wvlsi 2001: Emerging Technologies for VLSI Systems. Workshop Held April 19-20, 2001 Inorlando, FL (2001) (0)
- Designing systems on silicon: a digital spread spectrum pager (1996) (0)
- What is interface synthesis (1997) (0)
- Designing future system-on-a-chip: Impact on engineering education and research (2000) (0)
- System Design and Analysis Overview (2003) (0)
- ASP 12: Forum - Analog Electronics - a European Speciality? (1994) (0)
- A d-and-t roundtable - mixed-mode simulation (1989) (0)
- Proceedings : IEEE Computer Society Workshop on VLSI 2000, 19-20 April 2001, Orlando, Florida (2001) (0)
- DSP architecture synthesis (1993) (0)
- Channel estimation for a 100 Mbps SDMA WLAN basestation (1999) (0)
- Gate-level characterization and reduction of substrate noise in integrated digital circuits (2003) (0)
- A HILBERT FRACTAL CODEC FOR REGION ORIENTEDCOMPRESSION OF COLOR (1996) (0)
- Behavioral Interactive Silicon Compilation for Real Time Synchronous Algorithms (1989) (0)
- Efficient computer analysis of switched capacitor circuits via the z-domain (1981) (0)
- SESSION XV: LSI APPLICATIONS (1973) (0)
- Road through the interconnect red brick wall (2003) (0)
- Great challenges in nanoelectronics and impact on academic research: more than Moore or beyond CMOS? (2010) (0)
- Soft-Decision Decoding of Reed-Solomon codes based on Filterbanks (2004) (0)
- An application-specific architecture for the RBN-coder with efficient memory organization (1993) (0)
- Do our low-power tools have enough horse power? (panel session) (title only) (2000) (0)
- Rethinking Engineering Research and Education for Post-PC Systems-on-a-Chip (2000) (0)
- OFDM versus single-carrier: a multiple antenna comparison (2004) (0)
- Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation (1998) (0)
- Evolution of CAD tools towards third generation custom VLSI design (2019) (0)
- Proceedings : IEEE Computer Society Workshop on VLSI 2000 : system design for a system-on-chip era, 27-28 April, 2000, Orlando, Florida (2000) (0)
- An efficient memory organization for asic-implementation of the RBN-algorithm (1991) (0)
- Design Technology for Advanced Digital Systems in CMOS and Beyond (2008) (0)
- Session 1 digital LSI techniques (1978) (0)
- IIR critically subsampled filterbanks implementing systematic Reed-Solomon codes (2005) (0)
- Interconnect and Architecture Planning: Global interconnect trade-off for technology over memory modules to application level: case study. (2003) (0)
- On the use of hierarchy in timing verification with statically sensitizable paths (1992) (0)
- Scalable Gate-Level Models for Power and Timing Analysis (2007) (0)
- A Generalized Signal Transition Graph Model for Specification of Complex System Level Interfaces (1994) (0)
- Guest Editors' Introduction (1999) (0)
- A programmable spread spectrum modem chip for wireless communications (1996) (0)
- The multi-thread graph, a model for embedded software synthesis (1996) (0)
- Implementation of control functions (1993) (0)
- Computer aided design of switched capacitor circuits using the DIANA program (1981) (0)
- Reasoning about linear systems of Equations on HOL (1994) (0)
- Exploiting wiring hierarchy and system design to surpass the interconnect red brick wall (2002) (0)
- A spread spectrum chip family for wireless comununications (1996) (0)
- An Architecture for Ray - Bezier Patch Intersection (1993) (0)
- Design of the Low Complexity Turbo MIMO Receiver for WLAN (2004) (0)
- Improving DSP design expertise by stepwise educational intensification (1995) (0)
- RS-OFDM: Using Reed-Solomon codes as coded OFDM modulator (2006) (0)
- Retargetable code generation using a graph-based processor mode (1996) (0)
- Critically sampled filterbank representation of Reed-Solomon codes (2004) (0)
- Modeling Data Flow and Control Flow for Digital Signal Processing System Synthesis (1994) (0)
- The Underlying Synthesis Data Models (1997) (0)
- A Time Abstraction Method for Efficient Verification of Communicating Systems (1994) (0)
- Implementation of high-level operations (1993) (0)
- Proceedings IEEE Computer Society Workshop on VLSI '99 : system design: towards system-on-a-chip paradigm, April 8-9, 1999, Orlando, Florida (1999) (0)
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