Irith Pomeranz
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Israeli electrical engineer
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Why Is Irith Pomeranz Influential?
(Suggest an Edit or Addition)According to Wikipedia, Irith Pomeranz is an Israeli electrical engineer known for her research in circuit testing and fault tolerance. She is a professor of electrical and computer engineering at Purdue University and a Fellow of the IEEE.
Irith Pomeranz's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS (1991) (428)
- Transient-fault recovery for chip multiprocessors (2003) (365)
- Techniques for minimizing power dissipation in scan and combinational circuits during test application (1998) (333)
- Transient-fault recovery using simultaneous multithreading (2002) (329)
- Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits (1993) (243)
- Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs (2006) (242)
- 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set (1992) (159)
- On static compaction of test sequences for synchronous sequential circuits (1996) (124)
- On test data volume reduction for multiple scan chain designs (2002) (113)
- SOC test scheduling using simulated annealing (2003) (109)
- On the generation of small dictionaries for fault location (1992) (108)
- Vector restoration based static compaction of test sequences for synchronous sequential circuits (1997) (106)
- On n-detection test sets and variable n-detection test sets for transition faults (1999) (101)
- Generation of Functional Broadside Tests for Transition Faults (2006) (100)
- On the generation of scan-based test sets with reachable states for testing under functional operation conditions (2004) (100)
- On generating pseudo-functional delay fault tests for scan designs (2005) (97)
- On-chip compression of output responses with unknown values using lfsr reseeding (2003) (93)
- On reducing peak current and power during test (2005) (92)
- Fault dictionary compression and equivalence class computation for sequential circuits (1993) (90)
- Classification of Faults in Synchronous Sequential Circuits (1993) (89)
- On output response compression in the presence of unknown output values (2002) (82)
- Compact test sets for high defect coverage (1997) (81)
- The Multiple Observation Time Test Strategy (1992) (76)
- A Low Power Pseudo-Random BIST Technique (2002) (75)
- On generating high quality tests for transition faults (2002) (73)
- On reducing test data volume and test application time for multiple scan chain designs (2003) (72)
- An efficient non-enumerative method to estimate path delay fault coverage (1992) (68)
- Forward-looking fault simulation for improved static compaction (2001) (67)
- ROTCO: a reverse order test compaction technique (1992) (65)
- On static test compaction and test pattern ordering for scan designs (2001) (64)
- Selection of potentially testable path delay faults for test generation (2000) (64)
- Static Test Compaction for Scan-Based Designs to Reduce Test Application Time (1998) (62)
- On compacting test response data containing unknown values (2003) (61)
- A method for identifying robust dependent and functionally unsensitizable paths (1997) (60)
- PROPTEST: a property based test pattern generator for sequential circuits using test compaction (1999) (56)
- At-speed delay testing of synchronous sequential circuits (1992) (56)
- LOCSTEP: a logic simulation based test generation procedure (1995) (56)
- An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits (1994) (55)
- NEST: a nonenumerative test generation method for path delay faults in combinational circuits (1995) (53)
- On identifying undetectable and redundant faults in synchronous sequential circuits (1994) (52)
- Low Shift and Capture Power Scan Tests (2007) (52)
- On correction of multiple design errors (1995) (52)
- Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits (2008) (51)
- On the effects of test compaction on defect coverage (1996) (50)
- On generating compact test sequences for synchronous sequential circuits (1995) (49)
- Methods for improving transition delay fault coverage using broadside tests (2005) (49)
- An optimal algorithm for cycle breaking in directed graphs (1995) (46)
- On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences (1996) (46)
- A diagnostic test generation procedure for synchronous sequential circuits based on test elimination (1998) (46)
- COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits (1992) (45)
- A measure of quality for n-detection test sets (2004) (44)
- On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios (2005) (44)
- On compacting test sets by addition and removal of test vectors (1994) (44)
- On Selecting Testable Paths in Scan Designs (2002) (44)
- On testing of interconnect open defects in combinational logic circuits with stems of large fanout (2002) (44)
- Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration (1998) (43)
- Defect aware test patterns (2005) (43)
- On Dictionary-Based Fault Location in Digital Logic Circuits (1997) (43)
- NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits (1993) (39)
- A unified fault model and test generation procedure for interconnect opens and bridges (2005) (39)
- On achieving a complete fault coverage for sequential machines using the transition fault model (1991) (39)
- Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects (2008) (39)
- Techniques for improving the efficiency of sequential circuit test generation (1999) (39)
- On the Detectability of Scan Chain Internal Faults An Industrial Case Study (2008) (39)
- Enhancing Delay Fault Coverage through Low Power Segmented Scan (2006) (38)
- An efficient method to identify untestable path delay faults (2001) (37)
- Application of homing sequences to synchronous sequential circuit testing (1993) (37)
- Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test-Points (1994) (36)
- Fault equivalence identification using redundancy information and static and dynamic extraction (2001) (36)
- Test transformation to improve compaction by statistical encoding (2000) (36)
- MIX: a test generation system for synchronous sequential circuits (1998) (36)
- Definition and generation of partially-functional broadside tests (2009) (36)
- SPADES: a simulator for path delay faults in sequential circuits (1992) (36)
- Functional test generation for delay faults in combinational circuits (1995) (35)
- On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits (1996) (35)
- On reset based functional broadside tests (2010) (34)
- On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation (1994) (34)
- Dynamic test compaction for synchronous sequential circuits using static compaction techniques (1996) (34)
- GALLOP: genetic algorithm based low power FSM synthesis by simultaneous partitioning and state assignment (2003) (33)
- Forming N-detection test sets without test generation (2007) (33)
- Static test compaction for delay fault test sets consisting of broadside and skewed-load tests (2011) (32)
- On finding undetectable and redundant faults in synchronous sequential circuits (1998) (32)
- Test generation for multiple state-table faults in finite-state machines (1995) (32)
- On Testing Delay Faults In Macro-based Combinational Circuits (1994) (32)
- Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage (1998) (32)
- Compact test generation for bridging faults under I/sub DDQ/ testing (1995) (31)
- Synthesis of multi-level combinational circuits for complete robust path delay fault testability (1992) (31)
- Z-sets and z-detections: circuit characteristics that simplify fault diagnosis (2004) (30)
- A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests (2006) (30)
- On Complete Functional Broadside Tests for Transition Faults (2008) (30)
- Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits (2003) (30)
- On test generation for transition faults with minimized peak power dissipation (2004) (30)
- Conflict driven techniques for improving deterministic test pattern generation (2002) (30)
- On diagnosis and correction of design errors (1993) (29)
- On determining symmetries in inputs of logic circuits (1994) (29)
- Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests (2010) (29)
- Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation (2008) (29)
- Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage (2001) (28)
- Built-in test generation for synchronous sequential circuits (1997) (28)
- On speeding-up vector restoration based static compaction of test sequences for sequential circuits (1998) (28)
- Scan tests with multiple fault activation cycles for delay faults (2006) (27)
- On Error Correction In Macro-based Circuits (1994) (27)
- Full scan fault coverage with partial scan (1999) (27)
- Pseudo random patterns using Markov sources for scan BIST (2002) (27)
- On improving genetic optimization based test generation (1997) (26)
- A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults (2006) (26)
- PROPTEST: a property-based test generator for synchronous sequential circuits (2003) (26)
- Test enrichment for path delay faults using multiple sets of target faults (2002) (26)
- GAFPGA: Genetic algorithm for FPGA technology mapping (1993) (26)
- ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction (2008) (26)
- Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations (2003) (25)
- On achieving complete fault coverage for sequential machines (1994) (25)
- STOIC: state assignment based on output/input functions (1993) (24)
- SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration (2000) (23)
- Test data compression using don't-care identification and statistical encoding (2002) (23)
- On Synthesis-for-Testability of Combinational Logic Circuits (1995) (23)
- Battery-aware dynamic voltage scaling in multiprocessor embedded system (2005) (23)
- Testing for systematic defects based on DFM guidelines (2007) (22)
- On achieving zero aliasing for modeled faults (1992) (22)
- Exact computation of maximally dominating faults and its application to n-detection tests (2002) (22)
- Scan-Based Tests with Low Switching Activity (2007) (22)
- A new approach to test generation and test compaction for scan circuits (2003) (22)
- A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors (2015) (21)
- Fault equivalence identification in combinational circuits using implication and evaluation techniques (2003) (21)
- Detection of Internal Stuck-open Faults in Scan Chains (2008) (21)
- A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits (2000) (21)
- A scan BIST generation method using a Markov source and partial bit-fixing (2003) (20)
- On achieving complete coverage of delay faults in full scan circuits using locally available lines (1999) (20)
- A fault simulation based test pattern generator for synchronous sequential circuits (1999) (20)
- Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation (2007) (20)
- Defect diagnosis based on pattern-dependent stuck-at faults (2004) (19)
- Test generation for synchronous sequential circuits using multiple observation times (1991) (19)
- On n-detection test sequences for synchronous sequential circuits (1997) (19)
- Vector replacement to improve static-test compaction forsynchronous sequential circuits (2001) (19)
- OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis (2014) (19)
- A novel method of improving transition delay fault coverage using multiple scan enable signals (2005) (19)
- On validating data hold times for flip-flops in sequential circuits (2000) (19)
- On achieving complete testability of synchronous sequential circuits with synchronizing sequences (1994) (18)
- Generation of Multi-Cycle Broadside Tests (2011) (18)
- Scan BIST targeting transition faults using a Markov source (2004) (18)
- On pass/fail dictionaries for scan circuits (2001) (18)
- Don't-care identification on specific bits of test patterns (2002) (18)
- Output-Dependent Diagnostic Test Generation (2010) (17)
- On the use of fault dominance in n-detection test generation (2001) (17)
- Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy (1991) (17)
- Masking of unknown output values during output response compression by using comparison units (2004) (17)
- Dominance based analysis for large volume production fail diagnosis (2006) (17)
- SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes (1994) (17)
- New procedures for identifying undetectable and redundant faults in synchronous sequential circuits (1999) (17)
- Functional Broadside Tests with Minimum and Maximum Switching Activity (2008) (17)
- Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure (2013) (17)
- Improving the proportion of at-speed tests in scan BIST (2000) (16)
- FOLD (2015) (16)
- Implication and evaluation techniques for proving fault equivalence (1999) (16)
- On the Computation of Common Test Data for Broadside and Skewed-Load Tests (2012) (16)
- On tests to detect via opens in digital CMOS circuits (2008) (16)
- Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests (2014) (16)
- Selecting High-Quality Delay Tests for Manufacturing Test and Debug (2006) (16)
- On Test Generation With Test Vector Improvement (2010) (16)
- ACHIEVING COMPLETE DELAY FAULT TESTABILITY BY EXTRA INPUTS (1991) (15)
- Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations (2001) (15)
- A scalable method for the generation of small test sets (2009) (15)
- Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning (1998) (15)
- Computation of Seeds for LFSR-Based Diagnostic Test Generation (2015) (15)
- Z-DFD: design-for-diagnosability based on the concept of Z-detection (2004) (15)
- Low-Power Test Generation by Merging of Functional Broadside Test Cubes (2014) (15)
- On test program compaction (2015) (15)
- Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions (2005) (15)
- Fault simulation for synchronous sequential circuits under the multiple observation time testing approach (1993) (15)
- Pattern sensitivity: a property to guide test generation for combinational circuits (1999) (15)
- Switching Activity as a Test Compaction Heuristic for Transition Faults (2010) (15)
- $z$-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs (2007) (14)
- Diagnostic Test Generation Based on Subsets of Faults (2007) (14)
- Path Selection for Transition Path Delay Faults (2010) (14)
- Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation (2003) (14)
- Built-in generation of functional broadside tests (2011) (14)
- Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences (1999) (14)
- Synchronization of large sequential circuits by partial reset (1996) (14)
- New Techniques to Reduce the Execution Time of Functional Test Programs (2017) (14)
- Improving the Detectability of Resistive Open Faults in Scan Cells (2009) (14)
- Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity (2011) (14)
- Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity (1993) (13)
- Design-for-testability for path delay faults in large combinational circuits using test points (1998) (13)
- Vector-restoration-based static compaction using random initial omission (2004) (13)
- Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length (2012) (13)
- Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits (2011) (13)
- Forming multi-cycle tests for delay faults by concatenating broadside tests (2010) (13)
- Test Generation for Open Defects in CMOS Circuits (2006) (13)
- On minimizing the number of test points needed to achieve complete robust path delay fault testability (1996) (13)
- A diagnostic test generation procedure for combinational circuits based on test elimination (1998) (13)
- Static Test Data Volume Reduction Using Complementation or Modulo-$M$ Addition (2011) (13)
- On the characterization of hard-to-detect bridging faults (2003) (13)
- Static compaction for two-pattern test sets (1995) (12)
- Test-point insertion to enhance test compaction for scan designs (2000) (12)
- Testability considerations in technology mapping (1994) (12)
- Static test compaction procedure for large pools of multicycle functional broadside tests (2018) (12)
- TOV: Sequential Test Generation by Ordering of Test Vectors (2010) (12)
- Piecewise-Functional Broadside Tests Based on Reachable States (2015) (12)
- A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis (1993) (12)
- On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits (2000) (12)
- A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution (2008) (12)
- On double transition faults as a delay fault model (1996) (12)
- A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set (2002) (12)
- On application of output masking to undetectable faults in synchronous sequential circuits with Design-For-Testability logic (2003) (12)
- Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm (2016) (11)
- Level of similarity: a metric for fault collapsing (2004) (11)
- MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level (1995) (11)
- Scan-BIST based on transition probabilities for circuits with single and multiple scan chains (2006) (11)
- Test generation for synchronous sequential circuits based on fault extraction (1991) (11)
- A method to enhance the fault coverage obtained by output response comparison of identical circuits (2001) (11)
- Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs (2012) (11)
- Skewed-Load Tests for Transition and Stuck-at Faults (2019) (11)
- Reducing the number of specified values per test vector by increasing the test set size (2006) (11)
- Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences (2013) (11)
- Worst-case and average-case analysis of n-detection test sets (2005) (11)
- A learning-based method to match a test pattern generator to a circuit-under-test (1993) (11)
- On methods to match a test pattern generator to a circuit-under-test (1998) (11)
- Generation of Mixed Test Sets for Transition Faults (2012) (11)
- On the compaction of test sets produced by genetic optimization (1997) (11)
- REDI: an efficient fault oriented procedure to identify redundant faults in combinational logic circuits (2001) (10)
- Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing (2011) (10)
- Improved built-in test pattern generators based on comparison units for synchronous sequential circuits (1998) (10)
- Reverse-order-restoration-based static test compaction for synchronous sequential circuits (2003) (10)
- Forming N-detection test sets from one-detection test sets without test generation (2005) (10)
- Test generation for path delay faults based on learning (1993) (10)
- Simulation based test generation for scan designs (2000) (10)
- On diagnosis and diagnostic test generation for pattern-dependenttransition faults (2001) (10)
- A test pattern ordering algorithm for diagnosis with truncated fail data (2006) (10)
- On reducing test application time for scan circuits using limited scan operations and transfer sequences (2005) (10)
- On improving static test compaction for sequential circuits (2001) (10)
- An approach for improving the levels of compaction achieved by vector omission (1999) (10)
- Generation of close-to-functional broadside tests with equal primary input vectors (2015) (10)
- On Test Compaction of Broadside and Skewed-Load Test Cubes (2013) (10)
- Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage (2012) (10)
- Test application time reduction for scan circuits using limited scan operations (2004) (9)
- Double–Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits (2009) (9)
- On path selection for delay fault testing considering operating conditions [logic IC testing] (2003) (9)
- On the detection of reset faults; in synchronous sequential circuits (1997) (9)
- Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis (2007) (9)
- Weighted pseudo-random BIST for n-detection of single stuck-at faults (2004) (9)
- A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis (2016) (9)
- Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage (2010) (9)
- Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences (2002) (9)
- On Fault Simulation for Synchronous Sequential Circuits (1995) (9)
- Generalization of independent faults for transition faults (1992) (9)
- On Improving Fault Diagnosis for Synchronous Sequential Circuits (1994) (9)
- Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests (2018) (9)
- ACTIV-LOCSTEP: a test generation procedure based on logic simulation and fault activation (1997) (9)
- Detectability of internal bridging faults in scan chains (2009) (8)
- A test generation procedure for avoiding the detection of functionally redundant transition faults (2006) (8)
- Concurrent on-line testing of identical circuits through output comparison using non-identical input vectors (2004) (8)
- Theory and practice of sequential machine testing and testability (1993) (8)
- Signal-Transition Patterns of Functional Broadside Tests (2013) (8)
- Defect diagnosis based on DFM guidelines (2010) (8)
- Enhanced Broadside Testing for Improved Transition Fault Coverage (2007) (8)
- Reducing fault latency in concurrent on-line testing by using checking functions over internal lines (2004) (8)
- The minimum test set problem for circuits with nonreconvergent fanout (1991) (8)
- Reducing test application time for full scan circuits by the addition of transfer sequences (2000) (8)
- Effect of Communication in a Parallel Genetic Algorithm (1992) (8)
- Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests (2014) (8)
- On testing of non-isolated embedded legacy cores and their surround logic (1999) (8)
- Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits (1999) (8)
- Sequential Test Generation Based on Preferred Primary Input Cubes (2017) (8)
- Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths (2008) (8)
- Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States (2014) (8)
- INCREDYBLE-TG: INCREmental DYnamic Test Generation Based on LEarning (1993) (8)
- Low-complexity fault simulation under the multiple observation time testing approach (1995) (8)
- FaultHound: Value-locality-based soft-fault tolerance (2015) (8)
- On the coverage of delay faults in scan designs with multiple scan chains (2002) (8)
- Diagnosis of transition fault clusters (2011) (8)
- Static test compaction for synchronous sequential circuits based on vector restoration (1999) (8)
- Scan Shift Power of Functional Broadside Tests (2011) (8)
- Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects (2008) (7)
- Autoscan: a scan design without external scan inputs or outputs (2005) (7)
- Path selection based on static timing analysis considering input necessary assignments (2013) (7)
- Effectiveness of scan-based delay fault tests in diagnosis of transition faults (2007) (7)
- A Delay Fault Model for At-Speed Fault Simulation and Test Generation (2006) (7)
- Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion (1991) (7)
- On Finding Don't Cares in Test Sequences for Sequential Circuits (2005) (7)
- A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction (2016) (7)
- On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits (2010) (7)
- Safe Fault Collapsing Based on Dominance Relations (2008) (7)
- Test sequences to achieve high defect coverage for synchronous sequential circuits (1998) (7)
- On test compaction objectives for combinational and sequential circuits (1998) (7)
- A flexible path selection procedure for path delay fault testing (1999) (7)
- Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults (2011) (7)
- Sequence reordering to improve the levels of compaction achievable by static compaction procedures (2001) (7)
- On the use of multi-cycle tests for storage of two-cycle broadside tests (2014) (7)
- On the detection of path delay faults by functional broadside tests (2012) (7)
- State assignment using input/output functions (1992) (7)
- Test Compaction Under Bounded Transparent-Scan (2019) (7)
- Diagnostic Fail Data Minimization Using an $N$ -Cover Algorithm (2016) (7)
- On-chip Generation of the Second Primary Input Vectors of Broadside Tests (2009) (7)
- Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage (2020) (6)
- LFSR-Based Generation of Multicycle Tests (2017) (6)
- Test data compression based on input-output dependence (2003) (6)
- Diagnostic Test Generation Targeting Equivalence Classes (2007) (6)
- Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults (2006) (6)
- LFSR-Based Generation of Partially-Functional Broadside Tests (2016) (6)
- An Improved Markov Source Design for Scan BIST (2003) (6)
- Enhanced genetic algorithms in constrained search spaces with emphasis in parallel environments (1993) (6)
- On potential fault detection in sequential circuits (1996) (6)
- Maximal Independent Fault Set for Gate-Exhaustive Faults (2021) (6)
- Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion (2008) (6)
- Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences (2009) (6)
- Path delay fault test generation for standard scan designs using state tuples (2002) (6)
- Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences (2006) (6)
- On test data compression and n-detection test sets (2003) (6)
- Fault Simulation Under The Multiple Observation Time Approach Using Backward Implications (1997) (6)
- Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs (2010) (6)
- Output Hazard-Free Transition Delay Fault Test Generation (1998) (6)
- Test and non-test cubes for diagnostic test generation based on merging of test cubes (2014) (6)
- A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy (2008) (6)
- Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences (2003) (6)
- A divide-and-conquer approach to test generation for large synchronous sequential circuits (1992) (6)
- Close-to-Functional Broadside Tests With a Safety Margin (2017) (6)
- Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set (2015) (6)
- Concurrent online testing of identical circuits using nonidentical input vectors (2005) (6)
- Functional Broadside Tests With Incompletely Specified Scan-In States (2013) (6)
- The accidental detection index as a fault ordering heuristic for full-scan circuits (2005) (6)
- Forward-Looking Reverse Order Fault Simulation for $n$ -Detection Test Sets (2009) (6)
- Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits (2006) (6)
- On diagnosis of pattern-dependent delay faults (2000) (6)
- Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences (2014) (6)
- Delay fault models for VLSI circuits1 (1998) (6)
- Circuit Independent Weighted Pseudo-Random BIST Pattern Generator (2005) (6)
- On finding functionally identical and functionally opposite lines in combinational logic circuits (1996) (6)
- Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis (2010) (5)
- Enhanced untestable path analysis using edge graphs (2000) (5)
- A low power pseudo-random BIST technique (2002) (5)
- Design-for-testability for multi-cycle broadside tests by holding of state variables (2014) (5)
- Aliasing computation using fault simulation with fault dropping (1993) (5)
- Selection of a Fault Model for Fault Diagnosis Based on Unique Responses (2009) (5)
- On the characterization and efficient computation of hard-to-detect bridging faults (2004) (5)
- On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit (2004) (5)
- A Functional Fault Model with Implicit Fault Effect Propagation Requirements (2006) (5)
- LFSR-Based Test Generation for Path Delay Faults (2019) (5)
- A postprocessing procedure to reduce the number of different test lengths in a test set for scan circuits (2001) (5)
- An Enhanced Logic BIST Architecture for Online Testing (2008) (5)
- N-pass N-detection Fault Simulation and Its Applications (2002) (5)
- Max-Fill: A method to generate high quality delay tests (2011) (5)
- Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults (2019) (5)
- A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits (2002) (5)
- On cancelling the effects of logic sharing for improved path delay fault testability (1996) (5)
- On test generation for interconnected finite-state machines-the output sequence justification problem (1996) (5)
- A method to find don't care values in test sequences for sequential circuits (2003) (5)
- On generating test sets that remain valid in the presence of undetected faults (1997) (5)
- Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes (2013) (5)
- Path-oriented transition fault test generation considering operating conditions (2005) (5)
- On the Saturation of $n$-Detection Test Generation by Different Definitions With Increased $n$ (2008) (5)
- On synchronizing sequences and test sequence partitioning (1998) (5)
- Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes (2007) (5)
- A bridging fault model for line coverage in the presence of undetected transition faults (2017) (5)
- On improving a fault simulation based test generator for synchronous sequential circuits (2001) (5)
- Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission (2002) (5)
- A postprocessing procedure of test enrichment for path delay faults (2004) (4)
- Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults (2017) (4)
- Non-Uniform Coverage by $n$-Detection Test Sets (2012) (4)
- Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits (2002) (4)
- Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests (2018) (4)
- On removing redundant faults in synchronous sequential circuits (1998) (4)
- Multi-cycle broadside tests with runs of constant primary input vectors (2013) (4)
- N-distinguishing Tests for Enhanced Defect Diagnosis (2009) (4)
- An approach to test compaction for scan circuits that enhances at-speed testing (2001) (4)
- Reset and partial-reset-based functional broadside tests (2012) (4)
- On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan (2006) (4)
- On the saturation of n-detection test sets with increased n (2007) (4)
- Testing of Fault-Tolerant Hardware Through Partial Control of Inputs (1993) (4)
- Robust Fault Models Where Undetectable Faults Imply Logic Redundancy (2010) (4)
- Improving the efficiency of static compaction based on chronological order enumeration of test sequences [logic testing] (2002) (4)
- Test vector chains for increasing the fault coverage and numbers of detections (2009) (4)
- A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set (2016) (4)
- On synchronizable circuits and their synchronizing sequences (2000) (4)
- Selecting Replacements for Undetectable Path Delay Faults (2017) (4)
- Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests (2013) (4)
- Test Compaction for Transition Faults under Transparent-Scan (2006) (4)
- Fault simulation with test switching for static test compaction (2014) (4)
- Random limited-scan to improve random pattern testing of scan circuits (2001) (4)
- Computing Seeds for LFSR-Based Test Generation From Nontest Cubes (2016) (4)
- Multiple fault activation cycle tests for transistor stuck-open faults (2010) (4)
- Improving the accuracy of defect diagnosis by considering reduced diagnostic information (2015) (4)
- Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines (2019) (4)
- Functional broadside tests for embedded logic blocks (2012) (4)
- Fault location based on circuit partitioning (1996) (4)
- TEA: A Test Generation Algorithm for Designs with Timing Exceptions (2019) (4)
- A Generalized Test Generation Procedure for Path Delay Faults (1998) (4)
- Selecting state variables for improved on-line testability through output response comparison of identical circuits (2010) (4)
- On codeword testing of two-rail and parity TSC checkers (1994) (4)
- Properties of maximally dominating faults (2004) (4)
- Recovery during concurrent on-line testing of identical circuits (2005) (4)
- Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests (2018) (3)
- On the Generation of Weights for Weighted Pseudo Random Testing (1993) (3)
- Combinationally irredundant ISCAS-89 benchmark circuits (1996) (3)
- Fixed-State Tests for Delay Faults in Scan Designs (2011) (3)
- A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion (1992) (3)
- Generation of test cases for hardware design verification of a super-scalar Fetch Processor (1996) (3)
- Generation of compact multi-cycle diagnostic test sets (2013) (3)
- Computation of Seeds for LFSR-Based n-Detection Test Generation (2017) (3)
- Using Dummy Bridging Faults to Define Reduced Sets of Target Faults (2005) (3)
- Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation (2015) (3)
- Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits (2007) (3)
- On the use of reset to increase the testability of interconnected finite-state machines (1997) (3)
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- Functional Broadside Templates for Low-Power Test Generation (2013) (3)
- Observation Points on State Variables for the Compaction of Multicycle Tests (2018) (3)
- A built-in self-test method for diagnosis of synchronous sequential circuits (2001) (3)
- Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction (2015) (3)
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- Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults (2016) (3)
- Static test compaction for multiple full-scan circuits (2003) (3)
- Low-power skewed-load tests based on functional broadside tests (2014) (3)
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- Test pattern generation for path delay faults in synchronous sequential circuits using multiple fast clocks and multiple observation times (1994) (3)
- Test Compaction by Test Removal Under Transparent Scan (2019) (3)
- On multiple bridging faults (2010) (3)
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- On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests (2011) (3)
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- Tuple detection for path delay faults: a method for improving test set quality (2005) (3)
- Static test compaction for mixed broadside and skewed-load transition fault test sets (2013) (3)
- Broadside and Functional Broadside Tests for Partial-Scan Circuits (2011) (3)
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- The effects of test compaction on fault diagnosis (1999) (3)
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- Theorems for identifying undetectable faults in partial-scan circuits (2003) (3)
- Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage (2012) (3)
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- On masking of redundant faults in synchronous sequential circuits with design-for-testability logic (2005) (2)
- Design-for-testability for synchronous sequential circuits using locally available lines (1998) (2)
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- Synthesis for Broadside Testability of Transition Faults (2008) (2)
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- A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits (1999) (2)
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- COREL: a dynamic compaction procedure for synchronous sequential circuits with repetition and local static compaction (2001) (2)
- Test compaction by test cube merging for four-way bridging faults (2015) (2)
- Functional and partially-functional skewed-load tests (2010) (2)
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- Static test compaction for circuits with multiple independent scan chains (2016) (2)
- Reducing the input test data volume under transparent scan (2014) (2)
- On undetectable faults in partial scan circuits (2002) (2)
- Selecting Close-to-Functional Path Delay Faults for Test Generation (2020) (2)
- PROPTEST: A Property-Based Test Generator for (2003) (2)
- Computing Two-Pattern Test Cubes for Transition Path Delay Faults (2013) (2)
- EXOP (Extended Operation): A new logical fault model for digital circuits (1993) (2)
- Static test compaction for diagnostic test sets of full-scan circuits (2010) (2)
- Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs (2020) (2)
- Fail data reduction for diagnosis of scan chain faults under transparent-scan (2017) (2)
- Fault diagnosis aware ATE assisted test response compaction (2011) (2)
- Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design (2019) (2)
- TSV and DFT cost aware circuit partitioning for 3D-SOCs (2012) (2)
- Two-Dimensional Static Test Compaction for Functional Test Sequences (2015) (2)
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- POSTT: Path-oriented static test compaction for transition faults in scan circuits (2017) (2)
- Fault simulation based test generation for combinational circuits using dynamically selected subcircuits (1999) (2)
- Don't Care Identification and Statistical Encoding for Test Data Compression (2004) (2)
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- Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences (2017) (2)
- Fast Test Generation for Structurally Similar Circuits (2022) (2)
- Target Faults for Test Compaction Based on Multicycle Tests (2020) (2)
- Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions (2009) (2)
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- Functional Broadside Test Generation Using a Commercial ATPG Tool (2017) (2)
- Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity (2015) (2)
- A genetic learning strategy in constrained search spaces (1992) (2)
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- A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences (2015) (2)
- VERSE: a vector replacement procedure for improving test compaction in synchronous sequential circuits (1999) (2)
- ATE assisted test response compaction (2010) (2)
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- Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults (2013) (2)
- A test application scheme for embedded full-scan circuits to reduce testing costs (1992) (2)
- Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests (2008) (2)
- Test data volume reduction by test data realignment (2003) (2)
- Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks (2014) (2)
- Selection of Functional Test Sequences With Overlaps (2014) (2)
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- Random Test Generation With Input Cube Avoidance (2009) (2)
- Functional Broadside Tests Under Broadcast Scan (2020) (1)
- Fault isolation for nonisolated blocks (2004) (1)
- Test generation for embedded circuits under the transparent-scan approach (2005) (1)
- Undetectable transition faults under broadside tests with constant primary input vectors (2012) (1)
- Boundary-Functional Broadside and Skewed-Load Tests (2018) (1)
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- Non-Masking Non-Robust Tests for Path Delay Faults (2020) (1)
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- GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults (2022) (1)
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- Improved$n$-Detection Test Sequences Under Transparent Scan (2006) (1)
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- Storage-Based Logic Built-In Self-Test with Cyclic Tests (2023) (0)
- Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults (2020) (0)
- Topic: T1 Defects, Faults, Variability and Reliability Analysis and Modeling (2014) (0)
- Achieve complete robust path delay fault testability (1995) (0)
- Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan (2022) (0)
- State persistence: a property for guiding test generation (2009) (0)
- Optimizing SOC Test Resources using Dual Sequences (2003) (0)
- Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults (2022) (0)
- Static Compaction by Merging of Seeds for LFSR-Based Test Generation (2017) (0)
- Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation (2021) (0)
- On-chip generation of primary input sequences for multicycle functional broadside tests (2018) (0)
- Performance aware partitioning for 3D-SOCs (2012) (0)
- Built-in generation of functional broadside tests considering primary input constraints (2014) (0)
- Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits (2001) (0)
- Partially-Specified Output Response for Reduced Fail Data Volume (2022) (0)
- Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults (2002) (0)
- TEMPLATES: a test generation procedure for synchronous sequential circuits (1997) (0)
- Usable Circuits with Imperfect Scan Logic (2022) (0)
- Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits (2009) (0)
- Reverse Low-Power Broadside Tests (2020) (0)
- Constrained test generation for embedded synchronous sequential circuits with serial-input access (2004) (0)
- On Common-Mode Skewed-Load and Broadside Tests (2008) (0)
- Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults (2022) (0)
- Two-Dimensional Test Generation Objective (2022) (0)
- Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests (2022) (0)
- Fault Simulation for Synchronous Se uential Circuits (1993) (0)
- Test vector chains for increased resolution and reduced storage of diagnostic tests (2012) (0)
- Partitioned n-detection test generation (2009) (0)
- Preferred Fill: A Scalable MethodtoReduceCapture PowerforScan BasedDesigns (2006) (0)
- Incomplete Tests for Undetectable Faults to Improve Test Set Quality (2019) (0)
- Using piecewise-functional broadside tests for functional broadside test compaction (2017) (0)
- Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences (2015) (0)
- Conference Reports (2004) (0)
- Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads (2018) (0)
- A Built-In Self-Test Method for Diagnosis of (2001) (0)
- Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines (2022) (0)
- On multi-cycle test cubes (2013) (0)
- Fault diagnosis and fault model aliasing (2005) (0)
- Gate-level design diagnosis using a learning-based search strategy (1994) (0)
- The cut delay fault model for guiding the generation of n-detection test sets for transition faults (2006) (0)
- New Targets for Diagnostic Test Generation (2020) (0)
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