Jacob Abraham | Academic Influence

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Jacob Abraham

Engineering

#1115

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#1702

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#442

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Electrical Engineering

#208

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#239

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#92

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Jacob Abraham

Computer Science

#2313

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#2411

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#1033

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Computer Architecture

#23

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#23

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#18

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Database

#1062

World Rank

#1117

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#304

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computer-science Degrees

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Engineering
Computer Science

Jacob Abraham's Degrees

PhD Computer Science Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering Stanford University

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Why Is Jacob Abraham Influential?

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According to Wikipedia, Jacob A. Abraham is an American computer scientist and engineer who is currently the Cockrell Family Regents Chair in the Department of Electrical and Computer Engineering at the University of Texas at Austin. He is a member of the Institute of Electrical and Electronics Engineers and the Association for Computing Machinery.

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Jacob Abraham's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Algorithm-Based Fault Tolerance for Matrix Operations (1984) (1290)
An Improved Algorithm for Network Reliability (1979) (394)
FERRARI: A Flexible Software-Based Fault and Error Injection System (1995) (391)
Addressing failures in exascale computing (2014) (386)
Test Generation for Microprocessors (1980) (386)
Fault-tolerant computing : theory and techniques (1986) (292)
FERRARI: a tool for the validation of system dependability properties (1992) (275)
Fault-Tolerant FFT Networks (1988) (273)
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures (1986) (262)
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection (1999) (245)
Quantitative evaluation of soft error injection techniques for robust system design (2013) (204)
Functional Testing of Microprocessors (1984) (201)
Efficient Algorithms for Testing Semiconductor Random-Access Memories (1978) (196)
Load Balancing in Distributed Systems (1982) (180)
Native mode functional test generation for processors with applications to self test and design validation (1998) (173)
CRIS: A test cultivation program for sequential VLSI circuits (1992) (171)
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays (1990) (167)
Fault and error models for VLSI (1986) (165)
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor (1990) (146)
A comparison of Dadda and Wallace multiplier delays (2003) (140)
Abstraction Techniques for Validation Coverage Analysis and Test Generation (1998) (124)
Fault Tolerance Techniques for Systolic Arrays (1987) (103)
Fault-based automatic test generator for linear analog circuits (1993) (100)
Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems (1986) (89)
Property Checking via Structural Analysis (2002) (88)
A novel functional test generation method for processors using commercial ATPG (1997) (84)
CEDA: control-flow error detection through assertions (2006) (81)
Analog Testing with Time Response Parameters (1996) (81)
ACCE: Automatic correction of control-flow errors (2007) (80)
TESTING OF SEMICONDUCTOR RANDOM ACCESS MEMORIES. (1977) (80)
On correlating structural tests with functional tests for speed binning of high performance design (2004) (80)
Automatic test pattern generation for crosstalk glitches in digital circuits (1998) (78)
Design of Test Pattern Generators for Built-In Test (1984) (75)
On Combining Formal and Informal Verification (1997) (75)
An easily computed functional level testability measure (1989) (74)
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks (1974) (73)
Automatic test knowledge extraction from VHDL (ATKET) (1992) (69)
Hierarchical fault modeling for analog and mixed-signal circuits (1992) (68)
CLEAR: Cross-layer exploration for architecting resilience: Combining hardware and software techniques to tolerate soft errors in processor cores (2016) (66)
Synthesis of delay fault testable combinational logic (1989) (65)
A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits (1985) (65)
Test compaction for sequential circuits (1992) (64)
Characterization and Testing of Physical Failures in MOS Logic Circuits (1984) (63)
Iterative simulation-based Genetics + Deterministic Techniques = Complete AtPG (1994) (61)
Probabilistic verification of Boolean functions (1992) (60)
On-chip delay measurement for silicon debug (2004) (59)
A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS (2017) (58)
FAULT CHARACTERIZATION OF VLSI MOS CIRCUITS. (1982) (58)
VLSI logic and fault simulation on general-purpose parallel computers (1993) (57)
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor (2006) (56)
VIPER: An Efficient Vigorously Sensitizable Path Extractor (1993) (55)
A signature analyzer for analog and mixed-signal circuits (1994) (54)
CEDA: Control-Flow Error Detection Using Assertions (2011) (52)
Small-Delay Defect Detection in the Presence of Process Variations (2007) (51)
Complex gate implementations for quantum dot cellular automata (2004) (51)
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors (1995) (50)
Design of Testable CMOS Logic Circuits Under Arbitrary Delays (1985) (50)
Test generation for gigahertz processors using an automatic functional constraint extractor (1999) (50)
Evaluation of integrated system-level checks for on-line error detection (1996) (50)
Fault-Tolerant Matrix Operations On Multiple Processor Systems Using Weighted Checksums (1984) (50)
Load Redistribution Under Failure in Distributed Systems (1983) (49)
Compiler-assisted static checkpoint insertion (1992) (48)
CHEETA: Composition of hierarchical sequential tests using ATKET (1993) (48)
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation (2000) (48)
Automated mapping of pre-computed module-level test sequences to processor instructions (2005) (47)
Compaction of ATPG-generated test sequences for sequential circuits (1988) (46)
Built-In Tests for VLSI Finite-State Machines (1984) (46)
Fault-Tolerant Systems For The Computation Of Eigenvalues And Singular Values (1986) (45)
IBDDs: an efficient functional representation for digital circuits (1992) (44)
Delay fault testing and silicon debug using scan chains (2004) (44)
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor (1988) (44)
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms (1996) (43)
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems (2007) (43)
DCIATP-an iterative analog circuit test generation program for generating DC single pattern tests (1988) (43)
On-chip Programmable Capture for Accurate Path Delay Test and Characterization (2008) (43)
Fault simulation in a distributed environment (1988) (43)
Probabilistic design verification (1991) (43)
DRAFTS: Discretized Analog Circuit Fault Simulator (1993) (43)
Test Generation for Programmable Logic Arrays (1982) (40)
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions (1997) (40)
General linear codes for fault-tolerant matrix operations on processor arrays (1988) (40)
Fault-secure algorithms for multiple-processor systems (1984) (40)
Concurrent error detection in highly structured logic arrays (1984) (40)
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors (2007) (39)
A unified framework for design validation and manufacturing test (1996) (39)
Prediction of analog performance parameters using oscillation based test (2004) (39)
Forward Recovery Using Checkpointing in Parallel Systems (1990) (39)
Fault simulation of linear analog circuits (1993) (39)
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems (2011) (38)
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator (1985) (38)
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling (1991) (38)
Physical design of testable VLSI: techniques and experiments (1989) (38)
High level test generation using data flow descriptions (1990) (36)
A novel test generation approach for parametric faults in linear analog circuits (1996) (36)
Speed up of test generation using high-level primitives (1990) (36)
Quadruple Time Redundancy Adders (2003) (36)
A scheme for on-chip timing characterization (2006) (36)
A low-cost concurrent error detection technique for processor control logic (2008) (35)
Signature analysis for analog and mixed-signal circuit test response compaction (1998) (34)
BiCMOS fault models: is stuck-at adequate? (1990) (34)
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits (2006) (34)
Cache Design for Low Power and High Yield (2008) (34)
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations (1987) (34)
Reuse of addressable system bus for SOC testing (2001) (34)
Subband filtering for time and frequency analysis of mixed-signal circuit testing (2004) (33)
Generating Tests for Physical Failures in MOS Logic Circuits (1983) (33)
Low-Cost Comparison and Diagnosis of Large Remotely Located Files (1986) (33)
Hierarchical fault modeling for linear analog circuits (1996) (33)
A high throughput FFT processor with no multipliers (2009) (33)
Memory System Design for Tolerating Single Event Upsets (1983) (32)
Implementing Forward Recovery Using Checkpoints in Distributed Systems (1992) (32)
TEST GENERATION FOR ARITHMETIC UNITS BY GRAPH LABELLING. (1987) (31)
Verifying Properties Using Sequential ATPG (2002) (31)
Native mode functional self-test generation for Systems-on-Chip (2002) (30)
A study of faulty signatures using a matrix formulation (1990) (29)
TOTALLY SELF-CHECKING MOS CIRCUITS UNDER REALISTIC PHYSICAL FAILURES. (1984) (29)
A comprehensive signature analysis scheme for oscillation-test (2003) (28)
Validating PowerPC Microprocessor Custom Memories (2000) (28)
Design of Testable Structures Defined by Simple Loops (1981) (28)
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions (2006) (28)
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors (2008) (28)
FACTOR: a hierarchical methodology for functional test generation and testability analysis (2002) (27)
Verification of transient response of linear analog circuits (1995) (27)
Quadruple time redundancy adders [error correcting adder] (2003) (27)
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits (1988) (26)
CONCURRENT FAULT DIAGNOSIS IN MULTIPLE PROCESSOR SYSTEMS. (1986) (26)
Performance/Availability Model of Shared Resource Multiprocessors (1980) (26)
Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection (1990) (26)
AMBIANT: automatic generation of behavioral modifications for testability (1993) (26)
Designing for concurrent error detection in VLSI: application to a microprogram control unit (1987) (26)
Functional verification of the Equator MAP1000 microprocessor (1999) (26)
Structured Functional Level Test Generation Using Binary Decision Diagrams (1986) (26)
Built-In Test of RF Mixers Using RF Amplitude Detectors (2007) (25)
Fault Tolerance Techniques For Highly Parallel Signal Processing Architectures (1986) (25)
Hierarchical multi-level fault simulation of large systems (1990) (25)
DESIGN OF PLAS WITH CONCURRENT ERROR DETECTION. (1982) (25)
Portable parallel logic and fault simulation (1989) (24)
Program slicing for hierarchical test generation (2002) (24)
A Numerical Technique for the Hierarchical Evaluation of Large, Closed Fault-Tolerant Systems (1992) (24)
Transistor-Level Test Generation for Physical Failures in CMOS Circuits (1986) (24)
Quasi-oscillation based test for improved prediction of analog performance parameters (2004) (23)
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages (2003) (23)
Characterization of Standard Cells for Intra-Cell Mismatch Variations (2009) (23)
A METHODOLOGY FOR FUNCTIONAL LEVEL TESTING OF MICROPROCESSORS (1995) (22)
An efficient filter-based approach for combinational verification (1999) (22)
Functional abstraction of logic gates for switch-level simulation (1991) (22)
FAUST: An MOS Fault Simulator with Timing Information (1986) (22)
Formal verification using bounded model checking: SAT versus sequential ATPG engines (2003) (21)
EMAX - An automatic extractor of high-level error models (1993) (21)
Critical path identification and delay tests of dynamic circuits (1999) (21)
Program slicing for ATPG-based property checking (2004) (21)
Parallel Loopback Test of Mixed-Signal Circuits (2008) (21)
Testability driven statistical path selection (2011) (20)
Transistor level synthesis for static CMOS combinational circuits (1999) (20)
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model (1991) (20)
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model (2007) (20)
On-line error detecting constant delay adder (2003) (20)
Sequential Redundancy Identification Using Verification Techniques (1992) (20)
FAULT COLLAPSING TECHNIQUES FOR MOS VLSI CIRCUITS. (1986) (20)
Test generation for digital systems (1986) (19)
TESTING OF MOS VLSI CIRCUITS. (1985) (19)
Jitter decomposition by time lag correlation (2006) (19)
Test considerations for BiCMOS logic families (1991) (19)
Efficient soft error vulnerability estimation of complex designs (2015) (19)
LBW COST SCEEMES FOR FAULT TOLEEANCE IN MATRIX OPERATIONS WITH PROCESSOR ARRAYS (1982) (19)
DESIGN OF A MICROPROGRAM CONTROL UNIT WITH CONCURRENT ERROR DETECTION. (1983) (19)
Budget-Dependent Control-Flow Error Detection (2008) (19)
Efficient multisine testing of analog circuits (1995) (19)
A unified approach for fault simulation of linear mixed-signal circuits (1996) (19)
Critical Path Selection for Delay Test Considering Coupling Noise (2008) (19)
Efficient loop-back testing of on-chip ADCs and DACs (2003) (18)
Test generation for crosstalk effects in VLSI circuits (1996) (18)
Efficient Model Checking of Hardware Using Conditioned Slicing (2005) (18)
Fault simulation of linear analog circuits (1993) (18)
Verifying properties using sequential ATPG [IC design] (2002) (18)
Concurrent error detection in VLSI interconnection networks (1983) (18)
Improved verification of hardware designs through antecedent conditioned slicing (2007) (18)
Impact of behavioral modifications for testability (1994) (18)
On the C-Testability of Generalized Counters (1987) (17)
Design of Systems with Concurrent Error Detection Using Software Redundancy (1986) (17)
An aging-aware flip-flop design based on accurate, run-time failure prediction (2012) (17)
Average Interconnection Length and Interconnection Distribution Based on Rent's Rule (1989) (17)
A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory (2012) (17)
Testability-Driven Statistical Path Selection (2012) (17)
Verification of processor microarchitectures (1999) (17)
Tri-scan: a novel DFT technique for CMOS path delay fault testing (2004) (17)
Characterization and testing of microelectromechnical accelerometers (2008) (17)
TEST GENERATION FOR GENERAL MICROPROCESSOR ARCHITECTURES. (1979) (16)
Mixed-level sequential test generation using a nine-valued relaxation algorithm (1990) (16)
An efficient linearity test for on-chip high speed ADC and DAC using loop-back (2004) (16)
Automatic Generation of Behavioral Models from Switch-Level Descriptions (1989) (16)
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques (2001) (15)
Using write back cache to improve performance of multi-user multiprocessors (1982) (15)
SNEL: a switch-level simulator using multiple levels of functional abstraction (1990) (15)
KNOWLEDGE BASED TEST GENERATION FOR VLSI CIRCUITS. (1987) (15)
Jitter Decomposition in High-Speed Communication Systems (2008) (15)
Design and Development Paradigm for Industrial Formal Verification CAD Tools (2001) (15)
A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS (2016) (15)
A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks (1975) (14)
Performance characterization of mixed-signal circuits using a ternary signal representation (2004) (14)
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) (2017) (14)
Automatic verification of implementations of large circuits against HDL specifications (1997) (14)
False timing path identification using ATPG techniques and delay-based information (2002) (14)
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits (2011) (14)
Synthesis of Native Mode Self-Test Programs (1998) (14)
A comprehensive TDM comparator scheme for effective analysis of oscillation-based test (2000) (14)
PRACTICAL MICROPROCESSOR TESTING: OPEN AND CLOSED LOOP APPROACHES. (1981) (13)
Distributed Control of Computer Systems (1986) (13)
Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications (2007) (13)
A Novel Approach to Accurate Timing Verification Using RTL Descriptions (1989) (13)
Efficient parallel algorithms for processor arrays (1982) (13)
Delay Test Techniques For Boundary Scan Based Archictures (1992) (13)
NCUBE: an automatic test generation program for iterative logic arrays (1988) (13)
Simulation on a Network of Workstations * (2004) (13)
Extraction based verification method for off the shelf integrated circuits (2009) (13)
Test data compression and test time reduction using an embedded microprocessor (2003) (13)
WRAP: AN ALGORITHM FOR HIERARCHICAL COMPRESSION OF FAULT SIMULATION PRIMITIVES. (1986) (13)
An area efficient on-chip static IR drop detector/evaluator (2009) (13)
The economics of scan design (1989) (13)
Predicting mixed-signal dynamic performance using optimised signature-based alternate test (2007) (13)
A novel methodology for hierarchical test generation using functional constraint composition (2000) (12)
TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS. (1985) (12)
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator (2011) (12)
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories (2013) (12)
Efficient algorithmic circuit verification using indexed BDDs (1994) (12)
Performance and functional verification of microprocessors (2000) (12)
A low latency and low power dynamic Carry Save Adder (2004) (12)
Causality based generation of directed test cases (2000) (12)
High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms (1991) (12)
In-depth soft error vulnerability analysis using synthetic benchmarks (2015) (12)
Architectural performance verification: PowerPC processors (1994) (12)
Cache Organization for Embeded Processors: CAM-vs-SRAM (2006) (11)
Real-time checking of linear control systems using analog checksums (2013) (11)
Subband filtering scheme for analog and mixed-signal circuit testing (1999) (11)
Derivation of signal flow for switch-level simulation (1990) (11)
C-TESTABILITY FOR GENERALIZED TREE STRUCTURES WITH APPLICATIONS TO WALLACE TREES AND OTHER CIRCUITS. (1986) (11)
A D&T Roundtable: Online Test (1999) (11)
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states (2016) (11)
A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems (1986) (11)
Hierarchical test generation for systems on a chip (2000) (11)
Sequential equivalence checking between system level and RTL descriptions (2008) (11)
High level hierarchical fault simulation techniques (1985) (11)
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA (2000) (11)
Dynamic Trace Signal Selection for Post-Silicon Validation (2013) (10)
MUSTARD: A Coupled, Stochastic-Deterministic, Discrete-Continuous Technique for Predicting the Impact of Random Telegraph Noise on SRAMs and DRAMs (2011) (10)
MIXER: Mixed-signal fault simulator (1993) (10)
AnImproved Algorithm forNetwork Reliability (1979) (10)
Post-Silicon Timing Validation Method Using Path Delay Measurements (2011) (10)
EAGLE: A regression model for fault coverage estimation using a simulation based metric (2014) (10)
LOGIC FUNCTION EXTRACTION FOR NMOS CIRCUITS. (1982) (10)
Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes (1996) (10)
Functional test generation for hard to detect stuck-at faults using RTL model checking (2012) (10)
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages (1996) (10)
USE OF HIGH LEVEL DESCRIPTIONS FOR SPEEDUP OF FAULT SIMULATION. (1987) (10)
Efficient and product-representative timing model validation (2011) (10)
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters (2006) (10)
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits (2009) (10)
Verification of Delta-Sigma converters using adaptive regression modeling (2000) (10)
Automatic Assertion Generation for Simulation, Formal Verification and Emulation (2017) (10)
DESIGN OF TOTALLY SELF-CHECKING EMBEDDED CHECKERS. (1984) (10)
Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems (1992) (10)
Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors (2006) (10)
Efficient variable ordering and partial representation algorithm (1995) (10)
A new scheme to compute variable orders for binary decision diagrams (1994) (10)
Automatic validation test generation using extracted control models (2000) (9)
Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems (2012) (9)
Critical Path Selection for Delay Testing Considering Coupling Noise (2009) (9)
Dynamical Systems Theory: Application to Pedagogy (2003) (9)
EFFICIENT CONCURRENT ERROR DETECTION IN PLAS AND ROMS. (1985) (9)
COMPLEXITY OF ACCURATE LOGIC SIMULATION. (1987) (9)
Rethinking error injection for effective resilience (2014) (9)
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model (2011) (9)
DSP-based statistical self test of on-chip converters (2003) (9)
Formal verification of a system-on-chip using computation slicing (2004) (9)
TESTABLE CMOS LOGIC CIRCUITS UNDER DYNAMIC BEHAVIOR. (1984) (9)
A Framework for Distributed VLSI Simulation on a Network of Workstations (1992) (9)
Recursive Path Selection for Delay Fault Testing (2009) (9)
Toward reliable SRAM-based device identification (2010) (9)
A framework for low overhead hardware based runtime control flow error detection and recovery (2013) (9)
FALCON: Rapid statistical fault coverage estimation for complex designs (2012) (8)
Verification of circuits described in VHDL through extraction of design intent (1994) (8)
Design and evaluation tools for fault-tolerant systems (1987) (8)
Path criticality computation in parameterized statistical timing analysis (2012) (8)
Adaptive Design for Performance-Optimized Robustness (2006) (8)
A comprehensive fault model for deep submicron digital circuits (2002) (8)
On-Chip Delay Measurement Based Response Analysis for Timing Characterization (2010) (8)
Improved methods of simulating RLC coupled and uncoupled transmission lines based on the method of characteristics (1988) (8)
FAULT-TOLERANT ALGORITHMS AND THEIR APPLICATION TO SOLVING LAPLACE EQUATIONS. (1984) (8)
Delay defect diagnosis methodology using path delay measurements (2011) (8)
Concurrent Path Selection Algorithm in Statistical Timing Analysis (2013) (8)
Effects of multi-cycle sensitization on delay tests (2003) (8)
Analytical model for the impact of multiple input switching noise on timing (2008) (8)
Optimal BIST using an embedded microprocessor (2002) (8)
An oscillation-based test structure for timing information extraction (2012) (8)
Generation of testable designs from behavioral descriptions using high level synthesis tools (1993) (8)
A Modular Robust Binary Tree (1995) (7)
Self-Test for Microprocessors (1985) (7)
Connecting different worlds — Technology abstraction for reliability-aware design and Test (2014) (7)
Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer (2021) (7)
Techniques for automatic test knowledge extraction from compiled circuits (1990) (7)
A novel hierarchical test generation method for processors (1997) (7)
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation (2001) (7)
Efficient combinational verification using BDDs and a hash table (1997) (7)
Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding (2019) (7)
Automatic structural abstraction techniques for enhanced verification (2002) (7)
High-level design validation and test (1998) (7)
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate (2010) (7)
A Random Jitter RMS Estimation Technique for BIST Applications (2009) (7)
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL (2009) (7)
Reliability analysis of digital systems protected by massive redundancy. (1974) (7)
MOS FAULT SIMULATOR WITH TIMING INFORMATION. (1985) (7)
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC/sup TM/ microprocessor (2000) (7)
Generation and evaluation of current and logic tests for switch-level sequential circuits (1992) (7)
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs (2007) (7)
Functional Level Test Generation for Complex Digital Systems (1981) (7)
LFSR-based BIST for analog circuits using slope detection (2004) (7)
Distributed mixed level logic and fault simulation on the Pentium/sup (R/)Pro microprocessor (1996) (7)
Timing verification and delay test generation for hierarchical designs (2001) (7)
A timing methodology considering within-die clock skew variations (2008) (7)
On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector (2009) (7)
Benchmarking Parallel Processing Platforms: An Applications Perspective (1993) (7)
Fast evaluation of test vector sets using a simulation-based statistical metric (2014) (7)
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor (2005) (7)
Full chip false timing path identification: applications to the PowerPC/sup TM/ microprocessors (2001) (7)
Static program transformations for efficient software model checking (2004) (7)
TIDBITS: speedup via time-delay bit-slicing in ALU design for VLSI technology (1985) (7)
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA (2012) (7)
A Built-In Self-Test scheme for DDR memory output timing test and measurement (2012) (6)
Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications (2011) (6)
Characterization of sequential cells for constraint sensitivities (2009) (6)
Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems (2013) (6)
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor (2020) (6)
Interlock schemes for micropipelines: application to a self-timed rebound sorter (1991) (6)
Detecting false timing paths: experiments on PowerPC microprocessors (1999) (6)
Test generation for resistive opens in CMOS (2002) (6)
MURPHY: A LOGIC SIMULATOR FOR MOS VLSI CIRCUITS. (1983) (6)
Enhanced algorithm of combining trace and scan signals in post-silicon validation (2013) (6)
A novel low power 11-bit hybrid ADC using flash and delay line architectures (2014) (6)
Power prediction of embedded scalar and vector processor: Challenges and solutions (2017) (6)
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing (1988) (6)
A high-level approach to test generation (1993) (6)
Testing and debugging delay faults in dynamic circuits (2005) (6)
Model Checking of Security Protocols with Pre-configuration (2003) (6)
Adaptive SRAM memory for low power and high yield (2008) (6)
A 6-bit 300-MS/s 2.7mW ADC based on linear voltage controlled delay line (2008) (6)
PERFORMANCE MODEL FOR CONCURRENT HIERARCHICAL FAULT SIMULATION. (1986) (6)
Functionally valid gate-level peak power estimation for processors (2009) (5)
Safety Design of a Convolutional Neural Network Accelerator with Error Localization and Correction (2019) (5)
A new asynchronous multiplier using Enable/Disable CMOS Differential Logic (1994) (5)
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits (2008) (5)
Vector based Analog to Digital Converter sequential testing methodology to minimize ATE memory and analysis requirements (2009) (5)
At-speed Test of High-Speed DUT Using Built-Off Test Interface (2010) (5)
Design and evaluation of automated checks for signal processing applications (1996) (5)
Design of a scalable parallel switch-level simulator for VLSI (1990) (5)
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead (2019) (5)
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems (2008) (5)
Adaptive interpretation as a means of exploiting complex instruction sets (1983) (5)
HDL Program Slicing to Reduce Bounded Model Checking Search Overhead (2006) (5)
Distributed Computing Grids–Safety and Security (2007) (5)
A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers (2019) (5)
On efficient generation of instruction sequences to test for delay defects in a processor (2008) (5)
Jitter decomposition in ring oscillators (2006) (5)
Automatic classification of node types in switch-level descriptions (1990) (5)
Parallel switch-level simulation for VLSI (1991) (5)
Multitone digital signal based test for RF receivers (2010) (5)
Concurrent Error Detection In Vlsi Processor Arrays (1988) (5)
HARDWARE ACCELERATION ALONE WILL NOT MAKE FAULT GRADING ULSI A REALITY (1991) (5)
A language formalism for verification of PowerPC/sup TM/ custom memories using compositions of abstract specifications (2001) (5)
Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM (2010) (5)
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation (2002) (5)
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL (2008) (5)
Companson and Diagnosis of Large Replicated Files (1987) (5)
Hybrid BiST solution for Analog to Digital Converters with low-cost Automatic Test Equipment compatibility (2009) (5)
Case study of ATPG-based bounded model checking: verifying USB2.0 IP core (2005) (5)
Automated verification of temporal properties specified as state machines in VHDL (1995) (5)
On the Design of Fault-Tolerant Systolic Arrays with Linear Cells (1986) (5)
On Computing Criticality in Refactored Timing Graphs (2012) (4)
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control (2010) (4)
FzCRITIC-a functional timing verifier using a novel fuzzy delay model (1999) (4)
Test trade-offs for different dynamic testing techniques for analog and mixed-signal circuits (1994) (4)
High level static analysis of system descriptions for taming verification complexity (2007) (4)
Approaches to Circuit Level Design for Testability (1986) (4)
To model check or not to model check (1998) (4)
Environment modeling and efficient state reachability checking (1999) (4)
ESIFT: Efficient System for Error Injection (2018) (4)
Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method (2006) (4)
Efficient Microprocessor Verification using Antecedent Conditioned Slicing (2007) (4)
An efficient 3-bit-scan multiplier without overlapping bits, and its 64/spl times/64 bit implementation (2002) (4)
Phase-Aware Multitone Digital Signal Based Test for RF Receivers (2012) (4)
DESIGN AND EVALUATION OF EXECUTABLE ASSERTIONS FOR CONCURRENT ERROR DETECTION. (1987) (4)
Estimating path delay distribution considering coupling noise (2007) (4)
Statistical characterization for timing sign-off: from silicon to design and back to silicon (2009) (4)
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA (2009) (4)
Challenges in fault detection (1995) (4)
Techniques for efficiently implementing totally self-checking checkers in MOS te (1987) (4)
An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems (1997) (4)
A novel solution for chip-level functional timing verification (1997) (4)
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights (2017) (4)
Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources (2012) (4)
A reconfigurable parallel signature analyzer for concurrent error correction in DRAM (1990) (4)
Checking nested properties using bounded model checking and sequential ATPG (2006) (4)
Control Flow Checking in Object-Based Distributed Systems (1993) (4)
Closed-loop Built in Self Test for PLL production testing with minimal tester resources (2009) (4)
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection (2010) (4)
Raft: A Novel Program For Rapid-fire Test And Diagnosis Of Digital Logic For Marginal Delays And Delay Faults (1994) (4)
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management (2012) (4)
CLEAR: Cross-Layer Exploration for Architecting Resilience (2017) (4)
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces (2010) (3)
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm (2002) (3)
Incorporating Test Technology into an Undergraduate Curriculum (1983) (3)
Validation of PowerPC/sup TM/ custom memories using symbolic simulation (2000) (3)
Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction (2013) (3)
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP (2020) (3)
System accuracy estimation of SRAM-based device authentication (2011) (3)
The Testability of Generalized Counters Under Multiple Faulty Cells (1990) (3)
Designing nonlinearity characterization for mixed-signal circuits in system-on-chip (2015) (3)
Selective-run built-in self-test using an embedded processor (2002) (3)
Effective Control Flow Integrity Checks for Intrusion Detection (2018) (3)
The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits (1992) (3)
Is state mapping essential for equivalence checking custom memories in scan-based designs? (2002) (3)
PLL lock time prediction and parametric testing by lock waveform characterization (2010) (3)
Conditioned HDL Slicing A way to Speed-up Formal Verification (2006) (3)
Design of Shifting and Permutation Units using LSDL Circuit Family (2006) (3)
A mixed-signal BIST scheme with time-division multiplexing (TDM) comparator and counters (2000) (3)
Simulation Study on the Optimization of Photon Energy Delivered to the Prefrontal Cortex in Low-Level-Light Therapy Using Red to Near-Infrared Light (2021) (3)
Eecient Variable Ordering and Partial Representation Algorithms (1995) (3)
Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits (2014) (3)
Cross-Layer Control Adaptation for Autonomous System Resilience (2018) (3)
Using verification technology for validation coverage analysis and test generation (1998) (3)
Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players? (2014) (3)
Improving witness search using orders on states (1999) (3)
Error Resilient Real-Time State Variable Systems for Signal Processing and Control (2014) (3)
Built-in Self Test of RF Subsystems with Integrated Detectors (2012) (3)
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor (2021) (2)
The future of fault tolerant computing (2015) (2)
Adding capability checks enhances error detection and isolation in object-based systems (1993) (2)
Taming the Complexity of STE-based Design Verification Using Program Slicing (2006) (2)
On Design Validation Using Verification Technology (1999) (2)
Real-time correction of dc servo motor and controller failures using analog checksums (2014) (2)
Error detection in 2-D Discrete Wavelet lifting transforms (2009) (2)
Delay Constrained Register Transfer Level Dynamic Power Estimation (2006) (2)
A novel fractional-N PLL based on a simple reference multiplier (2011) (2)
Harmonic distortion correction for 8-bit delay line ADC using gray code (2014) (2)
TOTALLY SELF-CHECKING CMOS CIRCUITS USING A HYBRID REALIZATION. (1985) (2)
Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors (2012) (2)
A memory distribution mechanism for object oriented applications (1995) (2)
On more efficient combinational ATPG using functional learning (1996) (2)
On-chip source synchronous interface timing test scheme with calibration (2012) (2)
Impact of behavioral learning on the compilation of sequential circuit tests (1993) (2)
Accurate characterization of error propagation in a highly parallel architecture (1990) (2)
Transistor level synthesis and hierarchical timing optimization for cmos combinational circuits (1999) (2)
Test generation for hybrid iterative logic arrays (1990) (2)
BiCMOS logic testing (1994) (2)
DESIGN FOR TESTABILITY. (1983) (2)
The Evolution of Fault Tolerant Computing at the University of Illinois (1987) (2)
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip (2009) (2)
Estimation of maximum application-level power supply noise (2010) (2)
Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor (1993) (2)
Graphic-theoretic bounds for on-line checks in multiple processor systems (1986) (2)
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits (2017) (2)
Probabilistic model for the evaluation of fault-tolerant multiprocessor systems using concurrent error detection (1990) (2)
A multi-band low noise amplifier with strong immunity to interferers (2017) (2)
Lightweight guided random simulation (1998) (2)
A hierarchical approach for power reduction in VLSI chips (1996) (2)
Checksum based error detection in linearized representations of non linear control systems (2016) (2)
Reducing verification overhead with RTL slicing (2007) (2)
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits (2008) (2)
Balancing virtual and physical prototyping across a multi-course VLSI/embedded-systems/SoC design curriculum (2009) (2)
Abstraction of data path registers for multilevel verification of large circuits (1994) (2)
An adder using charge sharing and its application in DRAMs (2000) (1)
Optimization for Behavioral/RTL Simulation (1993) (1)
Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change (2013) (1)
Single Trojan injection model generation and detection (2016) (1)
Spectral Leakage-Driven Loopback Scheme for Prediction of Mixed-Signal Circuit Specifications (2019) (1)
Structured test generation techniques for analog and mixed signal circuits (1996) (1)
Low-cost assertion-based fault tolerance in hardware and software (2008) (1)
ALGORITHM FOR THE ACCURATE RELIABILITY EVALUATION OF TMR NETWORKS. (1973) (1)
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level (2009) (1)
On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test (2011) (1)
Cross-layer resilience: are high-level techniques always better? (2016) (1)
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor (2013) (1)
Quality Aware Error Detection in 2-D Separable Linear Transformation (2016) (1)
Towards the complete elimination of gate/switch level simulations (2004) (1)
Efficient testing techniques for bit and digit-serial arrays (1991) (1)
A delay measurement method using a shrinking clock signal (2010) (1)
Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor (2020) (1)
Calibration-enabled scalable built-in current sensor compatible with very low cost ATE (2010) (1)
Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits (1993) (1)
Performance Analysis of Numerical Problems on a Loosely Coupled System (1987) (1)
Formal checking of properties in complex systems using abstractions (1999) (1)
Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits (2014) (1)
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification (2015) (1)
“Manufacturing test of systems-on-a-chip (SoCs)” (2011) (1)
Design of a Safe Convolutional Neural Network Accelerator (2019) (1)
Fault grading of large digital systems (1990) (1)
HAT: A HEURISTIC ADVISER FOR TESTABILITY. (1985) (1)
From dependable computing systems to computing for integrated dependable systems? (1998) (1)
Zeno: A Scalable Capability-Based Secure Architecture (2022) (1)
Hierarchical specification of system behavior (1997) (1)
Testing and Fault Diagnosis of Time-Interleaved S? Modulators Using Checksums (2012) (1)
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table (2002) (1)
Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing (2012) (1)
Controllability of Static CMOS Circuits for Timing Characterization (2008) (1)
Communication space reduction for formal verification of secure authentication protocols (2001) (1)
Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design (2012) (1)
Automatic test generation for linear digital systems with bi-level search using matrix transform methods (1992) (1)
BUILT-IN TESTS FOR ARBITRARILY STRUCTURED VLSI CARRY-LOOKAHEAD ADDERS. (1983) (1)
Average interconnection length and interconnection distribution for rectangular arrays (1989) (1)
What's the next 'big thing' in simulation-based verification? (2003) (1)
Effective techniques for processor validation and test (1999) (1)
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000 (2009) (1)
Research in Reliable VLSI Architectures at the University of Illinois (1986) (1)
Special session 12B: Panel post-silicon validation & test in huge variance era (2013) (1)
Recent advances in algorithm-based fault tolerance (1994) (1)
Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults (2013) (1)
On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs (2013) (1)
ARCHITECTURE AND SOFTWARE ENHANCEMENTS FOR CONCURRENT DETECTION OF COMPUTER SYSTEM FAILURES. (1985) (1)
Memory Distribution: Techniques and Practice for CAD Applications (1998) (1)
An efficient critical path tracing algorithm for sequential circuits (1994) (1)
Test and Debug in Deep-Submicron Technologies (2004) (1)
Position Statement: Increasing Test Coverage in a VLSI Design Course (1999) (0)
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control (2015) (0)
2010 International Symposium on Electronic System Design ISED 2010 (2010) (0)
Cache design for low power and yield enhancement (2008) (0)
Scan Design and AC Test (2004) (0)
Keynote Speech 1: New Paths for Test (2007) (0)
Design and evaluation of fault tolerance techniques for highly parallel architectures (1991) (0)
A novel algorithm for sparse FFT pruning and its applications to OFDMA technology (2014) (0)
FAULT COVERAGE OF TEST PROGRAMS FOR A MICROPROCESSOR. (2017) (0)
Special Technology Area Review on Computer Aided Design (1993) (0)
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below (2016) (0)
Advances in VLSI-Testing (1989) (0)
Native-Mode Self Test for Embedded Systems on a Chip (2007) (0)
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? (2001) (0)
Frontiers of Computing Systems Research (1992) (0)
ETS 2008 BEST PAPER (2008) (0)
Functional Self-Test Generation for Superscalar Microprocessors (2007) (0)
Recovery Techniques for Real Time Electronic Systems (1992) (0)
Analog and mixed signal benchmarks: Who needs them? (2001) (0)
Dependable embedded systems special day panel: issues and challenges in dependable embedded systems (2008) (0)
Performance-Optimized Design for Parametric Reliability (2008) (0)
Detecting false timing paths: experiments on PowerPC/sup TM/ microprocessors (1999) (0)
Implications of Technology Trends on System Dependability (2008) (0)
Resilient Reorder Buffer Design for Network-on-Chip (2019) (0)
On-chipProgrammableCaptureforAccuratePathDelayTestand Characterization (2008) (0)
Microprocessor Verification using RT-Level Static Analysis Techniques (2006) (0)
Practical Test and DFT for Next Generation VLSI (1996) (0)
TWO ASPECTS OF HUMAN-CENTRIC EVOLUTIONARY DESIGN SYSTEMS (2006) (0)
Tutorial 3 High-level Design Validation And Test (1998) (0)
A distributed mechanism for memory-intensive computer-aided design problems (1996) (0)
Predicting performance parameters of analog and mixed-signal circuits using built-in and built-off self test (2007) (0)
Scalable solutions to specification and verification of large designs (1999) (0)
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor (2021) (0)
A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement (2012) (0)
Test of phase interpolators in high speed I/Os using a sliding window search (2012) (0)
LOW COST SCHEMES FOR FAULT TOLERANCE IN MATRIX OPEBATIONS WITH PROCESSOR ABBAYS (1995) (0)
T4: Verification (1997) (0)
Session details: Built-in self-test solutions for mixed-signal and RF ICs (2014) (0)
Native-Mode Self TestforEmbeddedSystems onaChip (2007) (0)
Bist-based performance characterization of mixed-signal circuits (2004) (0)
A multi-level hierarchical sequential circuit test generation algorithm (1992) (0)
RELIABILITY hIODELIXG OF NMR NETWORKS (1998) (0)
(Invited) Cross-Layer Resilience: Challenges, Insights, and the Road Ahead (2019) (0)
Test generation and fault simulation techniques for full custom ulsi (1995) (0)
Moore's Law and Beyond: Electronic Design Challenges (2010) (0)
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control? (2009) (0)
Formal verification: current use and future perspectives (2002) (0)
Indirect method for random jitter measurement on SoCs using critical path characterization (2012) (0)
Dynamic Testability Measures for ATPG (1988) (0)
SymposiumonFault-Tolerarv aRs Rs S l Computing (1985) (0)
Analysis of On-Chip Clock Distribution Systems in High Speed Systems (1988) (0)
Microprocessor Testing: Which Technique is Best? (Panel). (1994) (0)
Optimistic execution and checkpoint comparison for error recovery in parallel and distributed systems (1992) (0)
FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping (2019) (0)
Automatic Verification of Arithmetic Circuits using Step-wise Refinement of Term Rewriting Systems (2007) (0)
Robust power gating reactivation by dynamic wakeup sequence throttling (2011) (0)
Formal Verification ATPG Search Engine Emulator (Abstract Only) (2015) (0)
Using static timing analysis and verification engines to generate native-mode tests for small delay defects (2007) (0)
Guest Editorial Special Issue of IEEE Sensors on the 4th IEEE International Workshop on Advances in Sensors and Interfaces 2011 (IWASI 2011) (2012) (0)
Analysis and improvement of testability measure approximation algorithms (1994) (0)
Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters (2020) (0)
A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement (2012) (0)
A rigorous approach to self-checking programming (1986) (0)
Design Validation: Formal Verification vs. Simulation vs. Functional Testing (1996) (0)
Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing (2012) (0)
VLSI Design 2004 Technical Program Committee (2004) (0)
High speed recursion-free CORDIC architecture (2010) (0)
Arbitrary Waveform Generator Response Shaping Method to Enable ADC Linearity Testing on Very Low Cost Automatic Test Equipment (2011) (0)
Panel: Microprocessor Testing: Which Technique Is Best? (1994) (0)
The use of hierarchy in test generation, fault simulation, and testability analysis algorithms (1988) (0)
Workshop on Dependable and Secure Nanocomputing — Call for Contributions — (2007) (0)
Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control (2016) (0)
Resiliency Demands on Next Generation Critical Embedded Systems (2019) (0)
Sequential Redundancy I entificatisn Usin Verification Techni (1992) (0)
Microprocessor Test and Validation: Any New Avenues? (1997) (0)
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors (1991) (0)
USER TESTING OF MICROPROCESSORS. (2017) (0)
An emulation model for sequential ATPG-based bounded model checking (2005) (0)

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