James D. Meindl

Q: What Schools Are Affiliated With James D. Meindl

James D. Meindl is affiliated with the following schools: Rensselaer Polytechnic Institute, University of Notre Dame, Stanford University, Carnegie Mellon University, Georgia Tech

James D. Meindl's AcademicInfluence.com Rankings

James D. Meindl

Engineering

#755

World Rank

#1196

Historical Rank

#314

USA Rank

Electrical Engineering

#177

World Rank

#205

Historical Rank

#80

USA Rank

Applied Physics

#453

World Rank

#471

Historical Rank

#98

USA Rank

engineering Degrees

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Engineering

James D. Meindl's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering University of Notre Dame

Why Is James D. Meindl Influential?

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According to Wikipedia, James Donald Meindl was director of the Joseph M. Pettit Microelectronics Research Center and the Marcus Nanotechnology Research Center and Pettit Chair Professor of Microelectronics at the Georgia Institute of Technology in Atlanta, Georgia. He won the 2006 IEEE Medal of Honor "for pioneering contributions to microelectronics, including low power, biomedical, physical limits and on-chip interconnect networks.”

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James D. Meindl's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration (2002) (758)
The impact of intrinsic device fluctuations on CMOS SRAM cell stability (2001) (715)
Interconnect limits on gigascale integration (GSI) in the 21st century (2001) (516)
Ion-implanted complementary MOS transistors in low-voltage circuits (1972) (420)
Optimal interconnection circuits for VLSI (1985) (393)
Breakdown current density of graphene nanoribbons (2009) (384)
Limits on silicon nanoelectronics for terascale integration. (2001) (337)
Compact physical models for multiwall carbon-nanotube interconnects (2006) (330)
Low power microelectronics: retrospect and prospect (1995) (323)
Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) (2005) (310)
Interconnect Opportunities for Gigascale Integration (2002) (300)
A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation (1998) (290)
Intrinsic MOSFET parameter fluctuations due to random dopant placement (1997) (255)
A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs (2003) (254)
Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems (2007) (250)
Conductance Modeling for Graphene Nanoribbon (GNR) Interconnects (2007) (234)
Compact Physics-Based Circuit Models for Graphene Nanoribbon Interconnects (2009) (231)
A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation (1998) (214)
Ion-sensing devices with silicon nitride and borosilicate glass insulators (1987) (211)
Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks (2000) (187)
A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs (2002) (187)
Beyond Moore's Law: the interconnect era (2003) (182)
Resistivity of Graphene Nanoribbon Interconnects (2009) (182)
A physical alpha-power law MOSFET model (1999) (175)
Carbon nanotube interconnects (2007) (167)
Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems (2008) (161)
Physical Modeling of Temperature Coefficient of Resistance for Single- and Multi-Wall Carbon Nanotube Interconnects (2007) (158)
Theoretical analysis of the CW doppler ultrasonic flowmeter. (1974) (157)
The fundamental limit on binary switching energy for terascale integration (TSI) (2000) (156)
A monolithic capacitive pressure sensor with pulse-period output (1980) (155)
Solid-State Circuits Conference (1969) (154)
Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication (2007) (143)
Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions (2000) (141)
A stochastic wire length distribution for gigascale integration (GSI) (1997) (137)
Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips (2010) (114)
Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertion (2003) (111)
A 3D-IC Technology with Integrated Microchannel Cooling (2008) (108)
A conduction model for semiconductor-grain-boundary-semiconductor barriers in polycrystalline-silicon films (1983) (100)
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation (2008) (99)
Optimization of the Hydrazine‐Water Solution for Anisotropic Etching of Silicon in Integrated Circuit Technology (1975) (99)
A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy (1990) (96)
The Packaging of Implantable Integrated Sensors (1986) (96)
Impact of three-dimensional architectures on interconnects in gigascale integration (2001) (93)
Integrated Interconnect Technologies for 3D Nanoelectronic Systems (2008) (89)
Interconnect Technology and Design for Gigascale Integration (2003) (88)
Monolayer metallic nanotube interconnects: promising candidates for short local interconnects (2005) (82)
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip (2000) (81)
A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) (2001) (80)
A quantitative model of the effect of grain size on the resistivity of polycrystalline silicon resistors (1980) (79)
A minimum total power methodology for projecting limits on CMOS GSI (2000) (79)
Electrical and optical clock distribution networks for gigascale microprocessors (2002) (79)
Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI) (2005) (78)
3D stacking of chips with electrical and microfluidic I/O interconnects (2008) (75)
A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001 (1996) (74)
Characterization and modeling of clock skew with process variations (1999) (73)
Thermal Oxidation of Heavily Phosphorus‐Doped Silicon (1978) (71)
A process for the combined fabrication of ion sensors and CMOS circuits (1988) (70)
Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink (2006) (69)
Performance Benchmarking for Graphene Nanoribbon, Carbon Nanotube, and Cu Interconnects (2008) (68)
Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI) (2003) (67)
Impact of electron-phonon scattering on the performance of carbon nanotube interconnects for GSI (2005) (65)
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) (2001) (65)
Blood flow measurement using the attenuation-compensated volume flowmeter. (1979) (63)
Architecture of the Atlas chip-multiprocessor: dynamically parallelizing irregular applications (1999) (62)
Kinetics of the thermal oxidation of WSi2 (1979) (61)
Gigascale integration: is the sky the limit? (1996) (59)
Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load termination (2003) (56)
Performance limits of CMOS ULSI (1985) (56)
Opportunities for reduced power dissipation using three-dimensional integration (2002) (55)
A circuit-level perspective of the optimum gate oxide thickness (2001) (55)
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution (2001) (55)
A three-dimensional stochastic wire-length distribution for variable separation of strata (2000) (53)
Optimal global interconnects for GSI (2003) (53)
Global interconnect design in a three-dimensional system-on-a-chip (2004) (52)
VMOS: high speed TTL compatible MOS logic (1974) (50)
Chips for advanced computing (1987) (49)
Ultra-large scale integration (1984) (49)
An analytical two-dimensional model for silicon MESFETs (1988) (49)
Performance comparison between carbon nanotube and copper interconnects for GSI (2004) (48)
An experimental and theoretical analysis of double-diffused MOS transistors (1975) (47)
Impact of within-die parameter fluctuations on future maximum clock frequency distributions (2001) (47)
Intsim: a CAD tool for optimization of multilevel interconnect networks (2007) (47)
A monolithic capacitive pressure sensor with pulse-period output (1980) (46)
Prediction of interconnect fan-out distribution using Rent's rule (2000) (44)
Wafer-level microfluidic cooling interconnects for GSI (2005) (44)
A generic system simulator with novel on-chip cache and throughput models for gigascale integration (1998) (44)
Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication (2012) (43)
Process optimization and proximity effect correction for gray scale e-beam lithography (2006) (41)
Heterogeneous architecture models for interconnect-motivated system design (2000) (41)
Interconnecting device opportunities for gigascale integration (GSI) (2001) (40)
Theoretical, practical and analogical limits in ULSI (1983) (40)
A system-level circuit model for multi- and single-chip CPUs (1987) (40)
Some Effects of “Trichloroethylene Oxidation” on the Characteristics of MOS Devices (1975) (40)
An Integrated Circuit-Based Optical Sensor for In Vivo Measurement of Blood Oxygenation (1986) (40)
A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER) (2009) (39)
A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI) (1998) (39)
A monolithic signal processor for a neurophysiological telemetry system (1985) (39)
Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization (2004) (38)
MOSFET scaling limits determined by subthreshold conduction (1989) (38)
Two-dimensional transmit/receive ceramic piezoelectric arrays: Construction and performance (1978) (37)
Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections (2003) (36)
Interconnect limits on gigascale integration (1999) (35)
Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration (2004) (35)
A compact physical via blockage model (2000) (35)
Optimal interconnect circuits for VLSI (1984) (34)
Electrocutaneous stimulation in a reading aid for the blind. (1971) (34)
Dynamic-threshold CMOS SRAM cells for fast, portable applications (2000) (33)
Integrated Electronics for a Reading Aid for the Blind (1969) (33)
Three-dimensional analytical subthreshold models for bulk MOSFETs (1995) (32)
Analysis, Design, and Performance of a Capacitive Pressure Sensor IC (1986) (32)
Fundamental performance limits of MOS integrated circuits (1975) (32)
Interconnect limits on gigascale integration (GSI) (2001) (32)
Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC (1986) (32)
Random MOSFET parameter fluctuation limits to gigascale integration (GSI) (1996) (32)
The teams and the playrs: Japan, the United States, and Western Europe provide striking contrasts in national interests and techniques: Strategies (1983) (31)
MOS electronics for a portable reading aid for the blind (1972) (30)
Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI) (2004) (30)
Special issue on limits of semiconductor technology (2001) (30)
An Acoustic Image Sensor Using a Transmit-Receive Array (1974) (29)
Double jeopardy in the nanoscale court [MOSFET modeling] (2003) (29)
Surface Potential-pH Characteristics in the Theory of the Oxide-Electrolyte Interface (1987) (29)
Device parameter optimization for reduced short channel effects in retrograde doping MOSFET's (1996) (28)
Compact Physical Models for Power Supply Noise and Chip/Package Co-Design of Gigascale Integration (2007) (27)
Implantable Telemetry in Biomedical Research (1984) (27)
Nanoscale metal?oxide?semiconductor field-effect transistors: scaling limits and opportunities (2004) (27)
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule (1998) (27)
Performance Modeling for Carbon Nanotube Interconnects (2009) (27)
Double jeopardy in the nanoscale court (2003) (26)
Poly I/sup 2/L-a high-speed linear-compatible structure (1977) (26)
Power-Spectrum Centroid Detection for Doppler Systems Applications (1980) (26)
Sea-of-leads MEMS I/O interconnects for low-k IC packaging (2006) (25)
Optical transmission of polymer pillars for chip I/O optical interconnections (2004) (25)
Electron Transport Modeling for Junctions of Zigzag and Armchair Graphene Nanoribbons (GNRs) (2008) (25)
An ultrasonic imaging system for realtime cardiac imaging (1974) (24)
Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration (1996) (24)
Short channel models and scaling limits of SOI and bulk MOSFETs (1994) (24)
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems (2007) (24)
High‐resolution scanning electron‐beam annealing of ion‐implanted silicon (1979) (24)
Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs (2005) (23)
Flexible pillars for displacement compensation in optical chip assembly (2006) (23)
Opportunities for Scaling FET's for Gigascale Integration (GSI) (1993) (23)
Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip (1998) (23)
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects (2007) (23)
Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs (2010) (22)
A global interconnect design window for a three-dimensional system-on-a-chip (2001) (22)
Integrated circuits for a bidirectional implantable pulsed Doppler ultrasonic blood flowmeter (1978) (22)
A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs (2002) (22)
Receiving antenna design for miniature receivers (1977) (22)
Epitaxial V-groove bipolar integrated circuit process (1973) (22)
A hierarchical block-based modeling methodology for SoC in GENESYS (2002) (21)
An analytical threshold voltage and subthreshold current model for short-channel MESFETs (1993) (21)
Optimal low power interconnect networks (1996) (21)
Biomedical implantable microelectronics. (1980) (21)
Blood Flow Measurement Using the Attenuation-Compensated Volume Flowmeter (1979) (21)
The impact of stochastic dopant and interconnect distributions on gigascale integration (1997) (21)
Performance Modeling for Carbon Nanotube Interconnects in On-Chip Power Distribution (2007) (21)
A monolithic micropower command receiver (1971) (21)
Microelectronic circuit elements (1977) (21)
Structured epitaxial graphene growth on SiC by selective graphitization using a patterned AlN cap (2010) (21)
Modeling the effect of source/drain junction depth on bulk-MOSFET scaling (2007) (20)
Is interconnect the weak link (1998) (20)
A priori wiring estimations and optimal multilevel wiring networks for portable ULSI systems (1996) (20)
A Digitally Controlled CCD Dynamically Focussed Phased Array (1975) (20)
Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics (2005) (20)
Chip-level waveguide-mirror-pillar optical interconnect structure (2006) (20)
Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC) (2001) (20)
System-on-a-chip global interconnect optimization (2002) (19)
Temperature variable supply voltage for power reduction (2002) (19)
A history of low power electronics: how it began and where it's headed (1997) (18)
Quantum mechanical effects on double-gate MOSFET scaling (2003) (18)
Breakdown walkout in planar p-n junctions (1978) (18)
Invited: Circuit scaling limits for ultra-large-scale integration (1981) (17)
Photopolymer-based diffractive and MMI waveguide couplers (2004) (17)
Physical limits of VLSI dRAM's (1985) (17)
The evolution of monolithic and polylithic interconnect technology (2002) (17)
Compact distributed RLC models for multilevel interconnect networks (1999) (17)
The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors (2007) (17)
On the micro-architectural impact of clock distribution using multiple PLLs (2001) (17)
New IGFET short-channel threshold voltage model (1981) (17)
State-of-the-art in two-dimensional ultrasonic transducer array technology. (1976) (16)
Low cost high density Compliant Wafer Level Package (2000) (16)
Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks (2005) (16)
A monolithic image sensor for a reading aid for the blind (1970) (15)
New methods for whole blood oximetry (2006) (15)
Microelectronics and computers in medicine (1982) (15)
A physical model for the transient response of capacitively loaded distributed RLC interconnects (2002) (15)
Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors (2004) (15)
Quasi-free-space optical coupling between diffraction grating couplers fabricated on independent substrates. (2004) (15)
Effects of random MOSFET parameter fluctuations on total power consumption (1996) (15)
An implantable ion sensor transducer (1981) (15)
Prospects of gigascale integration (GSI) beyond 2003 (1993) (15)
Integrated power controllers and RF data transmitters for totally implantable telemetry. (1979) (15)
Scaling limitations of monolithic polycrystalline-Silicon resistors in VLSI static RAM's and logic (1982) (14)
An IGFET inversion charge model for VLSI systems (1985) (14)
Micropower integrated circuits for an implantable pulsed-doppler ultrasonic blood flowmeter (1975) (14)
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) (2000) (14)
Sea of dual mode polymer pillar I/O interconnections for gigascale integration (2003) (14)
Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors (1978) (14)
Mechanically Flexible Chip-to-Substrate Optical Interconnections Using Optical Pillars (2008) (14)
Performance limits of E/D NMOS VLSI (1980) (14)
Computer Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices (1981) (13)
Exact analysis of the Schmitt trigger oscillator (1984) (13)
A sub- and near-threshold current model for silicon MESFETs (1988) (13)
Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects (1998) (13)
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots (2007) (13)
Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOS FETs (2017) (13)
Optimum chip clock distribution networks (1999) (12)
Input coupling and guided-wave distribution schemes for board-level intra-chip guided-wave optical clock distribution network using volume grating coupler technology (2001) (12)
Analysis and optimization of coplanar RLC lines for GSI global interconnection (2004) (12)
A monolithic power-spectrum centroid detector (1979) (12)
A general-purpose implantable multichannel telemetry system for physiological research. (1979) (12)
Physical limits on gigascale integration (1996) (12)
Optimal System Design for an Implantable CW Doppler Ultrasonic Flowmeter (1978) (12)
What is graphene? (2009) (12)
Three-region analytical models for MESFETs in low-voltage digital circuits (1991) (11)
Minimum supply voltage for bulk Si CMOS GSI (1998) (11)
Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance (1999) (11)
A high voltage MOS switch (1975) (11)
Integrated Circuit Implantable Telemetry Systems (1983) (11)
One-phase CCD: a new approach to charge-coupled device clocking (1972) (11)
Small‐organ dynamic imaging system (1980) (11)
Performance improvement using on-board wires for on-chip interconnects (2000) (11)
Dynamics and Limitations of Blood/Muscle Interface Detection Using Doppler Power Returns (1980) (11)
Stochastic interconnect network fan-out distribution using Rent's rule (1998) (11)
Ultrasonic Imaging Using Two-Dimensional Transducer Arrays (1976) (11)
Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication (2005) (11)
Optimal System Design of the Pulsed Doppler Ultrasonic Blood Flowmeter (1973) (11)
Nanoelectronics in retrospect, prospect and principle (2010) (10)
An optical clock distribution network for gigascale integration (2000) (10)
Direct calibration of a totally implantable pulsed Doppler ultrasonic blood flowmeter. (1977) (10)
Low Power Linear Circuits (1966) (10)
Modeling technology impact on cluster microprocessor performance (2003) (10)
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session) (2000) (9)
Exploring Microprocessor Architectures for Gigascale Integration (1999) (9)
Short-channel V-groove MOS (VMOS) logic (1974) (9)
An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC) (2000) (9)
Interconnect performance limits on gigascale integration (GSI) (1995) (9)
Impact of Random Dopant Placement on CMOS Delay and Power Dissipation (1999) (9)
Optimal global interconnecting devices for GSI (2002) (9)
Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI) (2008) (9)
Physical limits of VLSI DRAMs (1985) (9)
Generic models for interconnect delay across arbitrary wire-tree networks (2000) (9)
Potential improvements in power-speed performance of digital circuits (1971) (9)
An implantable blood flowmeter using monolithic integrated circuits (1972) (9)
Source-pulsed dynamic-threshold CMOS SRAMs for fast, portable applications (2000) (9)
Cost analysis of compliant wafer level package (2000) (9)
Wafer-Testing of Optoelectonic–Gigascale CMOS Integrated Circuits (2011) (9)
Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems (2007) (9)
Chip-to-Module Interconnections Using "Sea of Leads" Technology (2003) (9)
Short-channel modeling of bulk accumulation MOSFETs (2004) (9)
An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation (2004) (9)
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI) (1996) (9)
General compact model for bit-rate limit of electrical interconnects considering DC resistance, skin effect and surface scattering (2004) (8)
A compact model for projections of future power supply distribution network requirements (2002) (8)
A transparent electrode CCD image sensor for a reading aid for the blind (1974) (8)
Performance enhancement through optimal n-tier multilevel interconnect architectures (1999) (8)
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion (2000) (8)
Impact of high-/spl kappa/ dielectrics on undoped double-gate MOSFET scaling (2002) (8)
Electrical performance of compliant wafer level package (2001) (8)
Unambiguous measurement of volume flow using ultrasound (1975) (8)
Optimum on-chip power distribution networks for gigascale integration (GSI) (2001) (8)
Interconnect-centric array architectures for minimum SRAM access time (2001) (8)
Applications of totally implantable telemetry systems to chronic medical research. (1979) (7)
Interconnection Limits on XXI Century Gigascale Integration (GSI) (1998) (7)
Optimal Repeaters for Sub-50nm Interconnect Networks (2006) (7)
An integrated circuit approach to totally implantable telemetry systems. (1979) (7)
The √f power-spectrum centroid detector: System considerations, implementation, and performance (1980) (7)
Optical Through-Wafer Interconnects for 3D Hyper-Integration (2006) (7)
Totally implantable directional Doppler flowmeters. (1979) (7)
A recombination model for the low current performance of submicron devices (1982) (7)
Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration (2004) (7)
New CMOS Driver and Receiver Circuits Reduce Interconnection Propagation Delays (1985) (7)
Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects (2005) (7)
A compact delay model for series-connected MOSFETs (2002) (7)
Silicon Epitaxy and Oxidation (1977) (7)
A new complementary bipolar transistor structure (1972) (7)
A Flexible, Real-Time System for Experimentation in Phased-Array Ultrasound Imaging (1980) (7)
Integrated Electronics in Medicine (1976) (7)
Physics-based device models for nanoscale double-gate MOSFETs (2004) (6)
Electrical and Optical Chip I/O Interconnections for Gigascale Systems (2007) (6)
Hydrogenation of Graphene Nanoribbon Edges: Improvement in Carrier Transport (2013) (6)
Optimal clock distribution with an array of phase-locked loops for multiprocessor chips (2001) (6)
A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration (2010) (6)
Calibration of a Doppler Blood Flowmeter for Measurements Independent of Flow Angle, Velocity Profile, and Lumen Shape (1976) (6)
WSi2gate MOS devices (1979) (6)
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures (2000) (6)
Optimal printed wiring board design for high I/O density chip size packages (1999) (6)
Opportunities for non-dissipative computation [adiabatic logic] (1996) (6)
Computer-Aided Engineering of Semiconductor Integrated Circuits. (1978) (6)
Morphology of Silicon Islands Grown By Selective Epitaxy Over Silicon Dioxide (1985) (6)
High Resolution Dynamic Ultrasonic Imaging (1978) (6)
The Impact of Integrated Electronics in Medicine (1977) (6)
Powe-spectrum centroid detection for Doppler systems applications. (1980) (6)
Flexible polymer pillars for optical chip assembly: materials, structures, and characterization (2007) (6)
Analytical models for coupled distributed RLC lines with ideal and nonideal return paths (2001) (6)
The urgency of deep sub-ambient cooling for gigascale integration (2005) (5)
Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices (2010) (5)
Definitions of Terms for Integrated Electronics (1967) (5)
An optimal partition between on-chip and on-board interconnects (2001) (5)
SOI MOSFET fluctuation limits on gigascale integration (GSI) (1999) (5)
Biochemical sensing with an arrayed silicon nanowire platform (2010) (5)
The impact of Cu/low /spl kappa/ on chip performance (1999) (5)
Power Dissipation in Microelectronic Transmission Circuits (1961) (5)
A redundant metal-polyimide thin film interconnection process for wafer scale dimensions (1990) (5)
I/sup 2/L DC functional requirements (1977) (5)
Inhibition of thrombus formation on intravascular sensors by electrical polarization. (1984) (5)
Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics (2004) (5)
Charge-coupled devices for use in electronically focused ultrasonic imaging systems (1978) (5)
Impact of deep sub-ambient cooling on GSI interconnect performance (2005) (5)
An Improved Wedge-Type Backing for Piezoelectric Transducers (1979) (5)
OPTIMIZATION OF THE HYDRAZINE-WATER SOLUTION FOR ANISOTROPIC ETCHING OF SILICON IN INTEGRATED CIRCUIT TECHNOLOGY (1975) (5)
Totally implantable dimension telemetry. (1979) (5)
Ultra high I/O density package: Sea of Leads (SoL) (2001) (5)
Optimal repeater insertion for n-tier multilevel interconnect architectures (2000) (5)
Optimization, performance and limitations of monolithic polycrystalline silicon distributed RC devices (1979) (5)
An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs (1993) (5)
Scaling limits of Si MOSFET technology imposed by random parameter fluctuations (1996) (5)
Integrated electron devices in medicine (1977) (5)
An IGFET Inversion Charge Model for VLSI Systems (1985) (4)
Optical waveguides with embedded air-gap cladding integrated within a sea-of-leads (SoL) wafer-level package (2002) (4)
The field-effect modified transistor: a high-responsivity photosensor (1972) (4)
IMPLANTABLE ULTRASONIC BLOOD FLOWMETERS (1972) (4)
Electromigration Resistant Power Delivery Systems (2007) (4)
A monolithic signal processor for multichannel implantable telemetry (1979) (4)
Optimal implementation of sea of leads (SoL) compliant interconnect technology (2004) (4)
Static and dynamic performance of micropower transistor logic circuits (1964) (4)
The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks (2007) (4)
Impact of High-KDielectrics on Undoped Double-Gate MOSFET Scaling (2002) (4)
High voltage monolithic MOS driver arrays (1971) (4)
MOS electronics for a reading aid for the blind (1970) (4)
Template-Set Approach to VLSI Pattern Inspection (1987) (4)
Polymer optical interconnect technologies for polylithic gigascale integration (2003) (4)
Integrated circuits for an implantable CW Doppler ultrasonic flowmeter (1977) (4)
Effects of Coarse Phase Quantization in Ultrasound Scanners (1978) (4)
Circuit techniques for low-power CMOS GSI (1996) (4)
Telemetry methods: animal and man. (1983) (4)
A novel via blockage model and its implications (2000) (4)
DMOS experimental and theoretical study (1975) (4)
A transparent-electrode CCD image sensor (1973) (4)
Electrical test strategies for a wafer-level packaging technology (2003) (4)
Comparative performance limits of MOSFET, MESFET and MODFET digital circuits (1990) (4)
An Ultrasonic Technique for Unambiguous Measurement of Blood Volume Flow (1974) (4)
An Ultrasonic Scanning System for Arterial Imaging (1973) (4)
Micropower integrated circuits for an implantable bidirectional blood flowmeter (1976) (3)
Two-material, air-clad, grating-in-the-waveguide optical interconnects (2004) (3)
Application of integrated electronics to ultrasonic medical instruments (1979) (3)
Poly I2L - A high-speed linear compatible structure (1977) (3)
An analysis of the gap between PWB technology and chip I/O interconnect technology, and a new wafer-level batch packaging concept (1999) (3)
A micropower, small input-to-output delay, high-voltage bipolar driver/demultiplexer IC (1981) (3)
A low-light-level self-scanned MOS image sensor (1972) (3)
Enhancing Hysteresis in Graphene Devices Using Dielectric Screening (2012) (3)
Complete Analytical Model for Different Variations of FinFET (2013) (3)
Low-power circuit advantages of the scaled accumulation FET (2002) (3)
`Trimodal' Wafer-Level Package: Fully Compatible Electrical, Optical, and Fluidic Chip I/O Interconnects (2007) (3)
The cascade charge-coupled device: A single-chip lens for ultrasonic imaging systems (1976) (3)
p-Type Electrical Transport of Chemically Doped Epitaxial Graphene Nanoribbons (2012) (3)
Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction (1993) (3)
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection (2002) (3)
Quantum mechanical effects on CMOS SOC performance (2003) (3)
Sol-compilant wafer-level package technologies (2002) (3)
A New Global Interconnect Paradigm: MIM Power-Ground Plane Capacitors (2006) (3)
Offset word line architecture for scaling DRAMs to the Gigabit level (1987) (3)
STOCHASTIC MULTILEVEL INTERCONNECT MODELING AND OPTIMIZATION (2003) (3)
E/D CMOS - A High Speed VLSI Technology (1983) (3)
THERMAL OXIDATION OF HEAVILY PHOSPHORUS-DOPED SILICON (1978) (3)
Performance limits of NMOS and CMOS (1984) (3)
Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects (2006) (3)
A monolithic analog signal processor for ultrasonic imaging systems (1975) (3)
CMOS system-on-a-chip voltage scaling beyond 50nm (2000) (3)
Oxide Thickness Scaling Limit for Optimum CMOS Logic Circuit Performance (2000) (3)
Asymptotically zero power dissipation gigahertz clock distribution networks (1999) (3)
A LOW POWER TRANSREGIONAL MOSFET MODEL CMOS GIGASCALE INTEGRATION (GSI) * FOR COMPLETE POWER-DELAY ANALYSIS OF (1998) (2)
Micropower linear compatible I2L techniques in biomedical telemetry (1980) (2)
High-density probe substrate for testing optical interconnects (2005) (2)
Implantable Integrated Electronics (1974) (2)
Large-value monolithic resistors for micropower integrated circuits (1972) (2)
Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010 (1997) (2)
Theoretical Analysis oftheCW DopplerUltrasonic Flowmeter (1974) (2)
Temperature Sensitive Transistor DC Stabilization Networks (1961) (2)
TA-A5 scaling and limits of monolithic polycrystalline silicon resistors (1980) (2)
Fluctuation Limits on Scaling of CMOS SRAMs (2000) (2)
USLI system models (1988) (2)
A new complementary monolithic transistor structure (1972) (2)
A Cardiac Dynamics Visualization System (1973) (2)
Foreword (September 1966) (1966) (2)
A novel technique for detecting lithographic defects (1988) (2)
WP-A1 monolithic polycrystalline silicon distributed RC devices (1978) (2)
Preface: Special Issue on Large Scale Integration (1967) (2)
Delay Generated Offset: A Direction Sensitive Pulse-Coherent Doppler Detection Technique (1977) (2)
Optimal circuit design for low power CMOS GSI (1996) (2)
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution (2004) (2)
Towards a comparison between chip-level optical interconnection and board-level exterconnection (2002) (2)
MOSFET Fluctuation Limits on Gigascale Integration (GSI) (1998) (2)
Minimizing energy-per-bit for on-board LC transmission lines (2005) (2)
Reliability challenges of FinFET and other multi-gate MOSFETs (2013) (2)
Dual-mode electrical-optical flip-chip I/O interconnects and a compatible probe substrate for wafer-level testing (2006) (2)
Doppler Instrumentation For Measuring Blood Velocity And Flow (1976) (2)
Relative inductance extraction method (2004) (2)
Invited: Integrated electronics in medicine (1974) (2)
The Coming Era of Microelectronics (1962) (2)
A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects (2005) (1)
uasi-free-space optical coupling between iffraction grating couplers fabricated on ndependent substrates (2004) (1)
A Fast Turn-Around Facility for Very Large Scale Integration (VLSI) (1981) (1)
Electrocutaneous Stimulation inaReadini (1971) (1)
Winning by a whisker (1998) (1)
Compact, Physics-Based Modeling of Nanoscale Limits of Double-Gate MOSFETs (2004) (1)
Atlas: a dynamically parallelizing chip-multiprocessor for gigascale integration (2000) (1)
An Integrated Circuit Implantable Pulsed Doppler Ultrasonic Blood Flowmeter (1974) (1)
Compliant Wafer Level Package (2001) (1)
Selective Epitaxial Graphene Growth on SiC via AlN Capping (2011) (1)
Nanotechnology: Retrospect and Prospect (2008) (1)
Real-Time Doppler Imaging for Unambiguous Measurement of Blood Volume Flow (1975) (1)
Corrections to "A quantitative model of the effect of grain size on the resistivity of polycrystalline silicon resistors" (1980) (1)
Editor's Notice (March 1967) (1967) (1)
Selective Graphitization of Silicon Carbide: Effect of Argon Background Pressure and Transport Measurements on the Epitaxial Graphene (2010) (1)
STATIC AND DYNAMIC PERFORMANCE OF MICROPOWER TRANSISTOR LINEAR AMPLIFIERS (1963) (1)
21st century gigascale integration (GSI) (1995) (1)
Ultrasonic Doppler measurement of renal artery blood flow (1975) (1)
A high-voltage MOSFET in polycrystalline silicon (1980) (1)
Bimodal MOS-bipolar monolithic kitchip array (1977) (1)
Physical models for electron transport in graphene nanoribbons and their junctions (2008) (1)
VLSI Process Problem Diagnosis and Yield Prediction: A Comprehensive Test Structure and Test Chip Design Methodology, (1985) (1)
Electronic Devices from Nano-patterned Epitaxial Graphite (2005) (1)
Fabrication of Bow-Tie Nano-Gap Structures by Electron Beam Lithography (2007) (1)
Opportunities for Gigascale Integration (GSI) Beyond 2003 (1993) (1)
Scaling Limits of Rectangular and Trapezoidal Channel FinFETs (2013) (1)
An intelligent multiplexer/driver integrated circuit for an implantable multichannel blood flowmeter (1989) (1)
Plasma processing of high density vias in Compliant Wafer Level Package (2001) (1)
Circuits for an Implantable Blood Flowmeter (1976) (1)
A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI) (1996) (1)
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method (2008) (1)
Integrated circuit implantable systems. (1979) (1)
Impact of Width Variation of Global Inductive VLSI Interconnect Line (2020) (1)
Analysis of thermal management in the system assembly of high density chip size packages (2000) (1)
Hierarchy of Limits of Power (1995) (1)
Device characteristics for poly I2L (1977) (1)
Large-Value Monolithic Resistors for Integrated Circuits Micropower (1972) (1)
Low Temperature Diffusion of Boron from Diborane Using Carbon Dioxide as Oxidant (1977) (1)
A prospectus for gigascale integration (GSI) (1993) (1)
New Con ode1 for Polycrystalline Silicon Films (1981) (1)
The Impact of Polysilicon-Resistor Scaling on the Performance of a VLSI Static RAM Cell (1981) (1)
Chemical Etching of Piezo-Electric Ceramics (半導体デバイス特集-6-) (1976) (1)
Electrical test strategies for a wafer-level packaging technology [Abstracts of Forthcoming Manuscripts] (2003) (1)
A multi-campus virtual corporate laboratory (2000) (1)
Three phase domino logic circuit (2002) (1)
Considerations for high-speed and analog-circuit-compatible I/sup 2/L and the analysis of Poly I/sup 2/L (1979) (1)
XXI century gigascale integration (GSI): the interconnect problem (1999) (1)
ADVANCES IN TOTALLY IMPLANTABLE DIMENSION SYSTEMS. (1984) (1)
Oxidation and epitaxy (1977) (1)
Integrated circuit implantable systems. (1979) (1)
A digital radio command link for implantable biotelemetry applications (1984) (1)
A 10 GHz hybrid optical/electrical clock distribution network for gigascale integration (1999) (1)
A 2µm poly-gate CMOS analog/digital array (1984) (0)
SPECIAL SECTION ON SYSTEM-LEVEL INTERCONNECT PREDICTION (SLIP) (2004) (0)
BLOOD FLOW TRANSDUCERS FOR IMPLANTABLE TELEMETRY SYSTEMS. (1984) (0)
JTEC panel report on advanced computing in Japan. Executive summary (1990) (0)
Monolithic circuits for a pulse-powered micropower command receiver (1977) (0)
Electrical, Optical and Thermofluidic Chip I/O Interconnections (2007) (0)
SESSION II: ANALOG CIRCUIT TECHNIQUES (1977) (0)
The Use of a Silicon-Gate C-MOS/SOS Test VehicI to Evaluate Technology Maturity (1978) (0)
Improving electron beam resist sensitivity by preexposure to deep ultraviolet radiation (2007) (0)
Compact physical models for multilevel interconnect crosstalk in a gigascale SoC (2003) (0)
SESSION XIV: New Applications of Integrated Electronics (1969) (0)
Keynote Address: 21st Century Gigascale Integration (GSI) (1995) (0)
Single Chip Lenses for Ultrasonic Imaging. Effects of Transfer Efficiency on Lens Performance (1978) (0)
Formal opening of conference (1969) (0)
Modeling Process Variations Using a Compact Model (2007) (0)
AN ULTRASONIC TECHNIQUE FOR UNAMBIGUOUS MEASUREhC3;ZENT OF BLOOD VOLbIqE FLOW (1974) (0)
FOURPOLE PARAMETRIC CHARACTERIZATION OF INTEGRATED CIRCUITS (1962) (0)
Design and Test Automation-Gigascale Integration (GSI) in the 21st Century (1991) (0)
AC Temperature Compensation of Integrated Amplifiers (1962) (0)
Compliant probe substrates with two-material, air-clad, grating-in-waveguide optical I/O interconnects (2004) (0)
Microelectronic systems engineering (1961) (0)
Template-Set Approach to VLSI (Very Large Scale Integrated) Pattern Inspection, (1984) (0)
Threshold Variations for Undoped Double-Gate MOSFET’s (2002) (0)
Compact Quantum Mechanical Device Models for MOSFETs in Gigascale Integration ( GSI ) (2002) (0)
Wafer-Testing of Optoelectonic-Gigascale (2011) (0)
SESSION XVIII: ADVANCED TECHNOLOGY (1976) (0)
Polymer pillar optical transmittance analysis (2004) (0)
FAM 19.3: A Monolithic Signal Processor for Neurophysiological Telemetry* (1981) (0)
()> IEEE ENGINEERNG IN MEDICINE AND BIOLOGY GROUP TheIEEEEngineering inMedicine andBiology Groupisanorganization within theframework oftheIEEEofmembers withprincipal Professional in- terest inbiomedical engineering. Allmembers oftheIEEEareeligible formembership intheGroupandwill receive this TRANSAC (1975) (0)
An Asynchronous Digital Multiplexer For Biotelemetry (1988) (0)
Epitaxial V-groove integrated circuit process (1972) (0)
A compact substrate spreading resistance model for SoC (2003) (0)
Impact of interconnect parameter variations on wire-tree delay (2000) (0)
SESSION IX: Integrated Electronics in Biomedicine (1971) (0)
Center of Excellence in Aerospace Manufacturing Automation (1983) (0)
Graphene Process Integration for Post-CMOS Devices (2010) (0)
BROAD BANDWIDTH LOW NOISE BIOTELEMETRY RECEIVER. (1984) (0)
An implantable multichannel ultrasonic pulsed Doppler blood flowmeter (1989) (0)
2 – Implantable Telemetry (1986) (0)
The square root of f power-spectrum centroid detector: system considerations, implementation, and performance. (1980) (0)
Sensors: solid state integrated platform for sensing arrays (2006) (0)
Gigascale Integration (GSI) in the 21 Century (1991) (0)
Electric Field Effect in Epitaxial Graphene Devices (2008) (0)
SMALL-SIGNAL TRANSISTOR CHARACTERIZATION FOR THE HF AND VHF RANGE. (1965) (0)
A new micropower complementary bipolar transistor structure (1972) (0)
Editor's Notice (June 1968) (1968) (0)
Communication of Novel Computational State Variables : Physical Limits and Circuit Implications (2009) (0)
A-C temperature compensation and integrated amplifiers (1963) (0)
Distributed RC and RLC Transient Models (2003) (0)
I/O Interconnections for Gigascale Integration (2003) (0)
Computer Aided Fast Turnaround Laboratory for Research in VLSI (Very Large Scale Integrated). (1987) (0)
STATIC AND DYNAMIC PERFORMANCE OF MICROPOWER TRANSISTOR LOGIC CIRCUITS. PART I: MICROPOWER TRANSISTOR CHARACTERIZATION. (1965) (0)
Performance Limits Due to Inter-Cluster Data Forwarding in Wire-Limited ILP Microprocessors (2000) (0)
Physical Modeling Of Nanoelectronic Devices (1993) (0)
Unified 2D Short Channel Effects Model for Bulk CMOS FETs (0)
Polymer Pillars as Optical I/O for Gigascale Chips using Mirror-Terminated Waveguides (2006) (0)
Single Chip Lenses for Ultrasonic Imaging (1979) (0)
Gigascale integration (GSI) technology (1991) (0)
Foreword the interdisciplinary scope of the ISSCC (1969) (0)
Listing of Papers Presented at the 1975 International Conference on the Application of Charge-Coupled Devices (1976) (0)
Integration of waveguide volume grating couplers with optical polymer pillars (2005) (0)
Integration of Polymer Pins, Volume Gratings and Waveguides for Chip-to-Board and Board-to-Chip Optical Interconnects (2007) (0)
Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnections (2004) (0)
SESSION XIII: ADVANCED CIRCUIT APPLICATIONS (1979) (0)
'The Evolution of Monolithic and I'sl)litliir Interronncct 'Technole~v (2002) (0)
A Compact Physical Model for Critical Quantum Mechanical Effects in Bulk MOSFETs (2005) (0)
The field-effect modified transistor: A new compound transistor (1971) (0)
VIB-5 the effect of metalic precipitates on the I-V characteristics of bipolar transistors and diodes (1981) (0)
STATIC AND DYNAMIC PERFORMANCE OF MICROPOWER TRANSISTOR LOGIC CIRCUITS. PART II. MICROPOWER LOGIC CIRCUIT DESIGN. (1967) (0)
Center for Automation and Manufacturing Science Established at Stanford University. (1985) (0)
Scaled accumulation FETs for ultra-low power logic (2002) (0)
21st Century Opportunities For Gigascale Integration (GSI) (1998) (0)
Incentives for Using Higher Frequency in Ultrasonic Imaging (1980) (0)
UP-TO-DATE COVERAGE on theories, applications, and techniques in (1971) (0)
SESSION XVI: PROCESSING AND DEVICE TECHNOLOGY ADVANCEMENTS (1979) (0)
Advanced Technology for Micropower Integrated Circuits. (1975) (0)
Center for Automation and Manufacturing Science. (1986) (0)
Scanning the issue (1986) (0)
Sensitivity analysis of grating couplers in gigascale integration (GSI) (2003) (0)
Integrated Electronics for Acoustic Imaging Arrays (1976) (0)
Micropower linear circuits (1966) (0)
The Power-Spectrum Centroid Detector: System Considerations, Implementation, and Performance (1980) (0)
Gigascale integration (GSI) beyond 2001 (1991) (0)
EDITOR'S NOTICE (1970) (0)

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