James Edwin Smith
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Engineering Computer Science
James Edwin Smith's Degrees
- PhD Computer Science Stanford University
- Masters Computer Science Stanford University
- Bachelors Electrical Engineering Stanford University
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(Suggest an Edit or Addition)James Edwin Smith's Published Works
Number of citations in a given year to any of this author's works
Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author
Published Works
- Complexity-Effective Superscalar Processors (1997) (922)
- Virtual machines - versatile platforms for systems and processes (2005) (765)
- A study of branch prediction strategies (1981) (700)
- The architecture of virtual machines (2005) (697)
- Trace cache: a low latency approach to high bandwidth instruction fetching (1996) (545)
- The predictability of data values (1997) (508)
- Data Cache Prefetching Using a Global History Buffer (2004) (370)
- Managing multi-configuration hardware via dynamic working set analysis (2002) (367)
- The microarchitecture of superscalar processors (1995) (344)
- Fair Queuing Memory Systems (2006) (342)
- Trace processors (1997) (330)
- A first-order superscalar processor model (2004) (324)
- Speculative versioning cache (1998) (308)
- Implementing Precise Interrupts in Pipelined Processors (1988) (299)
- Decoupled access/execute computer architectures (1984) (289)
- Assigning confidence to conditional branch predictions (1996) (265)
- Implementation of precise interrupts in pipelined processors (1985) (248)
- Comparing program phase detection techniques (2003) (247)
- Modeling superscalar processors via statistical simulation (2001) (204)
- Configurable isolation: building high availability systems with commodity multi-core processors (2007) (188)
- A performance counter architecture for computing accurate CPI components (2006) (179)
- A mechanistic performance model for superscalar out-of-order processors (2009) (177)
- Virtual private caches (2007) (176)
- Path-based next trace prediction (1997) (163)
- Decoupled access/execute computer architectures (1982) (137)
- AC/DC: an adaptive data cache prefetcher (2004) (134)
- Instruction Issue Logic in Pipelined Supercomputers (1984) (132)
- Quantifying the Complexity of Superscalar Processors (2002) (126)
- Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox (2003) (125)
- Very low power pipelines using significance compression (2000) (118)
- Improving multiprocessor performance with coarse-grain coherence tracking (2005) (113)
- A Trace Cache Microarchitecture and Evaluation (1999) (111)
- Multicore Resource Management (2008) (111)
- Vector architectures: past, present and future (1998) (104)
- An instruction set and microarchitecture for instruction level distributed processing (2002) (101)
- Prefetching in supercomputer instruction caches (1992) (99)
- Implementations of Context Based Value Predictors (1997) (96)
- A Simulation Study of Decoupled Architecture Computers (1986) (91)
- The ZS-1 central processor (1987) (88)
- A study of scalar compilation techniques for pipelined supercomputers (1987) (85)
- Optimal pipelining in supercomputers (1986) (80)
- Control flow speculation in multiscalar processors (1997) (79)
- Instruction Cache Replacement Policies and Organizations (1985) (78)
- A Day in the Life of a Data Cache Miss (2002) (76)
- Out-of-order vector architectures (1997) (76)
- A study of control independence in superscalar processors (1999) (75)
- Vector instruction set support for conditional operations (2000) (74)
- Trace Processors: Moving to Fourth-Generation Microarchitectures (1997) (70)
- Automated design of application specific superscalar processors: an analytical approach (2007) (69)
- Modeling program predictability (1998) (69)
- The future of simulation: a field of dreams (2006) (63)
- A study of instruction cache organizations and replacement policies (1983) (63)
- Instruction pre-processing in trace processors (1999) (63)
- Improving branch predictors by correlating on data values (1999) (59)
- Characterizing the branch misprediction penalty (2006) (56)
- Performance Of Cached Dram Organizations In Vector Supercomputers (1993) (56)
- Statistical simulation of symmetric multiprocessor systems (2002) (53)
- Rapid profiling via stratified sampling (2001) (52)
- Control independence in trace processors (1999) (52)
- PowerPC 601 and Alpha 21064: a tale of two RISCs (1994) (52)
- On Separable Unordered Codes (1984) (52)
- An approach for implementing efficient superscalar CISC processors (2006) (52)
- Stealth prefetching (2006) (49)
- Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays (2006) (45)
- Using dynamic binary translation to fuse dependent instructions (2004) (45)
- Saving energy with just in time instruction delivery (2002) (43)
- Hardware support for control transfers in code caches (2003) (42)
- Dynamic binary translation for accumulator-oriented architectures (2003) (41)
- The complexity of verifying memory coherence and consistency (2005) (40)
- Implementing Kilo-Instruction Multiprocessors (2005) (40)
- Exploring code cache eviction granularities in dynamic optimization systems (2004) (40)
- POWER and PowerPC (1994) (40)
- Dynamic Verification of Cache Coherence Protocols (2004) (39)
- The complexity of verifying memory coherence (2003) (39)
- Relational profiling: enabling thread-level parallelism in virtual machines (2000) (38)
- Cache performance in vector supercomputers (1994) (37)
- Power-Efficient DRAM Speculation (2008) (36)
- Isolation in Commodity Multicore Processors (2007) (35)
- An accurate, high speed implementation of division by reciprocal approximation (1989) (34)
- A Performance Study of Instruction Cache Prefetching Methods (1998) (34)
- Developments in Logic Network Path Delay Analysis (1982) (34)
- The Performance Potential of Data Dependence Speculation & Collapsing (1996) (33)
- Instruction-Level Distributed Processing (2001) (32)
- Early-Stage Definition of LPX: A Low Power Issue-Execute Processor (2002) (32)
- Runtime specialization with optimistic heap analysis (2005) (32)
- Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing (1992) (31)
- Dual path instruction processing (2002) (31)
- An Overview of Virtual Machine Architectures (2004) (30)
- Reducing Startup Time in Co-Designed Virtual Machines (2006) (30)
- Exploiting idle floating-point resources for integer execution (1998) (28)
- Decoupling integer execution in superscalar processors (1995) (27)
- A Top-Down Approach to Architecting CPI Component Performance Counters (2007) (27)
- Future general purpose supercomputer architectures (1990) (25)
- A study of scalar compilation techniques for pipelined supercomputers (1990) (25)
- Concurrent garbage collection using hardware-assisted profiling (2000) (22)
- An analysis of value predictability and its application to a superscalar processor (1999) (22)
- Software-controlled operand-gating (2004) (22)
- Introduction to Virtual Machines (2005) (20)
- Trace preconstruction (2000) (19)
- Characterizing Coarse-Grained Reuse of Computation (2000) (17)
- Decoupled access/execute computer architectures (1982) (17)
- Saving and Restoring Implementation Contexts with co-Designed Virtual Machines (2001) (17)
- Virtual private machines: a resource abstraction for multicore computer systems (2009) (15)
- Pipe: a high performance VLSI architecture (1983) (15)
- Trace processors: exploiting hierarchy and speculation (1999) (14)
- Experience on Performance Evaluation with OGSA-DQP (2005) (14)
- System Virtual Machines (2005) (14)
- Implementing high availability memory with a duplication cache (2008) (13)
- Service-based distributed query processing on the grid (2003) (13)
- Restricted Fetch and Φ operations for parallel processing (1989) (12)
- Efficient digital neurons for large scale cortical architectures (2014) (11)
- Automated design of application-specific superscalar processors (2006) (10)
- Superconducting Computing with Alternating Logic Elements (2021) (9)
- PIPE: a high performance VLSI processor implementation (1987) (8)
- ECE-978 December 1997 Implementations of Context Based Value Predictors (1997) (8)
- Motivating Commodity Multi-Core Processor Design for System-level Error Protection (8)
- Power and power PC - principles, architecture, implementation (1994) (7)
- Instruction Level Distributed Processing (2000) (7)
- Timing reconfigurable microarchitectures for power efficiency (2004) (7)
- Data Memory Alternatives for Multiscalar Processors (1996) (7)
- A study of partitioned vector register files (1992) (7)
- IBM Power and PowerPC (1994) (6)
- Process Virtual Machines (2005) (6)
- A Rollback-Recovery Protocol for Wide Area Pipelined Data Flow Computations (2004) (6)
- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis (2008) (6)
- Implicit Transactional Memory in Kilo-Instruction Multiprocessors (2007) (6)
- A unified view of virtualization (2005) (4)
- Keynote: Is there anything more to learn about high performance processors? (2003) (4)
- Dynamic Verification of Cache Coherence (3)
- A co-designed virtual machine for instruction-level distributed processing (2004) (3)
- High-performance frontends for trace processors (1999) (3)
- Retrospective: a study of branch prediction strategies (1998) (3)
- Applying Low-Overhead Rollback-Recovery to Wide Area Distributed Query Processing (2004) (3)
- Value Compression for Efficient Computation (2005) (3)
- Dynamic Software Trace Caching (3)
- Integrated Injection Logic (1980) (3)
- Tuning adaptive microarchitectures (2006) (3)
- Achieving high availability with commodity hardware and software (2008) (3)
- Reducing Overhead for Soft Error Coverage in High Availability Systems (3)
- Performance of Parallel Loops using Alternative Cache Consistency Protocols on a Non-Bus Multiprocessor (1990) (3)
- Limits of Data Value Predictability (1999) (2)
- Retrospective: decoupled access/execute architectures (1998) (2)
- Retrospective: implementing precise interrupts in pipelined processors (1998) (2)
- Efficient binary translation in co-designed virtual machines (2006) (2)
- Studying Compiler-Microarchitecture Interactions through Interval Analysis (2007) (1)
- Techniques for transparent program specialization in dynamic optimizers (2003) (1)
- An Architecture for a Parallel Object Database (2000) (1)
- Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture (1998) (1)
- Relational profiling in multithreaded virtual machines (2002) (1)
- High-Level Language Virtual Machine Architecture (2005) (1)
- Wrapper Based Adaptive Management of Concurrent Workflow Executions (2007) (1)
- Integrated Performance, Power, and Thermal Modeling (2002) (1)
- Concurrent Garbage Collection UsingHardware-Assisted Profiling (2000) (1)
- KIMP: Multicheckpointing Multiprocessors (2005) (1)
- Chip Multiprocessors with Implicit Transactions (2006) (1)
- Autonomic management of adaptive microarchitectures (2004) (1)
- Characterizing the Branch Miss Prediction Penalty (1)
- Dynamic Binary Optimization (2005) (0)
- Implicit transactional memory in chip multiprocessors (2007) (0)
- Current Resource Management Mechanisms and Policies Are Inadequate for Future Multicore Systems. Instead, a Hardware/software Interface Based on the Virtual Private Machine Abstraction Would Allow Software Policies to Explicitly Manage Microarchitecture Resources. Vpm Policies, Implemented Primarily (2008) (0)
- A Study of Control Independence with a Single Flow of Control (1998) (0)
- Concurrent Management of Composite Services According to Response Time SLAs (2008) (0)
- Coarse-grain coherence tracking (2006) (0)
- Chapter Nine – Multiprocessor Virtualization (2005) (0)
- Towards Concurrent SLA-based Management in a Composite Service Data Centre (2008) (0)
- Some Real Observations on Virtual Machines (2004) (0)
- d d Restricted Dual Path Execution (1997) (0)
- High-Level Language Virtual Machine Implementation (2005) (0)
- The future of simulation: A field of dreams (2004) (0)
- Development of a small-scale computer cluster (2008) (0)
- 7-1-1992 Report of the Purdue Workshop on Grand Challenges in Computer Architecture ! for the Support of High Performance Computing (2013) (0)
- Instruction Level Distributed Processing: Adapting to Future Technology (2000) (0)
- Instruction-level Distributed Processing Technology Shifts Wire Delays (0)
- Pipelined Register-Storage Architectures (1986) (0)
- Solving multiprocessor drawbacks with kilo-instruction processors (2005) (0)
- Codesigned Virtual Machines (2005) (0)
- Chapter Ten – Emerging Applications (2005) (0)
- Emulation: Interpretation and Binary Translation (2005) (0)
- o f the Purdue W o rkshop on Grand Challenges in Computer Architecture for the Support o f High Performance Computing * (1992) (0)
- Intrinsic Compatibility in Process Virtual Machines (2006) (0)
- Appears in the “ XVI Jornadas de Paralelismo ” . Granada , Spain , September 2005 KIMP : Multicheckpointing Multiprocessors (2005) (0)
- Climbing The Knowledge Mountain - The New Solids Processing Design and Management Manual (2009) (0)
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What Schools Are Affiliated With James Edwin Smith?
James Edwin Smith is affiliated with the following schools:
