James Hoe | Academic Influence

James Hoe's AcademicInfluence.com Rankings

James Hoe

Computer Science

#4215

World Rank

#4436

Historical Rank

#1434

USA Rank

Computer Architecture

#70

World Rank

#72

Historical Rank

#27

USA Rank

Database

#8585

World Rank

#8997

Historical Rank

#1147

USA Rank

computer-science Degrees

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Computer Science

James Hoe's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science Stanford University

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Why Is James Hoe Influential?

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According to Wikipedia, James Hoe is a Taiwanese-American professor of Electrical and Computer Engineering at Carnegie Mellon University . He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. Professor Hoe’s current research focus is on devising a new FPGA architecture for power efficient, high-performance computing. His research group is working on developing an FPGA runtime environment that incorporates partial reconfiguration, virtualization, and protection features to manage an FPGA as a dynamically sharable multitasking compute resource.

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James Hoe's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling (2003) (609)
SimFlex: Statistical Sampling of Computer System Simulation (2006) (355)
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? (2010) (285)
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding (2007) (279)
Dual use of superscalar datapath for transient-fault detection and recovery (2001) (240)
RAMP: Research Accelerator for Multiple Processors (2007) (215)
Fingerprinting: bounding soft-error-detection latency and bandwidth (2004) (198)
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs (2012) (187)
Data reorganization in memory using 3D-stacked DRAM (2015) (177)
Reunion: Complexity-Effective Multicore Redundancy (2006) (157)
CoRAM: an in-fabric memory architecture for FPGA-based computing (2011) (156)
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture (2004) (151)
Computer Generation of Hardware for Linear Digital Signal Processing Transforms (2012) (121)
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing (2013) (118)
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation (2014) (116)
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs (2009) (100)
Hardware Synthesis from Term Rewriting Systems (1999) (98)
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures (2004) (89)
START-NG: Delivering Seamless Parallel Computing (1995) (85)
Synthesis of operation-centric hardware descriptions (2000) (79)
Operation-centric hardware description and synthesis (2004) (78)
Commercial Antivirus Software Effectiveness: An Empirical Study (2011) (75)
TurboSMARTS: accurate microarchitecture simulation sampling in minutes (2005) (73)
Time-Multiplexed Multiple-Constant Multiplication (2007) (72)
Generation of optical OFDM signals using 21.4 GS/s real time digital signal processing. (2009) (71)
Detecting Emerging Wearout Faults (2007) (71)
SPIRAL: Extreme Performance Portability (2018) (71)
Automatic generation of customized discrete Fourier transform IPs (2005) (66)
Simulation sampling with live-points (2006) (60)
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs (2008) (59)
High Performance Stereo Vision Designed for Massively Data Parallel Platforms (2010) (56)
Permuting streaming data using RAMs (2009) (55)
Formal datapath representation and manipulation for implementing DSP transforms (2008) (54)
Research accelerator for multiple processors (2006) (53)
MPI-StarT: Delivering Network Performance to Numerical Applications (1998) (50)
Statistical sampling of microarchitecture simulation (2006) (49)
Optical OFDM for the data center (2010) (47)
Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization (2019) (44)
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator (2007) (43)
Generating FPGA-Accelerated DFT Libraries (2007) (40)
3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming (2013) (39)
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems (2016) (37)
FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations (2011) (37)
OpenSPARC : An Open Platform for Hardware Reliability Experimentation (2008) (36)
An Evaluation of Stratified Sampling of Microarchitecture Simulations (2004) (35)
TRUSS: a reliable, scalable server architecture (2005) (35)
Achieving 100Gbps Intrusion Prevention on a Single Server (2020) (32)
Automatic Pipelining From Transactional Datapath Specifications (2010) (32)
High-level modeling and FPGA prototyping of microprocessors (2003) (30)
Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs (2020) (30)
Fast and accurate resource estimation of automatically generated custom DFT IP cores (2006) (26)
Automatic generation of streaming datapaths for arbitrary fixed permutations (2009) (24)
Design and simulation of 25 Gb/s optical OFDM transceiver ASICs (2011) (24)
HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM (2014) (24)
Real time stereo vision using exponential step cost aggregation on GPU (2009) (24)
Understanding the design space of DRAM-optimized hardware FFT accelerators (2014) (23)
CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing (2015) (23)
In-system FPGA prototyping of an Itanium microarchitecture (2004) (23)
Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes (2012) (23)
Real-Time Digital Signal Processing for the Generation of Optical Orthogonal Frequency-Division-Multiplexed Signals (2010) (22)
Nautilus: Fast automated IP design space search using guided genetic algorithms (2015) (21)
The CONNECT Network-on-Chip Generator (2015) (20)
FPGA-Accelerated Simulation of Computer Systems (2014) (19)
The Granularity of Soft-Error Containment in Shared-Memory Multiprocessors (2006) (19)
Optimizing FFT Precision in Optical OFDM Transceivers (2011) (17)
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform (2019) (17)
Design studies for ASIC implementations of 28 GS/s optical QPSK- and 16-QAM-OFDM transceivers. (2011) (17)
21.4 GS/s real-time DSP-based optical OFDM signal generation and transmission over 1600 km of uncompensated fibre (2009) (17)
High-Level Design and Validation of the BlueSPARC Multithreaded Processor (2010) (16)
3 D-Stacked Memory-Side Acceleration : Accelerator and System Design (2014) (16)
Design studies for an ASIC implementation of an optical OFDM transceiver (2010) (15)
Hardware implementation of the discrete fourier transform with non-power-of-two problem size (2010) (15)
Dependence of optical OFDM transceiver ASIC complexity on FFT size (2012) (14)
ProtoFlex: Co-simulation for Component-wise FPGA Emulator Development (2006) (14)
Fast bilateral filtering by adapting block size (2010) (14)
Domain-specific library generation for parallel software and hardware platforms (2008) (14)
Automatic multithreaded pipeline synthesis from transactional datapath specifications (2010) (14)
SimFlex: Fast, Accurate, and Flexible Simulation of Computer Systems (2006) (14)
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing (2012) (14)
Improving fixed-point accuracy of FFT cores in O-OFDM systems (2012) (13)
Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only) (2017) (13)
Spiral: Joint Runtime and Energy Optimization of Linear Transforms (2006) (12)
HAMLeT Architecture for Parallel Data Reorganization in Memory (2016) (12)
Custom-optimized multiplierless implementations of DSP algorithms (2004) (12)
Automatic cost minimization for multiplierless implementations of discrete signal transforms (2004) (12)
PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers (2007) (11)
Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations (2014) (11)
PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV (2018) (10)
StarT-X - A One-Man-Year Exercise in Network Interface Engineering (1998) (10)
Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration (2018) (10)
Applying SMARTS to SPEC CPU20001 (2003) (10)
CoRAM : An In-Fabric Memory Abstraction for FPGA-Based Computing (2010) (10)
FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation (2016) (10)
Discrete Fourier Transform Compiler : From Mathematical Representation to Efficient Hardware (2007) (10)
FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation (2014) (9)
We need kernel interposition over the network dataplane (2021) (9)
Enabling portable energy efficiency with memory accelerated library (2015) (9)
MEMOCODE 2007 Co-Design Contest (2007) (8)
The Future of Architectural Simulation (2010) (8)
GraphGen for CoRAM : Graph Computation on FPGAs (2013) (8)
Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications (2019) (8)
Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory (2014) (7)
High-Performance Memory Snapshotting for Real-Time, Consistent, Hypervisor-Based Monitors (2020) (7)
Synchronous extensions to operation centric hardware description languages (2004) (7)
2009 MEMOCODE Co-Design Contest (2009) (6)
Multiple constant multiplication by time-multiplexed mapping of addition chains (2004) (6)
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction (2013) (6)
Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors (2009) (6)
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models (2015) (5)
Recent progress on real-time DSP for direct detection optical OFDM transceivers (2011) (5)
FFT Compiler: from math to efficient hardware HLDVT invited short paper (2007) (5)
Full-System Architectural Exploration Sandbox (2005) (5)
Optimizing FFT Resource Efficiency on FPGA using High-level Synthesis (2017) (5)
MEMOCODE 2008 Co-Design Contest (2008) (5)
Virtualized Full-System Emulation of Multiprocessors using FPGAs (2007) (4)
Partial Reconfiguration for Design Optimization (2020) (4)
International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS: Foreword (2010) (4)
Accelerating Blocked Matrix-Matrix Multiplication using a Software-Managed Memory Hierarchy with DMA (2005) (4)
REDAC: Distributed, Asynchronous Redundancy in Shared Memory Servers (2008) (4)
A Personal Supercomputer for Climate Research (1999) (3)
Real-time DSP-based optical OFDM transmission (2010) (3)
A Service-Oriented Memory Architecture for FPGA Computing (2020) (3)
Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation (2009) (3)
Effective parallel computation on workstation cluster with a user-level communication network (1994) (3)
Understanding the performance of concurrent error detecting superscalar microarchitectures (2005) (3)
Generation of Custom DSP Transform IP Cores: Case Study Walsh-Hadamard Transform (2002) (3)
Linear Transforms : From Math to Efficient Hardware Extended (2008) (3)
Scheduling and Synthesis of Operation-Centric Hardware Descriptions (2005) (3)
Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation (2017) (2)
Tolerating Processor Failures in a Distributed Shared-Memory Multiprocessor (2006) (2)
Network substrate for parallel processing on a workstation cluster (1994) (2)
Technical Perspective: FPGA compute acceleration is first about energy efficiency (2016) (2)
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (2010) (2)
High-Level Design and Validation of the (2010) (2)
Cross-platform FPGA accelerator development using CoRAM and CONNECT (2013) (1)
StarT-Jr : A Parallel System from Commodity (1996) (1)
HerQules: securing programs via hardware-enforced message queues (2021) (1)
Integrating formal verification and high-level processor pipeline synthesis (2011) (1)
FPGA compute acceleration is first about energy efficiency: technical perspective (2016) (1)
Fingerprinting Across On-Chip Memory Interconnects (2007) (1)
Table of Contents 2015 IEEE International Symposium on Performance Analysis of Systems and Software ISPASS 2015 (2015) (1)
Highly Efficient Performance Portable Tracking of Evolving Surfaces (2012) (1)
Start-ng: Delivering Seamless Parallel Computing Start-ng: Delivering Seamless Parallel Computing (1995) (1)
Session details: Embedded multicore computing (2011) (0)
Zoom Out: Abstractions for Efficient Radar Algorithms on COTS architectures (2022) (0)
Keynote Talk III (2006) (0)
Synthesis of a synchronous circuit using an asynchronous specification (2000) (0)
BeiHang Short Course, Part 2: Operation Centric Hardware Operation-Centric Hardware Description and Synthesis (2014) (0)
Message from the chairs (2009) (0)
ACM SIGPLAN Notices: Foreword (2010) (0)
Nautilus (2015) (0)
A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem (2021) (0)
Predistortion and OFDM realizations (2011) (0)
CONNECT: Fast Flexible FPGA-Tuned Networks-on-Chip (2012) (0)
MEMOCODE 2006 guest editors’ introduction (2008) (0)
Hardware Synthesis from Term Rewriting Systems Computation Structures Group Memo 421 A August 20 , 1999 (1999) (0)
Flexible Hardware Accelerator Design Generation with Spiral (2022) (0)
Pigasus 2.0: making the pigasus IDS robust to attacks and different workloads (2022) (0)
Custom Reduction of Arithmetic in Linear DSP Transforms (2003) (0)
Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA (2023) (0)
CoRAM : FPGA Architecture for Computing (0)
6.823 Computer System Architecture, Spring 2002 (2002) (0)
Session details: Technical Session 4: Applications and System-level Tools (2016) (0)
Session details: Methods and representations for logic synthesis (2005) (0)
Undergraduate Research and Graduate Schools: "Life" outside-of-class and beyond (2012) (0)
Superscalar out-of-order demystified in four instructions (2003) (0)
Discrete Fourier Transform IP Generator (2004) (0)
Study of Performance and Optimization of MPI Over 100BaseT Switched Ethernet Networks (2001) (0)
Automatic Generation of Customized Discrete (2005) (0)
FPGA-based optical transmitters for electronic predistortion and advanced signal format generation (2009) (0)
CEDA currents: IEEE/ACM MEMOCODE Contest Update (2008) (0)
Discrete Fourier Transform Compiler for FPGA and CPU / FPGA Partitioned Implementations ∗ (2006) (0)
Perspectives on AI Architectures and Co-design for Earth System Predictability (2023) (0)
Session details: Latency tolerance and asynchronous design (2004) (0)
Dependable VLSI: Device, design and architecture - How should they cooperate? (2009) (0)
THE HISTORY OF INTERNAL PROCESSOR STATE UPDATES INTO A CRYPTOGRAPHIC SIGNATURE . THE PROCESSORS IN A DUAL MODULAR REDUNDANT PAIR (2009) (0)
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010 (2010) (0)
Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only) (2012) (0)
2004 Workshop on Duplicating , Deconstructing and Debunking June 20 , 2004 Munich , Germany (2004) (0)
Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration (2018) (0)
A Collaborative Research Proposal to the NSF: Research Accelerator for Multiple Processors (RAMP) - A Shared Experimental Parallel HW/SW Platform (2008) (0)
Session details: Design studies and design methodologies (2013) (0)

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