James R. Goodman | Academic Influence

James R. Goodman's AcademicInfluence.com Rankings

James R. Goodman

Computer Science

#2086

World Rank

#2168

Historical Rank

#963

USA Rank

Big Data

#27

World Rank

#27

Historical Rank

#4

USA Rank

Data Mining

#261

World Rank

#262

Historical Rank

#21

USA Rank

Software Engineering

#309

World Rank

#315

Historical Rank

#84

USA Rank

computer-science Degrees

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Computer Science

James R. Goodman's Degrees

PhD Computer Science Stanford University
Masters Computer Science Stanford University
Bachelors Computer Science Stanford University

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Why Is James R. Goodman Influential?

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According to Wikipedia, James Richard "Jim" Goodman retired as professor of computer science at the University of Auckland in Auckland, New Zealand, and emeritus professor at the University of Wisconsin–Madison. Education and research Goodman received a PhD from the University of California, Berkeley in 1980. He joined the faculty at the University of Wisconsin–Madison the same year as an assistant professor of computer science.

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James R. Goodman's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

Memory systems (1996) (708)
Structured Computer Organization (1976) (687)
Speculative lock elision: enabling highly concurrent multithreaded execution (2001) (506)
Memory Bandwidth Limitations of Future Microprocessors (1996) (464)
Cache Consistency and Sequential Consistency (1991) (356)
Transactional lock-free execution of lock-based programs (2002) (351)
Using cache memory to reduce processor-memory traffic (1983) (345)
The Wisconsin Multicube: a new large-scale cache-coherent multiprocessor (1988) (197)
Efficient synchronization primitives for large-scale cache-coherent multiprocessors (1989) (178)
Efficent Synchronization Primitives for Large-Scale Cache-Coherent Multiprocessors (1989) (178)
Hypertree: A Multiprocessor Interconnection Topology (1981) (163)
Code scheduling and register allocation in large basic blocks (1988) (158)
Efficient Synchronization: Let Them Eat QOLB (1997) (119)
PIPE: a VLSI decoupled architecture (1985) (117)
Billion-Transistor Architectures (1997) (112)
The Impact of Pipelined Channels on k-ary n-Cube Networks (1994) (109)
Using cache memory to reduce processor-memory traffic (1983) (97)
Coherency for multiprocessor virtual address caches (1987) (86)
Improving CC-NUMA performance using Instruction-based Prediction (1999) (86)
The declining effectiveness of dynamic caching for general- purpose microprocessors (1995) (81)
Performance of the SCI Ring (1992) (79)
Instruction Cache Replacement Policies and Organizations (1985) (78)
NZTM: nonblocking zero-indirection transactional memory (2009) (76)
Billion-transistor architectures: there and back again (2004) (75)
Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication (1972) (71)
Limited bandwidth to affect processor design (1997) (69)
A study of instruction cache organizations and replacement policies (1983) (63)
On the Minimization of Loads/Stores in Local Register Allocation (1989) (61)
Datascalar Architectures (1997) (53)
Noise reduction and targeted exploration in imitation learning for Abstract Meaning Representation parsing (2016) (48)
Efficient Synchronization: Let Them Eat QOLB /sup1/ (1997) (43)
Improving the throughput of synchronization by insertion of delays (2000) (34)
MESIF: A Two-Hop Cache Coherency Protocol for Point-to-Point Interconnects (2004) (2004) (34)
Transactional Execution: Toward Reliable, High-Performance Multithreading (2003) (33)
Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing (1992) (31)
An investigation of multiprocessor structures and algorithms for data base management (1980) (29)
Proceedings of the 39th Annual International Symposium on Computer Architecture (1983) (27)
Hardware support for synchronization in the Scalable Coherent Interface (SCI) (1994) (27)
The GLOW cache coherence protocol extensions for widely shared data (1996) (26)
Hardware techniques to improve the performance of the processor/memory interface (1998) (26)
Techniques for reducing overheads of shared-memory multiprocessing (1995) (25)
Author retrospective for code scheduling and register allocation in large basic blocks (1988) (23)
WISQ: a restartable architecture using queues (1987) (22)
Architectural approach to the role of optics in mono and multiprocessor machines. (2000) (22)
Billion-Transistor Architectures - Guest Editors' Introduction. (1997) (20)
On the use of registers vs. cache to minimize memory traffic (1986) (20)
Cache implementation for multiple microprocessors (1983) (19)
Synthesizing General Topologies from Rings (1992) (17)
The use of static column ram as a memory hierarchy (1984) (17)
Quantifying Memory Bandwidth Limitations of Current and Future Microprocessors (1996) (17)
UCL+Sheffield at SemEval-2016 Task 8: Imitation learning for AMR parsing with an alpha-bound (2016) (17)
Pipe: a high performance VLSI architecture (1983) (15)
An Analysis of Synchronization Mechanisms in Shared-Memory Multiprocessors (1991) (15)
Cache memory optimization to reduce processor/memory traffic (1987) (14)
Inferential queueing and speculative push for reducing critical communication latencies (2003) (13)
Transactional Value Prediction (2009) (13)
Mechanisms for efficient shared-memory, lock-based synchronization (1999) (13)
Performance of Pruning-Cache Directories for Large-Scale Multiprocessors (1993) (12)
Re-determinizing Information Set Monte Carlo Tree Search in Hanabi (2019) (12)
The SCI Cache Coherence Protocol (1992) (12)
Restricted Fetch and Φ operations for parallel processing (1989) (12)
A Programmer's View of Computer Architecture: With Assembly Language Examples from the MIPS RISC Architecture (1993) (11)
Interconnect Topologies With Point-To-Point Rings (1991) (10)
Identification and optimization of sharing patterns for scalable shared-memory multiprocessors (1998) (9)
PIPE: a high performance VLSI processor implementation (1987) (8)
Scalability and Its Application to Multicube (1989) (8)
A study of three dynamic approaches to handle widely shared data in shared-memory multiprocessors (1998) (7)
Simulation of the SCI Transport Layer on the Wisconsin Wind Tunnel (1995) (6)
DataScalar: A memory-centric approach to computing (1999) (5)
Inferential Queueing and Speculative Push (2004) (5)
Exploiting optical interconnects to eliminate serial bottlenecks (1996) (5)
Transactional conflict decoupling and value prediction (2011) (5)
An Analysis of the Interactions of Overhead-Reducing Techniques for Shared-Memory Multiprocessors (1995) (4)
SOFTQOLB: An Ultra-Efficient Synchronization Primitive for Clusters of Commodity Workstations (1996) (4)
Programmer's View of Computer Architecture: With Examples from the Mips RISC Architecture (1993) (4)
Does it matter how well I know what you’re thinking? Opponent Modelling in an RTS game (2020) (4)
Re-determinizing MCTS in Hanabi (2019) (3)
AI and Wargaming (2020) (3)
Retrospective: using cache memory to reduce processor-memory traffic (1998) (3)
Using Speculative Push to Reduce Communication Latencies in Critical Sections (2000) (2)
When does computer architecture education begin?: assembly language as computer architecture (1996) (2)
The Design of a Queue-Based Vector Supercomputer (1986) (2)
Weighting NTBEA for Game AI Optimisation (2020) (2)
Metagame Autobalancing for Competitive Multiplayer Games (2020) (2)
Visualizing Multiplayer Game Spaces (2022) (2)
Comments on "A Massive Memory Machine" (1986) (2)
Fingerprinting Tabletop Games (2021) (1)
Reply to David R. Cheriton's, Pat Boyle's, and Gert A. Slavenburg's “Comments on 'Coherency for multiprocessor virtual addressed caches' by James R. Goodman” (1988) (1)
Hypertree: A Multiprocessor Interconnection (1981) (1)
Two square root algorithms utilizing multiplication as the iterative operator (1969) (1)
Memory-centric architectures: why and perhaps what (1997) (1)
Instruction CacheReplacement Policies andOrganizations (1985) (1)
VLSI Considerations that Influence Data Flow Architecture (1982) (1)
Compiler and Operating System Requirements for 16-Bit Microcomputer Architectures: Intel 8086, Zilog Z8000 and Motorola MC68000 (1981) (1)
Following the Leader in Multiplayer Tabletop Games (2023) (0)
Efficient Synchronization : Let Them Eat QOLB 1 (1997) (0)
Skirting Amdahl ’ s Law : Using SPSD Execution with Optical Interconnects (2007) (0)
Chaitin's Graph Coloring Algorithm (2007) (0)
INSTRUCTION-BASED PREDICTION FOR MIGRATORY SHARING IN SHARED-MEMORY MULTIPROCESSORS (2000) (0)
5 a Set-theoretic Reformulation of the Inconsistency (1995) (0)
7-1-1992 Report of the Purdue Workshop on Grand Challenges in Computer Architecture ! for the Support of High Performance Computing (2013) (0)
Billion-Transistor Architectures: and Back Again (2004) (0)
o f the Purdue W o rkshop on Grand Challenges in Computer Architecture for the Support o f High Performance Computing * (1992) (0)
MultiTree MCTS in Tabletop Games (2022) (0)

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