Jan M. Rabaey

Q: What Schools Are Affiliated With Jan M. Rabaey

Jan M. Rabaey is affiliated with the following schools: University of California, Berkeley, KU Leuven, Stanford University

Jan M. Rabaey's AcademicInfluence.com Rankings

Jan M. Rabaey

Engineering

#1443

World Rank

#2126

Historical Rank

Electrical Engineering

#262

World Rank

#300

Historical Rank

engineering Degrees

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Engineering

Jan M. Rabaey's Degrees

PhD Electrical Engineering Stanford University
Masters Electrical Engineering Stanford University
Bachelors Electrical Engineering KU Leuven

Why Is Jan M. Rabaey Influential?

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According to Wikipedia, Jan M. Rabaey is an academic and engineer who is Professor Emeritus and Professor in the Graduate School of in the Electrical Engineering and Computer Sciences at the University of California, Berkeley. He also serves as the CTO of the Systems Technology Co-Optimization division at imec, Belgium.

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Jan M. Rabaey's Published Works

Number of citations in a given year to any of this author's works

Total number of citations to an author for the works they published in a given year. This highlights publication of the most important work(s) by the author

Published Works

A study of low level vibrations as a power source for wireless sensor nodes (2003) (2768)
Digital Integrated Circuits: A Design Perspective (1995) (2149)
Energy aware routing for low energy ad hoc sensor networks (2002) (1739)
PicoRadio Supports Ad Hoc Ultra-Low Power Wireless Networking (2000) (1222)
Digital Integrated Circuits (2003) (1084)
Improving power output for vibration-based energy scavengers (2005) (1056)
Robust Positioning Algorithms for Distributed Ad-Hoc Wireless Sensor Networks (2002) (1016)
Low power design methodologies (1996) (871)
System-Level Design: Orthogonalization of Concerns and Platform-Based Design (2001) (794)
Location in distributed ad-hoc wireless sensor networks (2001) (694)
Lightweight time synchronization for sensor networks (2003) (532)
Energy Scavenging for Wireless Sensor Networks: with Special Focus on Vibrations (2012) (502)
Optimizing power using transformations (1995) (479)
Power Sources for Wireless Sensor Networks (2004) (468)
PicoRadios for wireless sensor networks: the next challenge in ultra-low power design (2002) (423)
Comparison of Methods (2004) (416)
System-level design: orthogonalization of concerns andplatform-based design (2000) (415)
Ultralow-Power Design in Near-Threshold Region (2010) (413)
Addressing the system-on-a-chip interconnect woes through communication-based design (2001) (405)
Low Power Design Essentials (2009) (398)
Wireless Recording in the Peripheral Nervous System with Ultrasonic Neural Dust (2016) (372)
Energy scavenging for wireless sensor networks (2003) (357)
Architectural power analysis: The dual bit type method (1995) (352)
Distributed algorithms for transmission power control in wireless sensor networks (2003) (342)
Low-swing on-chip signaling techniques: effectiveness and robustness (2000) (329)
Low power distributed MAC for ad hoc sensor radio networks (2001) (308)
A 52 $\mu$ W Wake-Up Receiver With $-$ 72 dBm Sensitivity Using an Uncertain-IF Architecture (2009) (296)
Fast prototyping of datapath-intensive architectures (1991) (290)
A Minimally Invasive 64-Channel Wireless μECoG Implant (2015) (286)
Digital integrated circuits: a design perspective / Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic (2003) (286)
Power-efficient rendez-vous schemes for dense wireless sensor networks (2004) (275)
Modeling within-die spatial correlation effects for process-design co-optimization (2005) (242)
SRAM leakage suppression by minimizing standby supply voltage (2004) (240)
Power Aware Design Methodologies (2002) (240)
A 2GHz 52 μW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture (2008) (219)
A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$ , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply (2012) (206)
Cathedral-II: A Silicon Compiler for Digital Signal Processing (1986) (206)
A wearable biosensing system with in-sensor adaptive machine learning for hand gesture recognition (2020) (203)
A 300-μW 1.9-GHz CMOS oscillator utilizing micromachined resonators (2003) (200)
HYPER-LP: a system for power minimization using architectural transformations (1992) (199)
Physical principles for scalable neural recording (2013) (193)
Power conscious CAD tools and methodologies: a perspective (1995) (193)
Neural Dust: An Ultrasonic, Low Power Solution for Chronic Brain-Machine Interfaces (2013) (188)
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments (2000) (174)
PicoRadio: Ad-hoc wireless networking of ubiquitous low-energy sensor/monitor nodes (2000) (172)
Energy-Efficient Abundant-Data Computing: The N3XT 1,000x (2015) (165)
A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing (2016) (164)
A 1.9GHz RF Transmit Beacon using Environmentally Scavenged Energy (2003) (163)
The design of a low energy FPGA (1999) (161)
Low-energy embedded FPGA structures (1998) (155)
A Fully-Integrated, Miniaturized (0.125 mm²) 10.5 µW Wireless Neural Sensor (2013) (155)
Reconfigurable processing: the solution to low-power programmable DSP (1997) (150)
Exploring Hyperdimensional Associative Memory (2017) (149)
A 65 μW, 1.9 GHz RF to digital baseband wakeup receiver for wireless sensor nodes (2007) (147)
A 400 /spl mu/W-RX, 1.6mW-TX super-regenerative transceiver for wireless sensor networks (2005) (146)
Power estimation for high level synthesis (1993) (143)
Optimizing resource utilization using transformations (1991) (141)
Model validation of untethered, ultrasonic neural dust motes for cortical recording (2015) (135)
A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates (2018) (134)
Activity-sensitive architectural power analysis (1996) (133)
Scheduling of DSP programs onto multiprocessors for maximum throughput (1993) (124)
A 0.013mm2 5μW DC-coupled neural signal acquisition IC with 0.5V supply (2011) (123)
Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition (2016) (123)
A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths (1992) (121)
An integrated CAD system for algorithm-specific IC design (1989) (116)
When does opportunistic routing make sense? (2005) (113)
DSP specification using the Silage language (1990) (110)
Ultra-Low Power Wireless Technologies for Sensor Networks (2007) (110)
An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks (2005) (110)
A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing (2000) (110)
High-Dimensional Computing as a Nanoscalable Paradigm (2017) (108)
Performance optimization using template mapping for datapath-intensive high-level synthesis (1996) (107)
Low-swing interconnect interface circuits (1998) (106)
An ultra-low power MEMS-based two-channel transceiver for wireless sensor networks (2004) (102)
Behavioral Level Power Estimation and Exploration (1997) (102)
A 0 . 013 mm � , 5 � W , DC-Coupled Neural Signal Acquisition IC With 0 . 5 V Supply (2011) (100)
The Swarm at the Edge of the Cloud (2015) (99)
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study (2018) (97)
Efficient Biosignal Processing Using Hyperdimensional Computing: Network Templates for Combined Learning and Classification of ExG Signals (2019) (96)
Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition (2016) (92)
An implantable 700μW 64-channel neuromodulation IC for simultaneous recording and stimulation with rapid artifact recovery (2017) (90)
Low-Energy FPGAs - Architecture and Design (2001) (90)
Design methodology for PicoRadio networks (2001) (90)
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System (2001) (89)
The Energy-per-Useful-Bit Metric for Evaluating and Optimizing Sensor Network Physical Layers (2006) (88)
Vlsi Signal Processing II (1986) (87)
Far-Field RF Wireless Power Transfer with Blind Adaptive Beamforming for Internet of Things Devices (2017) (86)
An efficient microcode compiler for application specific DSP processors (1990) (85)
Antenna applications corner: Miniature implantable and wearable on-body antennas: Towards the new era of wireless body-centric systems (2014) (85)
Classification and Recall With Binary Hyperdimensional Computing: Tradeoffs in Choice of Density and Mapping Characteristics (2018) (83)
A study of energy consumption and reliability in a multi-hop sensor network (2004) (81)
A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications (2000) (80)
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation (2015) (79)
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS (2012) (78)
Miniature implantable and wearable on-body antennas: towards the new era of wireless body-centric systems [antenna applications corner] (2014) (77)
An ultra-low-power power management IC for energy-scavenged Wireless Sensor Nodes (2008) (76)
Maximally fast and arbitrarily fast implementation of linear computations (circuit layout CAD) (1992) (75)
Limitations and challenges of computer-aided design technology for CMOS VLSI (2001) (75)
AN ULTRA-LOW POWER AND DISTRIBUTED ACCESS PROTOCOL FOR BROADBAND WIRELESS SENSOR NETWORKS (2001) (74)
HYPER: an interactive synthesis environment for high performance real time applications (1989) (74)
An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier (2018) (73)
Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS (2007) (71)
Memory Estimation for High Level Synthesis (1994) (69)
Early power exploration—a World Wide Web application (1996) (68)
Standby supply voltage minimization for deep sub-micron SRAM (2005) (68)
On the performance of geographical routing in the presence of localization errors [ad hoc network applications] (2005) (68)
A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder (1995) (67)
Exploiting regularity for low-power design (1996) (67)
An RF ToF Based Ranging Implementation for Sensor Networks (2006) (66)
Estimating implementation bounds for real time DSP application specific circuits (1994) (63)
An Integrated Automated Layout Generation System for DSP Circuits (1985) (63)
Evaluation of a Low-Power Reconfigurable DSP Architecture (1998) (63)
A Service-Based Universal Application Interface for Ad-hoc Wireless Sensor Networks (2003) (62)
The swarm at the edge of the cloud - A new perspective on wireless (2011) (61)
Practical implementation of a general computer aided design technique for switched capacitor circuits (1980) (61)
A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs (1989) (61)
Overcoming untuned radios in wireless networks with network coding (2006) (59)
Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play? (2000) (58)
Powering and communicating with mm-size implants (2011) (57)
A Service-Based Universal Application Interface for Ad Hoc Wireless Sensor and Actuator Networks (2005) (57)
SAR reduction and link optimization for mm-size remotely powered wireless implants using segmented loop antennas (2011) (57)
Hyperdimensional Computing for Blind and One-Shot Classification of EEG Error-Related Potentials (2020) (56)
24.1 A miniaturized 64-channel 225μW wireless electrocorticographic neural sensor (2014) (56)
A class A/B low power amplifier for wireless sensor networks (2004) (55)
A 46% Efficient 0.8dBm Transmitter for Wireless Sensor Networks (2006) (55)
Joint optimization of a protocol stack for sensor networks (2004) (54)
Adaptive sleep discipline for energy conservation and robustness in dense sensor networks (2004) (53)
Activity-sensitive architectural power analysis for the control path (1995) (53)
Backscattering Neural Tags for Wireless Brain-Machine Interface Systems (2015) (53)
Research accelerator for multiple processors (2006) (53)
Low-power architectural synthesis and the impact of exploiting locality (1996) (51)
Design guidance in the power dimension (1995) (51)
PicoCube: A 1cm3 sensor node powered by harvested energy (2008) (51)
Ultra-low-power design (2006) (50)
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression (2013) (50)
A 300µmW 1.9GHz CMOS oscillator utilizing micromachined resonators (2002) (50)
A low-power, lightweight unit to provide ubiquitous information access application and network support for InfoPad (1996) (50)
A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture (2016) (49)
UML and Platform-based Design (2003) (49)
13.5 A −97dBm-sensitivity interferer-resilient 2.4GHz wake-up receiver using dual-IF multi-N-Path architecture in 65nm CMOS (2015) (47)
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration (2018) (46)
Hyperdimensional computing for noninvasive brain-computer interfaces: Blind and one-shot classification of EEG error-related potentials (2017) (46)
Time, frequency, and z-domain modified nodal analysis of switched-capacitor networks (1981) (45)
Modeling and analysis of opportunistic routing in low traffic scenarios (2005) (45)
An Ultra-Low-Power Power Management IC for Wireless Sensor Nodes (2007) (44)
Software Architecture of the Infopad System (1994) (44)
A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms (1993) (44)
Exploring Very Low-Energy Logic: A Case Study (2007) (44)
System-level design guidance using algorithm properties (1994) (43)
A Power-Managed Protocol Processor for Wireless Sensor Networks (2006) (42)
Does proper coding make single hop wireless sensor networks reality: the power consumption perspective (2005) (42)
Dynamic amplifier for m.o.s. technology (1979) (41)
APPLICATION AND NETWORK SUPPORT FOR INFOPAD1 (1996) (41)
Processors for mobile applications (2000) (41)
A 1mm3 2Mbps 330fJ/b transponder for implanted neural sensors (2011) (40)
Embedded System Design using UML and Platforms (2003) (39)
An integrated data-link energy model for wireless sensor networks (2004) (39)
The Search for Alternative Computational Paradigms (2008) (39)
Hyperdimensional Computing for Text Classification (2016) (39)
A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio (2016) (38)
Low-power design of memory intensive functions (1994) (38)
InfoNet: The networking infrastructure of InfoPad (1995) (38)
Reliable Next-Generation Cortical Interfaces for Chronic Brain–Machine Interfaces and Neuroscience (2017) (38)
The adjoint switched capacitor network and its application to frequency, noise and sensitivity analysis (1981) (38)
A sub-100 /spl mu/W 1.9-GHz CMOS oscillator using FBAR resonator (2005) (37)
Energy Harvesting - A Systems Perspective (2007) (37)
Altruists in the PicoRadio sensor network (2002) (37)
Vector Symbolic Architectures as a Computing Framework for Nanoscale Hardware (2021) (37)
Architectural strategies for an application-specific synchronous multiprocessor environment (1988) (37)
Design of Wireless Links to Implanted Brain–Machine Interface Microelectronic Systems (2012) (37)
Resource driven synthesis in the HYPER system (1990) (36)
Millimetro: mmWave retro-reflective tags for accurate, long range localization (2021) (36)
CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems (1988) (36)
A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects (2012) (36)
A partitioning scheme for optimizing interconnect power (1997) (36)
Challenges and Solutions for Late- and Post-Silicon Design (2008) (35)
Wireless beyond the third generation-facing the energy challenge (2001) (35)
Low power operating system for heterogeneous wireless communication system (2003) (34)
QuantHD: A Quantization Framework for Hyperdimensional Computing (2020) (34)
Embedding Mixed-Signal Design in Systems-on-Chip (2006) (34)
Low-Power Sparse Hyperdimensional Encoder for Language Recognition (2017) (34)
High level synthesis for reconfigurable datapath structures (1993) (34)
21.4 A 400∝W-RX, 1.6mW-TX Super- Regenerative Transceiver for Wireless Sensor Networks (2005) (33)
SRAM supply voltage scaling: A reliability perspective (2009) (33)
A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP (1995) (33)
Low-power silicon architectures for wireless communications (2000) (33)
A Programmable Hyper-Dimensional Processor Architecture for Human-Centric IoT (2019) (32)
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic (2009) (32)
Ultrasonic beamforming system for interrogating multiple implantable sensors (2015) (32)
Wireless channel characterization for mm-size neural implants (2010) (31)
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's (1998) (31)
Analysis of wireless powering of mm-size neural recording tags in RFID-inspired wireless brain-machine interface systems (2013) (31)
A Revenue Enhancing Stackelberg Game for Owners in Opportunistic Spectrum Access (2008) (31)
Super-Regenerative Transceiver for Wireless Sensor Networks (2004) (29)
Modeling within-field gate length spatial variation for process-design co-optimization (2005) (29)
The TerraSwarm Research Center (TSRC) (A White Paper) (2012) (29)
Low power synchronization for wireless sensor network modems (2005) (29)
Smart Energy Distribution and Consumption: Information Technology as an Enabling Force (2001) (28)
Heterogeneous reconfigurable systems (1997) (28)
Instruction set mapping for performance optimization (1993) (28)
Printed, flexible, compact UHF-RFID sensor tags enabled by hybrid electronics (2020) (28)
Challenges and opportunities in broadband and wireless communication designs (2000) (28)
Self-Sovereign Identity for IoT environments: A Perspective (2020) (28)
Wireless protocols design: challenges and opportunities (2000) (28)
An Integrated CAD Environment for Low-Power Design (1996) (28)
VLSI design and implementation fuels the signal-processing revolution (1998) (27)
An integrated system for rapid prototyping of high performance algorithm specific data paths (1992) (27)
Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches (2014) (27)
“EChO” Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions (2013) (27)
Low power design of memory intensive functions. Case study: vector quantization (1994) (27)
Cathedral II: A Synthesis and Module Generation System for Multiprocessor Systems on a Chip (1987) (27)
Yield optimization with energy-delay constraints in low-power digital circuits (2003) (26)
Designing wireless protocols: methodology and applications (2000) (26)
A large-vocabulary real-time continuous-speech recognition system (1989) (26)
Maximizing the throughput of high performance DSP applications using behavioral transformations (1994) (26)
Robust Positioning Algorithms for Distrib uted (26)
High level synthesis techniques for efficient built-in-self-repair (1993) (26)
RFID transceiver for wireless powering brain implanted microelectrodes and backscattered neural data collection (2014) (24)
A 100 /spl mu/W, 1.9GHz oscillator with fully digital frequency tuning (2005) (24)
Interprocessor communication in synchronous multiprocessor digital signal processing chips (1989) (24)
A methodology for guided behavioral-level optimization (1998) (24)
Retargetable estimation scheme for DSP architecture selection (2000) (23)
Measurement of Wireless Link for Brain–Machine Interface Systems Using Human-Head Equivalent Liquid (2013) (23)
Fundamental Data Retention Limits in SRAM Standby Experimental Results (2008) (23)
Fast implementation of recursive programs using transformations (1992) (23)
A low power localization architecture and system for wireless sensor networks (2004) (23)
The Roadmap to Disappearing Electronics and Ambient Intelligence (2006) (23)
Workloads of the Future (2008) (23)
Digital Integrated Circuits: A Design Perspective By Jan M. Rabaey (2003) (23)
Algorithm Selection: A Quantitative Computation-intensive Optimization Approach (1994) (23)
Receiver initiated rendezvous schemes for sensor networks (2005) (22)
Pipelining: just another transformation (1992) (21)
A 1 V 250 KPPS 90 NM CMOS pulse based transceiver for CM-range wireless communication (2007) (21)
Reconfigurable platform design for wireless protocol processors (2001) (21)
The human intranet — Where swarms and humans meet (2015) (20)
Beamforming approaches for untethered, ultrasonic neural dust motes for cortical recording: A simulation study (2014) (20)
A prototype user interface for a mobile multimedia terminal (1995) (19)
A brand new wireless day (2008) (19)
A Comparative Study of On-Body Radio-Frequency Links in the 420 MHz–2.4 GHz Range (2018) (18)
Design at the end of the silicon roadmap (2005) (18)
Generalized Learning Vector Quantization for Classification in Randomized Neural Networks and Hyperdimensional Computing (2021) (18)
Sensitivity Analysis for AM Detectors (2008) (18)
Low-power silicon architecture for wireless communications: embedded tutorial (2000) (18)
A 1.5MS/s 6-bit ADC with 0.5V supply (2006) (18)
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM (2007) (18)
Ultra Low Power CORDIC Processor for Wireless Communication Algorithms (2004) (18)
Algorithm and Architectural Level Methodologies for Low Power (1996) (17)
On the Total Power Capacity of Regular-LDPC Codes With Iterative Message-Passing Decoders (2015) (17)
An Intelligent Module Generator Environment (1986) (17)
A 100KS/s 65dB DR Σ — Δ ADC with 0.65V supply voltage (2007) (17)
Design and optimization of mm-size implantable and wearable on-body antennas for biomedical systems (2014) (17)
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler (1990) (17)
A fully-integrated 10.5µW miniaturized (0.125mm2) wireless neural sensor (2012) (17)
An integrated, low power localization system for sensor networks (2004) (16)
Integrated circuits for a real-time large-vocabulary continuous speech recognition system (1991) (16)
An efficient microcode compiler for custom multiprocessor DSP-systems (1987) (16)
A multiprocessor DSP system using PADDI-2 (1998) (16)
Swarm OS control plane: An architecture proposal for heterogeneous and organic networks (2015) (16)
ZUMA: A platform for smart-home environmnents (2006) (16)
Exploring the Power Dimension (1996) (16)
Hardware selection and clustering in the HYPER synthesis system (1992) (15)
Massively parallel wireless reconfigurable processor architecture and programming (2003) (15)
Fabrication and Characterization of Flexible Spray-Coated Antennas (2018) (15)
Active RFID: Perpetual wireless communications platform for sensors (2012) (15)
Beyond Sensor Networks: ZUMA Middleware (2007) (15)
Antenna design for implanted tags in wireless brain machine interface system (2013) (14)
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation (2008) (14)
Scheduling Algorithms For Hierarchical Data Control Flow Graphs (1992) (14)
A Data-driven Architecture For Rapid Prototyping Of High Throughput Dsp Algorithms (1992) (14)
Ultra-Low Power Integrated Wireless Nodes for Sensor and Actuator Networks (2005) (14)
Exploring the power dimension [in digital CMOS] (1996) (14)
A Dynamic Design Estimation And Exploration Environment (1997) (14)
Complexity Estimation for Real Time Application Specific Circuits (1991) (14)
A Dual-Resolution Wavelet-Based Energy Detection Spectrum Sensing for UWB-Based Cognitive Radios (2018) (14)
Ultra-low-voltage robust design issues in deep-submicron CMOS (2004) (14)
ZUMA: A platform for smart-home environments the case for infrastructure (2006) (13)
A compiler for multiprocessor DSP implementation (1992) (13)
DIANA as a mixed-mode simulation for MOSLSI sampled-data circuits (1980) (13)
A 10b 600MS/s multi-mode CMOS DAC for multiple Nyquist zone operation (2011) (13)
An Efficient Microcode-Compiler for Custom DSP-Processors (2003) (12)
Design of wireless portable systems (1995) (12)
A 200Mb/s inductively coupled wireless transcranial transceiver achieving 5e-11 BER and 1.5pJ/b transmit energy efficiency (2018) (12)
A general and efficient noise analysis technique for switched capacitor filters (1983) (12)
A low-energy chip-set for wireless intercom (2003) (12)
Technologies for an Autonomous Wireless Home Healthcare System (2009) (12)
A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms (2006) (12)
A Bio-Inspired Analog Gas Sensing Front End (2017) (11)
A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios (2018) (11)
Algorithm selection: a quantitative optimization-intensive approach (1999) (11)
Statistical Analysis and Optimization of Asynchronous Digital Circuits (2012) (11)
The Pleiades Architecture (2002) (11)
Developing a Multidimensional Synchronous Dataflow Domain in Ptolemy (1994) (11)
Wireless beyond the third generation wireless beyond the third generation: facing the energy challenge (2001) (11)
Power minimization in DSP application specific systems using algorithm selection (1995) (11)
Parallel DSP with memory and I/O processors (1998) (11)
Computer Aided Distortion Analysis of Switched Capacitor Filters in the Frequency Domain (1982) (11)
A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation (2014) (11)
Low Voltage Analog to Digital Converter Design in 90nm CMOS (2007) (10)
WAND: A 128-channel, closed-loop, wireless artifact-free neuromodulation device (2017) (10)
Ultra low-energy transceivers for wireless sensor networks (2002) (10)
Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis (2008) (10)
Specification and support for multidimensional DSP in the SILAGE language (1994) (10)
Optimized design of a Human Intranet network (2017) (10)
Brain-machine interfaces as the new frontier in extreme miniaturization (2011) (10)
Analysis of Interference Effects in MB-OFDM UWB Systems (2008) (10)
Equalization for intracortical microstimulation artifact reduction (2013) (10)
Antenna design for wireless electrocorticography (2012) (10)
A ( 6 x 3 ) cm 2 Self-Contained Energy-Scavenging Wireless Sensor Network Node (2004) (9)
Linearity analysis of CMOS passive mixer (2011) (9)
An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements (2012) (9)
A 200-Mb/s Energy Efficient Transcranial Transmitter Using Inductive Coupling (2019) (9)
Predicting performance potential of modern DSPs (2000) (9)
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression (2012) (9)
Powering and communication for OMNI: A distributed and modular closed-loop neuromodulation device (2016) (9)
A Highly Energy-Efficient Hyperdimensional Computing Processor for Wearable Multi-Modal Classification (2021) (9)
Adaptive Body Area Networks Using Kinematics and Biosignals (2018) (9)
Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata (2021) (9)
The adjoint switched capacitor network and its applications (1980) (9)
SRAM Cell Optimization for Ultra-Low Power Standby (2006) (9)
Electromagnetic modelling and measurement of antennas for wireless brain-machine interface systems (2013) (9)
Exploring the Architecture and Algorithmic Space for Signal Processing Applications (1993) (8)
Is "Network" the next "Big Idea" in design? (2006) (8)
Choosing “green” codes by simulation-based modeling of implementations (2012) (8)
Energy Efficient Heartbeat-Based MAC Protocol for WBAN Employing Body Coupled Communication (2020) (8)
Beyond the horizon: The next 10x reduction in power - Challenges and solutions (2011) (8)
Brain-machine interfaces as the new frontier in extreme miniaturization (2011) (8)
Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput (1992) (8)
System-level power estimation and optimization—challenges and perspectives (1997) (8)
System-on-Chip-Challenges in the Deep-Sub-Micron Era (2005) (8)
Information based design environment (1995) (8)
Memory-Efficient, Limb Position-Aware Hand Gesture Recognition using Hyperdimensional Computing (2021) (8)
Short distance wireless and its opportunities (2006) (8)
Swarm os control plane: an architecture proposal for heterogeneous and organic networks (2015) (8)
A 2.7- $\mu$ W Neuromodulation AFE With 200 mVpp Differential-Mode Stimulus Artifact Canceler Including On-Chip LMS Adaptation (2018) (7)
Synthesis for real time systems: Solutions and challenges (1995) (7)
Analysis of Contraction Effort Level in EMG-Based Gesture Recognition Using Hyperdimensional Computing (2019) (7)
A unified data-link energy model for wireless sensor networks (2004) (7)
Fundamental Redundancy Versus Power Trade-Off in Standby SRAM (2007) (7)
Human-Centric Computing (2020) (7)
A CMOS switched-capacitor fractional bandgap reference (2012) (7)
A reconfigurable multiprocessor IC for prototyping of real-time data paths (1992) (7)
Optimizing throughput and resource utilization using pipelining: Transformation based approach (1994) (7)
A fully integrated, 300pJ/bit, dual mode wireless transceiver for cm-range interconnects (2010) (7)
Architecture for web-based image processing (1997) (7)
Multi-Dimensional Circuit and Micro-Architecture Level Optimization (2007) (7)
Homo technologicus (2018) (7)
Toward standardized localization service (2016) (7)
Modelling and simulation techniques for highly integrated, low-power wireless sensor networks (2007) (7)
A design methodology for low-power heterogeneous reconfigurable digital signal processors (2001) (7)
Ultra-Low Power Signal Processing [DSP Forum] (2010) (6)
A 1Gb/s energy efficient triple-channel UWB-based cognitive radio (2015) (6)
Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks (2022) (6)
PICORADIO: COMMUNICATION/COMPUTATION PICONODES FOR SENSOR NETWORKS (2003) (6)
Design Without Borders (2007) (6)
Energy Scavenging in Support of Ambient Intelligence: Techniques, Challenges, and Future Directions (2006) (6)
Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel) (1996) (6)
Wireless powering and data communication for neural implantable electrodes (2013) (6)
A 2.2mW CMOS LNA for 6–8.5GHz UWB receivers (2010) (6)
Isolator-Less Near-Field RFID Reader for Sub-Cranial Powering/Data Link of Millimeter-Sized Implants (2018) (6)
Research challenges in wireless multimedia (1994) (6)
Concurrency characteristics in DSP programs (1994) (6)
A 3.1–10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers (2015) (6)
A computer-aided design methodology for mapping DSP-algorithms onto custom multiprocessor architectures (1986) (6)
Design Solutions And Challenges For Low Power Systems (1994) (6)
Design and Optimization of an MB-OFDM Ultra-Wideband Receiver Front-End (2008) (6)
DIANA-SC : A Complete CAD system for switched capacitor filters (1981) (6)
Maximally and arbitrarily fast implementation of linear andfeedback linear computations (2000) (6)
Mobile Communications: Technology, Tools Applications, Authentication and Security (1996) (6)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors (2018) (6)
Distributed algorithms to maximize the lifetime of wireless sensor networks (2005) (5)
Selection and Aggregation of Location Information Provisioning Services (2017) (5)
Target architectures in the CATHEDRAL synthesis systems: objectives and impact (1989) (5)
Vector Symbolic Architectures as a Computing Framework for Emerging Hardware (2022) (5)
Automatic 3D Design for Efficiency Optimization of a Class E Power Amplifier (2018) (5)
DIANA.SC — a versatile top-down analysis tool for switched-capacitor circuits (1983) (5)
A low-power mixed-signal baseband system design for wireless sensor networks (2005) (5)
A 3–10mW, 3.1–10.6GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios (2015) (5)
Energy detection technique for ultra-low power high sensitivity wake-up receiver (2013) (5)
Interference robust self-mixing UWB systems using phase-domain spreading (2011) (5)
Sparse-Push: Communication- & Energy-Efficient Decentralized Distributed Learning over Directed & Time-Varying Graphs with non-IID Datasets (2021) (5)
Proceedings of the 55th Annual Design Automation Conference (1998) (5)
Evolution of Microsystem Design (1989) (5)
Architectural Power The Dual Bit Type Method (1995) (5)
Locationing and Timing Synchronization Services in Ambient Intelligence Networks (2005) (5)
Adaptive EMG-based hand gesture recognition using hyperdimensional computing (2019) (5)
Feasability of On-Body Backscattering in the UHF-RFID Band using Screen-Printed Dipole Antennas (2019) (4)
Analyzing the Performance of WBAN Links during Physical Activity Using Real Multi-Band Sensor Nodes (2021) (4)
Isolator-less near-field RFID reader for sub-cranial powering/data link of mm-sized implants (2017) (4)
Digital energy detection for OOK demodulation in ultra-low power radios (2011) (4)
Hyperdimensional Computing Nanosystem (2018) (4)
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic (2008) (4)
Frequency offset estimation with improved convergence time and energy consumption (2004) (4)
Analysis of multidimensional DSP specifications (1996) (4)
Towards Approaching Total-Power-Capacity: Transmit and Decoding Power Minimization for LDPC Codes (2015) (4)
Ultralow-Power Radio Frequency Beamformer Using Transmission-Line Transformers and Tunable Passives (2019) (4)
Design Methodology and Tools for Wireless System Design (1998) (4)
Data communication and power system for wireless neural recording (2013) (4)
Information theory meets circuit design: Why capacity-approaching codes require more chip area and power (2011) (4)
Coding for sensor networks using untuned radios (2005) (4)
The Impact of Width Granularity on FinFET Latch Operation and Optimization (2004) (4)
Connectivity Brokerage: From coexistence to collaboration (2010) (4)
Highly Integrated Ultra-Low Power RF Transceivers for Wireless Sensor Networks (2004) (4)
An integrated framework for optimizing transformations (1996) (4)
Behavioral level guidance using property-based design characterization (1996) (4)
Guest Editorial: Alternative Computing and Machine Learning for Internet of Things (2017) (4)
The standby power challenge: Wake-up receivers to the rescue (2009) (3)
Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations (1993) (3)
Heartbeat-Based Synchronization Scheme for the Human Intranet: Modeling and Analysis (2020) (3)
SLSR: A flexible middleware localization service architecture (2017) (3)
Hardware for Hidden Markov-Model-Based, Large-Vocabulary Real-Time Speech Recognition (1990) (3)
A Global QoS Management for Wireless Network (1996) (3)
Early power exploration-a World Wide Web application [high-level design] (1996) (3)
Towards TRUE human-centric computation (2018) (3)
Wafer Scale Distributed Radio (2009) (3)
Piezoelectric Converter Design (2004) (3)
Design without Borders - A Tribute to the Legacy of A. Richard Newton (2007) (3)
The Human Intranet--Where Swarms and Humans Meet (2015) (3)
An overview of CAD techniques for switched capacitor networks (1981) (3)
Energy-Aware Routing and Data Funneling in Sensor Networks (2004) (3)
An energy-conscious exploration methodology for reconfigurable DSPs (1998) (3)
Experiences with automatic generation of audio band digital signal processing circuits (1986) (3)
Traveling the Wild Frontier of Ultra Low-Power Design (2005) (3)
Automatic Generation of Digital Signal Processing Circuits (1987) (3)
Synthesis of Datapath Architectures (1992) (3)
On unlimited parallelism of DSP arithmetic computations (1993) (3)
A pictorial derivation of the signal processing mechanism of multiphase switched capacitor networks (1982) (3)
Capacitive Body-Coupled Communication in the 400-500 MHz Frequency Band (2019) (3)
Human-centric computing — The case for a Hyper-Dimensional approach (2017) (3)
Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI (2021) (3)
A 13.2 mW 1.9 GHz interpolative BAW-based VCO for miniaturized RF frequency synthesis (2009) (2)
Wireless Power Transfer to Randomly Distributed Implants via Homogeneous Magnetic Fields (2019) (2)
A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS (2022) (2)
Ultra Low Power/Voltage Design (2009) (2)
Advances in implantable and wearable antennas for wireless brain-machine interface systems (2014) (2)
The Conceptual-Level Design Approach to Complex Systems (1998) (2)
More Moore: foolish, feasible, or fundamentally different? (2008) (2)
On the Role of Hyperdimensional Computing for Behavioral Prioritization in Reactive Robot Navigation Tasks (2022) (2)
Wearable and Implantable Antennas for Wireless Body-Centric Sensing Systems (2013) (2)
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS (2012) (2)
Towards Wireless Flexible Printed Wearable Sensors (2019) (2)
Application of canonical polyadic decomposition for ultrasonic interrogation of neural dust grids: a simulation study (2016) (2)
What's the next EDA driver? (2002) (2)
Nanotechnology-inspired Information Processing Systems of the Future (2020) (2)
Low Power Design Methodologies and Flows (2009) (2)
Wireless testing of ink-jet printed mm-size gold implant antennas for Brain-Machine Interfaces (2014) (2)
Optimizing Power @ Standby – Memory (2009) (2)
A Neuro-Inspired Spike Pattern Classifier (2018) (2)
Content Management and Replication in the SNSP: A Distributed Service-Based OS for Sensor Networks (2008) (2)
A Brain-Inspired Hierarchical Reasoning Framework for Cognition-Augmented Prosthetic Grasping (2021) (2)
A low-overhead approach for self-sovereign identity in IoT (2021) (2)
A unified theory for the computer aided analysis of general switched capacitor networks (1980) (2)
Vibration Sources and Conversion Model (2004) (2)
General datapath, controller and inter-communication architectures for the creation of a dedicated multi-processor environment (1986) (2)
Neural Dust: An Untethered Approach to Chronic Brain-Machine Interfaces (2014) (2)
Impedance modeling of the intracortical microelectrode for a reliable design of a brain activity recording system (2014) (2)
Optimizing Power @ Design Time – Circuit-Level Techniques (2009) (2)
Hybrid reconfigurable processors-the road to low-power consumption (1998) (2)
Operating system support for mobile robot swarms (2015) (2)
Sampling modulation: An energy efficient novel feature extraction for biosignal processing (2016) (2)
On the Simulation of Switched Capacitor Filters and Convertors using the DIANA Program (1979) (2)
Reconfigurable Processors — The Road to Flexible Power-Aware Computing (2002) (2)
A Highly Energy-Efficient Hyperdimensional Computing Processor for Biosignal Classification (2022) (2)
A 0.2 to 1.7 GHz low-jitter integer-N QPLL for power efficient direct digital RF modulator (2013) (1)
Computing with Hypervectors for Efficient Speaker Identification (2022) (1)
Experiences and challenges in system design (1998) (1)
Maximally Fast and Arbitrarily Fast Hardwar e Efficient Implementation of Linear and Feedback Linear Computations 1 (1996) (1)
Analysis of Ultralow Power Radio Frequency Beamforming Using Transmission-Line Transformers and Tunable Passives (2022) (1)
A VLSI grammar processing subsystem for a real time large vocabulary continuous speech recognition system (1990) (1)
Efficient throughput optimization of feedback linear computations using generalized Horner's scheme (1995) (1)
Analysis of non-ideal sc circuits including resistances and op amp poles (1981) (1)
Wireless platforms: GOPS for cents and MilliWatts (2005) (1)
Chapter 8 Optimizing Power @ Standby – Circuits and Systems (2009) (1)
Design in the Late-and Post-Silicon Eras (2009) (1)
Chapter 5 UML AND PLATFORM-BASED DESIGN (2003) (1)
Special Issue on Sensors and Interfaces for Mobile Healthcare (2016) (1)
Brain-machine interfaces — The core of the human intranet (2015) (1)
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996 (1996) (1)
Short Distance Wireless, Dense Networks, and Their Opportunities (2007) (1)
A low-leakage parallel CRC generator for ultra-low power applications (2011) (1)
A systems approach to computing in beyond CMOS fabrics (2017) (1)
Invited Address: Hybrid Reconfigurable Processors - The Road to Low-Power Consumption (1998) (1)
Next generation wireless-multimedia devices — who is up for the challenge? (2008) (1)
Panel: what's the next eda driver? (2002) (1)
Short Range Pulse Based Inductive Transceiver (2006) (1)
A Fully-Digital 0.1-to-27 Mb/s ULV 450 MHz Transmitter with sub-100 $\mu \mathrm{W}$ Power Consumption for Body-Coupled Communication in 28 nm FD-SOI CMOS (2021) (1)
A 3-10GHz Ultra-Wideband Pulser (2006) (1)
On the frequency domain analysis of switched capacitor networks including all parasistics (1981) (1)
. " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout (1)
Hyperdimensional computing nanosystem: in-memory computing using monolithic 3D integration of RRAM and CNFET (2020) (1)
Reconfigurable Memory Module in the RAMP System for Stream Processing (2004) (1)
Design and Prototyping of Hard Real Time Systems (1990) (1)
Power and Energy Basics (2009) (1)
Piezoelectric Converter Test Results (2004) (1)
Silicon compilation and design synthesis for digital systems (1989) (1)
Incremental Learning in Multiple Limb Positions for Electromyography-Based Gesture Recognition using Hyperdimensional Computing (2021) (1)
Semantic swarm (2015) (1)
Circuits and Technologies for Wireless Sensor Networks (2006) (1)
“Green codes with short wires at the decoder: Fundamental limits and constructions” (2011) (1)
EDA challenges and options: Investing for the future (2010) (1)
Vela Project on Collaborative Distributed Design: New Client/serverimplementations (university-booth Demos at Dac'99, June 22-24) (1999) (1)
LINK LAYER DESIGN FOR WIRELESS SENSOR NETWORKS (2001) (1)
Optimizing Power @ Design Time - Memory (2009) (1)
Electrostatic Converter Design (2004) (0)
Always energy-optimal microscopic wireless systems (2010) (0)
Low-power heterogeneous reconfigurable digital signal processors with energy-efficient interconnect network (2004) (0)
Randomized Sleeping for Energy Conservation and Robustness in Dense Sensor Networks (2003) (0)
Bio-Inspired On-Chip Sensory Processing (2011) (0)
Towards Wireless Flexible Printed Wearable Sensors (2019) (0)
Wireless in the home - opportunities and challenges (2006) (0)
Resurrection of 5G: In defense of Massive MIMO (2016) (0)
Summary and Perspectives (2009) (0)
The emerging field of bioelectronic medicine seeks methods for deciphering and modulating electrophysiological activity (2016) (0)
An information-theoretic framework for joint architectural and circuit level optimization for olfactory recognition processing (2011) (0)
The Dual Bit Type Method (1995) (0)
Session details: Wireless platforms: GOPS for cents and milliwatts (2005) (0)
Ultralow-Power Design in Near-Threshold Region New basic logic that selects between possible output values using a sense amplifier may be able to dramatically improve ultralow-power system performance. (2010) (0)
A wearable biosensing system with in-sensor adaptive machine learning for hand gesture recognition (2020) (0)
Optimizing Power @ Design Time – Architecture, Algorithms, and Systems (2009) (0)
Session details: Special session: emerging directions in wireless (2005) (0)
A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates (2018) (0)
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures (1994) (0)
Throughput of wireless networks of untuned radios (2005) (0)
Design and characterization of a 65nm CMOS wireless RFID reader for ECoG tag (2017) (0)
AFRL-RY-WP-TR-2009-1172 WAFER SCALE DISTRIBUTED RADIO (2009) (0)
All Systems Go (2010) (0)
Computer aided design of switched capacitor circuits using the DIANA program (1981) (0)
Brain-inspired interconnect architectures and technologies (2016) (0)
A 213-nW/Channel Analog Euclidian Vector Normalizer (2018) (0)
Channel Gain for a Wrist-to-Arm Scenario in the 55-65 GHz Frequency Band (2019) (0)
ANALYSIS AND DESIGN OF THE DATA-LINK LAYER IN WIRELESS SENSOR NETWORKS (2004) (0)
Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata (2022) (0)
5th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2013, Bari, Italy, June 13-14, 2013 (2013) (0)
Low-power design tools—where is the impact? (panel) (1997) (0)
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies (2022) (0)
Reshaping EDA for power (2003) (0)
Systems on Nanoscale Information fabriCs Outcomes and Future Prospects (2018) (0)
Session details: Reshaping EDA for power (2003) (0)
Architecting the Human Intranet (2021) (0)
Optimizing Power @ Standby – Circuits and Systems (2009) (0)
The Design of an Analog Associative Memory Circuit for Applications in High-Dimensional Computing (2018) (0)
Design methodology for run-time management of reconfigurable digital signal processor systems (2006) (0)
Computing at the Crossroads (And What Does it Mean to Verification and Test?) (2008) (0)
A VLSI grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system (1991) (0)
Hyperdimensional Computing for Blind and One-Shot Classification of EEG Error-Related Potentials (2017) (0)
CIRCUITS AND TECHNOLOGIES FOR WIRELESS SENSING (2007) (0)
SSCS Distinguished Lecture - 1 The Innovation is in the Mind - The Converging Trajectories of IT, Neuro and Nano (2014) (0)
A/D architectures of the future (1985) (0)
Is“Network” the Next “Big Idea” in Design? (2006) (0)
EDA in flux - Should I stay or should I go? (2009) (0)
Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead (2013) (0)
Implementation & synthesis of V.L.S.I. signal processing systems (1992) (0)
Fast prototyping of real time systems: A new challenge? (1993) (0)
Human-Centric Computing (2021) (0)
Chapter 4 Optimizing Power @ Design Time – Circuit-Level Techniques (2009) (0)
Mobile Communications (1996) (0)
Reducing the implant footprint: low-area neural recording (2015) (0)
Optimizing Power @ Runtime – Circuits and Systems (2009) (0)
Guest editor's introduction design environments for DSP (1995) (0)
The path toward energy-efficient inference engine architectures on scaled and beyond-CMOS fabrics (2013) (0)
Bluetooth Control Interface for the PicoRadio Network Muhua Pang (2000) (0)
INSTRUCTION SET APPING FOR PERFORMANCE OPTIMIZATION (1993) (0)
A CAD environment for Real-time DSP implementations on multiprocessors (1994) (0)
Electrostatic Converter Test Results (2004) (0)
Optimizing Power @ Design Time – Interconnect and Clocks (2009) (0)
Blind parallel interrogation of ultrasonic neural dust motes based on canonical polyadic decomposition: A simulation study (2017) (0)
System-ona-Chip-A Platform Perspective (2002) (0)
Application and Network Support for InfoPad A low-power, lightweight unit to provide ubiquitous information access (1996) (0)
1997 EECS/ERL research summary (1997) (0)
A MEMS-Enabled Two-Receiver Chipset for Asynchronous Networks (2013) (0)
Ba˘ glanirlik Aracili˘ gi ˙¸in K¨ ut ¨ uphane Deste˘ gi Library Support For Connectivity Brokerage (2011) (0)
Session details: Panel (2008) (0)
EnergyHarvesting - ASystems Perspective (2007) (0)
Adaptivity to Enable an Efficient and Robust Human Intranet (2018) (0)
Low Power Synchronization for Wireless Communication Abstract Low Power Synchronization for Wireless Communication (2004) (0)
EE2: Intelligent machines: Will the technological singularity happen? (2017) (0)
Architecting the Human Intranet (2021) (0)
Microscopic wireless - Exploring the boundaries of ultra low-power design (2009) (0)
A probability-inspired normalization for fixed-precision Hyper-Dimensional Computing (2022) (0)
System Design and Analysis Overview (2003) (0)
Chapter 10 Optimizing Power @ Runtime – Circuits and Systems (2009) (0)
The innovation is in the minds (2013) (0)
Wireless Platforms: GOPS for Cents and Milliwatts Organizer: (2005) (0)
Powering and communication for OMNI: A distributed and modular closed-loop neuromodulation device. (2016) (0)
Library support for connectivity brokerage (2011) (0)
Session details: Will power kill FPGAs? (2006) (0)
Introduction (2005) (0)
Brain-inspired Multi-level Control of an Assistive Prosthetic Hand through EMG Task Recognition (2022) (0)
ADPCM ON TENSILICA (0)
Data pass synthesizing method and bilt-in self repair realizing hardware circuit (1994) (0)
Logic and Interconnect Architecture (2001) (0)
Distributed os for sensor networks (2007) (0)
Power Dissipation in FPGAs (2001) (0)
Surface-Mounted Parallel-Plate Coupler for Cylindric Dielectric Waveguides (2022) (0)
Are we ready for system-level synthesis? (2005) (0)
Session details: Development of processors and communication networks for embedded systems (2002) (0)
Session details: What's the Next EDA Driver? (2002) (0)
SSCS elects five AdCom members (2004) (0)
Fabrication of Electrostatic Converters (2004) (0)
Of Brains and Computers (2021) (0)
1 . 0 Introduction 1 . 1 Motivation : Design Space Exploration (2007) (0)
MultiPADDI-2 board for image processing (1997) (0)
Chapter # EMBEDDED SYSTEM DESIGN USING UML AND PLATFORMS (2001) (0)
Swarm Technology (2015) (0)
Spatially Distributed Semi-Passive Backscattering Platform for Biomedical Application (2019) (0)
R-1: Special Evening Session: "Energy Efficiency: How is 'Green' Implemented in Reality?" (2009) (0)
Chapter 6 Optimizing Power @ Design Time – Interconnect and Clocks (2009) (0)
System-level power estimation and optimization-challenges and perspectives (1997) (0)
Simulation of Analog Sampled-Data MOSLSI Circuits (1984) (0)
SSCS AdCom reports (2004) (0)
Design Synthesis and Tools for DSP (1993) (0)
Type Of Integrated Clock Gating Standard Cells (2015) (0)
Nanometer Transistors and Their Models (2009) (0)
Activity - S ensi tive Architectural Pow er Analysis (1996) (0)
[90] G. C. Sih and E.A. Lee, “A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous (1997) (0)
7. CONCLUSION (2002) (0)

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